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1. 发明授权

US07813289B2 Electrical idle detection circuit including input signal rectifier 有权
标题翻译：电气怠速检测电路包括输入信号整流器
公开(公告)号：US07813289B2
公开(公告)日：2010-10-12
申请号：US11346064
申请日：2006-02-02
申请人： Hamid Partovi , Karthik Gopalakrishnan , Luca Ravezzi
发明人： Hamid Partovi , Karthik Gopalakrishnan , Luca Ravezzi
IPC分类号： H04L1/00
CPC分类号： G06F13/4072
摘要： An electrical idle detection circuit including a full wave rectifier and a first amplifier. The full wave rectifier is configured to receive differential input signals and provide a rectified output signal based on the differential input signals. The first amplifier is configured to receive a first input signal based on the rectified output signal and a second input signal based on a reference signal. The first amplifier is configured to provide an output signal that indicates the differential input signals are one of active and in electrical idle based on the first input signal and the second input signal.
摘要翻译：一种包括全波整流器和第一放大器的电怠速检测电路。全波整流器配置为接收差分输入信号，并根据差分输入信号提供整流输出信号。第一放大器被配置为基于经整流的输出信号接收第一输入信号，并且基于参考信号接收第二输入信号。第一放大器被配置为提供输出信号，其基于第一输入信号和第二输入信号来指示差分输入信号是有效和电空闲之一。

2. 发明授权

US07733815B2 Data sampler including a first stage and a second stage 失效
标题翻译：数据采样器包括第一级和第二级
公开(公告)号：US07733815B2
公开(公告)日：2010-06-08
申请号：US11494848
申请日：2006-07-28
申请人： Karthik Gopalakrishnan , Luca Ravezzi , Sivaraman Chokkalingam , Edoardo Prete , Hamid Partovi
发明人： Karthik Gopalakrishnan , Luca Ravezzi , Sivaraman Chokkalingam , Edoardo Prete , Hamid Partovi
IPC分类号： H04B3/52 , H03F3/04
CPC分类号： H03M1/1245
摘要： A data sampler including a first stage and a second stage. The first stage is configured to receive differential signals and provide a first edge rate in a first output signal and a second edge rate in a second output signal based on the differential signals. The second stage is configured to amplify the difference between the first output signal and the second output signal to provide regenerated output signals. The second stage provides a third edge rate in a first internal signal and a fourth edge rate in a second internal signal based on the first edge rate and the second edge rate.
摘要翻译：数据采样器，包括第一级和第二级。第一级被配置为基于差分信号接收差分信号并提供第一输出信号中的第一边沿速率和第二输出信号中的第二边缘速率。第二级被配置为放大第一输出信号和第二输出信号之间的差以提供再生的输出信号。第二级基于第一边沿速率和第二边缘速率，提供第一内部信号中的第三边沿速率和第二内部信号中的第四边缘速率。

3. 发明申请

US20090180335A1 INTEGRATED CIRCUIT WITH REDUCED POINTER UNCERTAINLY 审中-公开
标题翻译：集成电路与减少指针不确定
公开(公告)号：US20090180335A1
公开(公告)日：2009-07-16
申请号：US12014452
申请日：2008-01-15
申请人： Sivaraman Chokkalingam , Hamid Partovi , Luca Ravezzi
发明人： Sivaraman Chokkalingam , Hamid Partovi , Luca Ravezzi
IPC分类号： G11C7/00 , H03L7/00 , G11C8/00
CPC分类号： G11C7/22 , G11C5/00 , G11C7/222 , H03L7/06
摘要： One embodiment provides an integrated circuit including a first circuit and a second circuit. The first circuit is configured to obtain a sample of a first clock via a second clock and provide a selected clock from multiple clocks based on the sample. The second circuit is configured to provide a first pointer clock based on the first clock and a second pointer clock based on the selected clock. An edge of the second pointer clock relative to an edge of the first pointer clock is limited to an uncertainty range of within one-half a first pointer clock cycle.
摘要翻译：一个实施例提供了包括第一电路和第二电路的集成电路。第一电路被配置为经由第二时钟获得第一时钟的采样，并且基于该采样从多个时钟提供选定的时钟。第二电路被配置为基于第一时钟提供第一指针时钟，并且基于所选择的时钟提供第二指针时钟。相对于第一指针时钟的边缘的第二指针时钟的边缘被限制在第一指针时钟周期的二分之一内的不确定性范围。

4. 发明申请

US20090160559A1 INTEGRATED CIRCUIT INCLUDING IMPEDANCE TO PROVIDE SYMMETRICAL DIFFERENTIAL SIGNALS 审中-公开
标题翻译：集成电路，包括阻抗提供对称差分信号
公开(公告)号：US20090160559A1
公开(公告)日：2009-06-25
申请号：US11960036
申请日：2007-12-19
申请人： Luca Ravezzi , Hamid Partovi
发明人： Luca Ravezzi , Hamid Partovi
IPC分类号： H03F3/04
CPC分类号： H03F3/45183 , H03F2203/45148 , H03F2203/45166 , H03H11/32
摘要： One embodiment provides an integrated circuit including an input stage and an impedance. The input stage is configured to receive a single-ended input signal and provide a differential output signal. The impedance is configured to receive the single-ended input signal and provide compensation to the input stage to provide symmetrical differential signals in the differential output signal.
摘要翻译：一个实施例提供了包括输入级和阻抗的集成电路。输入级被配置为接收单端输入信号并提供差分输出信号。阻抗被配置为接收单端输入信号，并向输入级提供补偿，以在差分输出信号中提供对称的差分信号。

5. 发明授权

US6137126A Method to reduce gate-to-local interconnect capacitance using a low dielectric constant material for LDD spacer 有权
标题翻译：使用LDD间隔物的低介电常数材料来减少门到局部互连电容的方法
公开(公告)号：US6137126A
公开(公告)日：2000-10-24
申请号：US375499
申请日：1999-08-17
申请人： Steven C. Avanzino , Minh Van Ngo , Angela T. Hui , Chun Jiang , Hamid Partovi
发明人： Steven C. Avanzino , Minh Van Ngo , Angela T. Hui , Chun Jiang , Hamid Partovi
IPC分类号： H01L21/336 , H01L21/768 , H01L29/49 , H01L29/72 , H01L27/10
CPC分类号： H01L29/6659 , H01L21/76895 , H01L29/4983 , Y10S257/90
摘要： The capacitance between a gate electrode of a transistor and local interconnect is reduced by employing SiC sidewall spacers on the side surfaces of the gate electrode when forming the source/drain regions with shallow extensions. Embodiments include forming SiC sidewall spacers at a width of about 500 .ANG. to about 800 .ANG. having a dielectric constant of less than about 3.2, depositing a silicon oxide inter-dielectric layer, and forming the local interconnect through the inter-dielectric layer. The resulting composite dielectric constant between the gate electrode and local interconnect is about 4.2 to about 4.7.
摘要翻译：当形成具有浅延伸的源极/漏极区域时，通过在栅电极的侧表面上使用SiC侧壁间隔来减小晶体管的栅电极和局部互连之间的电容。实施例包括将SiC侧壁间隔物形成为具有小于约3.2的介电常数的约500安培的宽度至约800安培角，沉积氧化硅介电层，以及通过介电层形成局部互连。栅电极和局部互连之间的所得复合介电常数为约4.2至约4.7。

6. 发明授权

US6081136A Dynamic NOR gates for NAND decode 失效
标题翻译：用于NAND解码的动态NOR门
公开(公告)号：US6081136A
公开(公告)日：2000-06-27
申请号：US993335
申请日：1997-12-19
申请人： Rajesh Khanna , Hamid Partovi
发明人： Rajesh Khanna , Hamid Partovi
IPC分类号： H03K19/096 , H03K19/003
CPC分类号： H03K19/0963
摘要： A NOR gate pair includes a first and second NOR gate, each with a plurality of inputs and an output. A first NAND gate has a first input coupled to the output of the first NOR gate, a second input coupled to the output of the second NOR gate through a first input inverter, and an output. A second NAND gate has a first input coupled to the output of the second NOR gate, a second input coupled to the output of the first NOR gate through a second input inverter, and an output. A first output inverter is coupled to the output of the first NAND gate and a second output inverter is coupled to the output of the second NAND gate. This configuration assures that NOR gates used in a one-hot-decode decoder will all have logic-low outputs during a precharge phase.
摘要翻译： NOR门对包括第一和第二NOR门，每个具有多个输入和输出。第一NAND门具有耦合到第一或非门的输出的第一输入端，通过第一输入反相器耦合到第二或非门的输出的第二输入和输出。第二与非门具有耦合到第二或非门的输出的第一输入，通过第二输入反相器耦合到第一或非门的输出的第二输入和输出。第一输出反相器耦合到第一NAND门的输出，第二输出反相器耦合到第二NAND门的输出。该配置确保在一个热解码解码器中使用的或非门将在预充电阶段期间都具有逻辑低输出。

7. 发明授权

US5966026A Output buffer with improved tolerance to overvoltage 失效
标题翻译：输出缓冲器，具有改善的过压容差
公开(公告)号：US5966026A
公开(公告)日：1999-10-12
申请号：US738598
申请日：1996-10-29
申请人： Hamid Partovi , Matthew P. Crowley
发明人： Hamid Partovi , Matthew P. Crowley
IPC分类号： G05F1/571 , G05F3/24 , H03K19/0185
CPC分类号： G05F1/571 , G05F3/24 , G05F3/242
摘要： An output buffer with improved tolerance to overvoltage conditions. Among other features, especially when in a high-impedance state, the output buffer prevents a leakage path from a pad (108) through a pull-up driver (101) to supply voltage VDD when any voltage above VDD is placed on the pad (108). Further, the output buffer provides improved transient response characteristics. In one embodiment, the output buffer includes a pull-up driver (101), a first tracking transistor (120), a second tracking transistor (122), a voltage bias generator (112), and a coupling capacitor (124).
摘要翻译：输出缓冲器，具有改善的过电压条件容限。尤其是当处于高阻抗状态时，输出缓冲器防止当焊盘（108）上的任何电压放置在焊盘上时从焊盘（108）穿过上拉驱动器（101）的漏电路径供给电压VDD 108）。此外，输出缓冲器提供改进的瞬态响应特性。在一个实施例中，输出缓冲器包括上拉驱动器（101），第一跟踪晶体管（120），第二跟踪晶体管（122），电压偏置发生器（112）和耦合电容器（124）。

8. 发明授权

US08618856B1 Shadow latch 有权
标题翻译：阴影闩锁
公开(公告)号：US08618856B1
公开(公告)日：2013-12-31
申请号：US13077949
申请日：2011-03-31
申请人： Alfred Yeung , Hamid Partovi , John Ngai , Ronen Cohen
发明人： Alfred Yeung , Hamid Partovi , John Ngai , Ronen Cohen
IPC分类号： H03K3/289
CPC分类号： H03K3/013 , H03K3/356121
摘要： A latch device is provided with a driver and a shadow latch. The driver has an input to accept a binary driver input signal, an input to accept a clock signal, and an input to accept a shadow-Q signal. The driver has an output to supply a binary Q signal equal to the inverse of the driver input signal, in response to the driver input signal, the shadow-Q signal, and the clock signal. The shadow latch has an input to accept the driver input signal, and an input to accept the clock signal. The shadow latch has an output to supply the shadow-Q signal equal to the inverted Q signal, in response to the driver input signal and clock signal.
摘要翻译：闩锁装置设置有驱动器和阴影闩锁。驱动器具有接受二进制驱动器输入信号的输入端，接受时钟信号的输入端和接收阴影Q信号的输入端。驱动器具有响应于驱动器输入信号，阴影-Q信号和时钟信号而提供等于驱动器输入信号的倒数的二进制Q信号的输出。阴影锁存器具有接受驱动器输入信号的输入端和接受时钟信号的输入端。阴影锁存器具有响应于驱动器输入信号和时钟信号而提供等于反相Q信号的阴影Q信号的输出。

9. 发明授权

US07480358B2 CDR-based clock synthesis 有权
标题翻译：基于CDR的时钟合成
公开(公告)号：US07480358B2
公开(公告)日：2009-01-20
申请号：US10786879
申请日：2004-02-25
申请人： Hamid Partovi , William P. Evans
发明人： Hamid Partovi , William P. Evans
IPC分类号： H04L7/00
CPC分类号： H03L7/06 , H04L7/0091
摘要： A clock signal can be synthesized by performing a clock and data recovery (CDR) operation on a potentially noisy clock source signal which has a known transition density. The CDR operation produces a desired clock signal in response to the clock source signal. In order to reduce crosstalk between plesiochronous receive and transmit clock domains of a serial data transceiver, a single common PLL is used both to recover the receive clock from the received data and to synthesize the transmit clock from a potentially noisy transmit clock source signal.
摘要翻译：可以通过对具有已知转换密度的潜在噪声时钟源信号执行时钟和数据恢复（CDR）操作来合成时钟信号。 CDR操作响应于时钟源信号产生期望的时钟信号。为了减少串行数据收发器的同步接收和发送时钟域之间的串扰，使用单个公共PLL来从接收到的数据恢复接收时钟，并从潜在的噪声发射时钟源信号合成发送时钟。

10. 发明申请

US20080024215A1 Data sampler including a first stage and a second stage 失效
标题翻译：数据采样器包括第一级和第二级
公开(公告)号：US20080024215A1
公开(公告)日：2008-01-31
申请号：US11494848
申请日：2006-07-28
申请人： Karthik Gopalakrishnan , Luca Ravezzi , Sivaraman Chokkalingam , Edoardo Prete , Hamid Partovi
发明人： Karthik Gopalakrishnan , Luca Ravezzi , Sivaraman Chokkalingam , Edoardo Prete , Hamid Partovi
IPC分类号： H03F3/04
CPC分类号： H03M1/1245
摘要： A data sampler including a first stage and a second stage. The first stage is configured to receive differential signals and provide a first edge rate in a first output signal and a second edge rate in a second output signal based on the differential signals. The second stage is configured to amplify the difference between the first output signal and the second output signal to provide regenerated output signals. The second stage provides a third edge rate in a first internal signal and a fourth edge rate in a second internal signal based on the first edge rate and the second edge rate.
摘要翻译：数据采样器，包括第一级和第二级。第一级被配置为基于差分信号接收差分信号并提供第一输出信号中的第一边沿速率和第二输出信号中的第二边缘速率。第二级被配置为放大第一输出信号和第二输出信号之间的差以提供再生的输出信号。第二级基于第一边沿速率和第二边缘速率，提供第一内部信号中的第三边沿速率和第二内部信号中的第四边缘速率。

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