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1. 发明授权

US07594158B2 Parity error checking and compare using shared logic circuitry in a ternary content addressable memory 有权
标题翻译：在三元内容可寻址存储器中使用共享逻辑电路进行奇偶校验错误检查和比较
公开(公告)号：US07594158B2
公开(公告)日：2009-09-22
申请号：US11213367
申请日：2005-08-26
申请人： John Wickeraad
发明人： John Wickeraad
IPC分类号： H03M13/00
CPC分类号： G06F11/1064 , G11C15/04
摘要： Methods and apparatus for performing, using smaller, more efficient shared logic circuitry, the parity checking function and the compare function in a mutually exclusive manner in different cycles of a ternary content addressable memory are disclosed.
摘要翻译：公开了在三元内容可寻址存储器的不同周期中以相互排斥的方式执行使用较小的更有效的共享逻辑电路的奇偶校验功能和比较功能的方法和装置。

2. 发明申请

US20060176899A1 Support chip for handling network chips on a network device 有权
标题翻译：支持在网络设备上处理网络芯片的芯片
公开(公告)号：US20060176899A1
公开(公告)日：2006-08-10
申请号：US11054646
申请日：2005-02-08
申请人： Bruce Lavigne , John Wickeraad , Lewis Kootstra , Jonathan Watts
发明人： Bruce Lavigne , John Wickeraad , Lewis Kootstra , Jonathan Watts
IPC分类号： H04J3/22
CPC分类号： H04L49/65 , H04L49/109
摘要： Network devices and methods are provided involving a support chip in association with network chips. One embodiment includes a network device having a processor, a high speed interconnect, and a number of network chips coupled to one another through the high speed interconnect. The number of network chips include a conduit port which can be selectively chosen to exchange packets, received to the number of network chips, with the processor. The support chip is coupled to the number of network chips in association with selecting a conduit port on one of the number of network chips to exchange packets with the processor.
摘要翻译：提供了涉及与网络芯片相关联的支持芯片的网络设备和方法。一个实施例包括具有处理器，高速互连以及通过高速互连彼此耦合的多个网络芯片的网络设备。网络芯片的数量包括可以选择性地选择以与处理器交换接收到数量的网络芯片的分组的导管端口。支持芯片与多个网络芯片耦合，与在多个网络芯片中的一个网络芯片上选择一个导线端口，以与处理器交换分组。

3. 发明申请

US20070234182A1 Error checking and correction (ECC) system and method 有权
标题翻译：错误检查和纠正（ECC）系统和方法
公开(公告)号：US20070234182A1
公开(公告)日：2007-10-04
申请号：US11394949
申请日：2006-03-31
申请人： John Wickeraad , King Luk
发明人： John Wickeraad , King Luk
IPC分类号： G11C29/00
CPC分类号： G06F11/1008 , G11C5/04 , G11C2029/1806
摘要： A method stores data and check bits for that data within a memory chip. The memory chip stores the data and check bits in a plurality of pages contained in the memory chip, each page including a plurality of storage locations with each storage location having an associated address. The method includes receiving data to be stored in the memory, calculating check bits for the received data, mapping the data to addresses associated with the storage locations in a given page in the memory chip, mapping the check bits to addresses associated with the storage locations contained in the same page as the data, and storing the data and check bits in the page. The method may be applied to a single memory chip or to multiple memory chips.
摘要翻译：一种方法将存储器芯片内的该数据的数据和校验位存储。存储器芯片将包含在存储器芯片中的多个页面中的数据和校验位存储，每个页面包括多个存储位置，每个存储位置具有相关联的地址。该方法包括接收要存储在存储器中的数据，计算接收到的数据的校验位，将数据映射到与存储器芯片中的给定页面中的存储位置相关联的地址，将校验位映射到与存储位置相关联的地址包含在与数据相同的页面中，并且将数据和校验位存储在页面中。该方法可以应用于单个存储器芯片或多个存储器芯片。

4. 发明申请

US20070061692A1 Parallel parity checking for content addressable memory and ternary content addressable memory 有权
标题翻译：内容可寻址存储器和三元内容可寻址存储器的并行奇偶校验
公开(公告)号：US20070061692A1
公开(公告)日：2007-03-15
申请号：US11207387
申请日：2005-08-18
申请人： John Wickeraad
发明人： John Wickeraad
IPC分类号： G06F11/00 , H03M13/00
CPC分类号： G06F11/1064
摘要： Methods and arrangements for parallel parity checking for content addressable memory and ternary content addressable memory during compare cycles are disclosed. Further, methods and arrangements for remedying storage bit corruption are also disclosed.
摘要翻译：公开了在比较周期期间用于内容可寻址存储器和三元内容可寻址存储器的并行奇偶校验的方法和装置。此外，还公开了用于补救存储位损坏的方法和布置。

5. 发明申请

US20060242543A1 Packet protection for header modification 有权
标题翻译：分组保护用于报头修改
公开(公告)号：US20060242543A1
公开(公告)日：2006-10-26
申请号：US11102973
申请日：2005-04-11
申请人： Bruce LaVigne , John Wickeraad , Jonathan Watts
发明人： Bruce LaVigne , John Wickeraad , Jonathan Watts
IPC分类号： H03M13/00
CPC分类号： H04L1/0045 , H04L1/0061 , H04L1/0072 , H04L2001/0098
摘要： Systems, methods, and devices are disclosed that provide packet protection for header modification. One method includes receiving a packet to a computing device. The method includes apply error checking techniques independently to different portions of the packet.
摘要翻译：公开了提供用于报头修改的分组保护的系统，方法和设备。一种方法包括向计算设备接收分组。该方法包括独立地对分组的不同部分应用错误检查技术。

6. 发明申请

US20060215432A1 TCAM BIST with redundancy 有权
公开(公告)号：US20060215432A1
公开(公告)日：2006-09-28
申请号：US11092028
申请日：2005-03-28
申请人： John Wickeraad , Jonathan Greenlaw
发明人： John Wickeraad , Jonathan Greenlaw
IPC分类号： G11C15/00
CPC分类号： G11C29/816 , G11C15/00 , G11C29/44 , G11C29/76
摘要： In an embodiment of the invention, a method of providing redundancy in a ternary content addressable memory (TCAM) includes: detecting a defective entry in a ternary content addressable memory (TCAM); marking the defective entry so that the defective entry is visible to a software; and avoiding in using the defective entry. For data that normally would have been written into the defective entry, the data is written into an entry that is subsequent to the defective entry. In another embodiment, the redundancy is provided in a CAM instead of a TCAM.

7. 发明申请

US20060190757A1 Monitoring multiple clock domains 审中-公开
标题翻译：监控多个时钟域
公开(公告)号：US20060190757A1
公开(公告)日：2006-08-24
申请号：US11062572
申请日：2005-02-22
申请人： John Wickeraad
发明人： John Wickeraad
IPC分类号： G06F1/04
CPC分类号： G01R31/31725
摘要： Methods, systems, and circuits are provided for monitoring multiple clock domains. One method for monitoring multiple clock domains includes pipelining different sets of signals from different clock domains on an application specific integrated circuit (ASIC) to a particular input/output (I/O) port on the ASIC using an associated clock from each different clock domain, and selecting a particular set of signals from among the different sets of signals to send out of the particular I/O port.
摘要翻译：提供了方法，系统和电路，用于监视多个时钟域。用于监视多个时钟域的一种方法包括使用专用集成电路（ASIC）上的不同时钟域向ASIC上的特定输入/输出（I / O）端口流水线不同的信号集合，使用来自每个不同时钟域的关联时钟并且从不同的信号组中选择特定的一组信号以从特定的I / O端口发出。

8. 发明申请

US20060187913A1 Conduit port for network chips 有权
标题翻译：网络芯片导管口
公开(公告)号：US20060187913A1
公开(公告)日：2006-08-24
申请号：US11051422
申请日：2005-02-04
申请人： Bruce LaVigne , John Wickeraad , Lewis Kootstra , Jonathan Watts
发明人： Bruce LaVigne , John Wickeraad , Lewis Kootstra , Jonathan Watts
IPC分类号： H04L12/56
CPC分类号： H04L12/56
摘要： Network devices and methods are provided for device monitoring. One embodiment includes a network device having a processor, a high speed interconnect and a number of network chips. The number of network chips are coupled to one another through the high speed interconnect. The number of network chips have a conduit port which can be selectively chosen to exchange packets, received to any network chip, with the processor.
摘要翻译：提供网络设备和方法进行设备监控。一个实施例包括具有处理器，高速互连和多个网络芯片的网络设备。网络芯片的数量通过高速互连彼此耦合。网络芯片的数量具有可以选择性地选择以将接收到任何网络芯片的分组与处理器交换的导管端口。

9. 发明申请

US20120110656A1 SELECTIVE INVALIDATION OF PACKET FILTERING RESULTS 有权
标题翻译：分组筛选结果的选择性无效
公开(公告)号：US20120110656A1
公开(公告)日：2012-05-03
申请号：US12938090
申请日：2010-11-02
申请人： Jose Renato Santos , Yoshio Turner , John Wickeraad
发明人： Jose Renato Santos , Yoshio Turner , John Wickeraad
IPC分类号： G06F21/20
CPC分类号： H04L63/0263
摘要： Example embodiments relate to selective invalidation of packet filtering cache results based on rule priority. In example embodiments, a network node determines whether a rule identifier included in a cache entry of a cache of results of a packet filtering rule set is of a higher priority than a highest priority rule corresponding to a rule set version identifier included in the cache entry. If so, the network node may apply an action included in the cache entry.
摘要翻译：示例性实施例涉及基于规则优先级的分组过滤高速缓存结果的选择性无效。在示例实施例中，网络节点确定包过滤规则集的结果的高速缓存的高速缓存条目中包括的规则标识符是否高于与包括在高速缓存条目中的规则集版本标识符相对应的最高优先级规则。如果是，则网络节点可以应用包括在高速缓存条目中的动作。

10. 发明申请

US20060190758A1 Signals crossing multiple clock domains 失效
标题翻译：信号穿越多个时钟域
公开(公告)号：US20060190758A1
公开(公告)日：2006-08-24
申请号：US11063274
申请日：2005-02-22
申请人： John Wickeraad
发明人： John Wickeraad
IPC分类号： G06F1/04
CPC分类号： G01R31/31727 , G06F11/3632 , G06F11/3648
摘要： Methods, systems, and circuits are provided for signals crossing multiple clock domains. One circuit includes a number of different clock domains located on different portions of the ASIC. A number of input/output (I/O) ports are provided to couple signals to and from the ASIC. The circuit includes means for moving internal signals from a subset of the number of different clock domains of multiple frequencies to a different clock domain for monitoring, observation, counting, and debug.
摘要翻译：为跨越多个时钟域的信号提供了方法，系统和电路。一个电路包括位于ASIC的不同部分上的多个不同的时钟域。提供多个输入/输出（I / O）端口以将信号耦合到ASIC和从ASIC耦合信号。电路包括用于将来自多个频率的不同时钟域的数量的子集的内部信号移动到用于监视，观察，计数和调试的不同时钟域的装置。

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