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1. 发明授权

US08675409B2 Non-volatile memory devices 有权
标题翻译：非易失性存储器件
公开(公告)号：US08675409B2
公开(公告)日：2014-03-18
申请号：US13463060
申请日：2012-05-03
申请人： Jong-Sun Sel , Jung-Dal Choi , Young-Woo Park , Jin-Taek Park
发明人： Jong-Sun Sel , Jung-Dal Choi , Young-Woo Park , Jin-Taek Park
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/0483 , G11C16/3427
摘要： A non-volatile memory device may include a semiconductor substrate including an active region at a surface thereof, a ground select line crossing the active region, and a string select line crossing the active region and spaced apart from the ground select line. A plurality of memory cell word lines may cross the active region between the ground select line and the string select line with about a same first spacing provided between adjacent ones of the plurality of word lines and between a last of the plurality of memory cell word lines and the string select line. A second spacing may be provided between the ground select line and a first of the plurality of memory cell word lines.
摘要翻译：非易失性存储器件可以包括半导体衬底，其包括其表面处的有源区，与有源区交叉的接地选择线，以及与有源区交叉并与地选线相隔的串选择线。多个存储单元字线可以与地线选择线和弦选择线之间的有源区域相交，并且与多个字线中的相邻字线之间以及多个存储单元字线中的最后一个之间提供大致相同的第一间隔和字符串选择行。可以在接地选择线和多个存储单元字线中的第一个之间提供第二间隔。

2. 发明授权

US08558283B2 Semiconductor device including dummy 有权
标题翻译：半导体器件包括虚拟
公开(公告)号：US08558283B2
公开(公告)日：2013-10-15
申请号：US12794809
申请日：2010-06-07
申请人： Jong-sun Sel , Nam-su Lim , In-wook Oh
发明人： Jong-sun Sel , Nam-su Lim , In-wook Oh
IPC分类号： H01L23/48
CPC分类号： H01L23/522 , H01L21/76816 , H01L23/5226 , H01L27/0207 , H01L27/11519 , H01L27/11521 , H01L27/11524 , H01L27/11565 , H01L27/11568 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device or a memory which includes the same have a line pattern, and a contact plug, the line pattern including a first linear feature to which the contact plug is connected by design, and a second linear feature having a connecting portion and a dummy portion adjacent the location at which the contact plug is electrically connected to the first linear feature. A second contact plug is electrically connected to the connecting portion of the second linear feature of the line pattern. In the case of a misalignment error or the like, the first contact plug may also be electrically connected to the second linear feature of the line pattern but at the dummy portion thereof so as to not create a short circuit in that case. The dummy portion thus allows a sufficiently large process margin to be secured for the contact plug.
摘要翻译：包括该图案的半导体器件或存储器具有线图案和接触插头，该线图案包括接触插头通过设计连接到其上的第一线性特征，以及具有连接部分和虚拟的第二线性特征邻近接触插头电连接到第一线性特征的位置的部分。第二接触插塞电连接到线路图案的第二线性特征的连接部分。在不对准误差等的情况下，第一接触插塞也可以电连接到线路图案的第二线性特征，但是在其虚拟部分处，以便在这种情况下不产生短路。因此，虚拟部分可以确保接触插头足够大的工艺余量。

3. 发明授权

US08188532B2 Semiconductor device having a gate contact structure capable of reducing interfacial resistance 有权
标题翻译：具有能够降低界面电阻的栅极接触结构的半导体器件
公开(公告)号：US08188532B2
公开(公告)日：2012-05-29
申请号：US12856295
申请日：2010-08-13
申请人： Chang-Seok Kang , Yoo-Cheol Shin , Jung-Dal Choi , Jong-Sun Sel , Ju-Hyung Kim , Sang-Hun Jeon
发明人： Chang-Seok Kang , Yoo-Cheol Shin , Jung-Dal Choi , Jong-Sun Sel , Ju-Hyung Kim , Sang-Hun Jeon
IPC分类号： H01L29/788
CPC分类号： H01L27/11521 , H01L21/823462 , H01L21/823475 , H01L27/115 , H01L27/11524 , H01L29/7883
摘要： A semiconductor device has a gate contact structure, including a semiconductor substrate, a polycrystalline silicon layer used as a gate electrode of a transistor, a middle conductive layer, a top metal layer having an opening exposing the polycrystalline silicon layer, and a contact plug directly contacting the polycrystalline silicon layer through the opening.
摘要翻译：半导体器件具有栅极接触结构，包括半导体衬底，用作晶体管的栅电极的多晶硅层，中间导电层，具有暴露多晶硅层的开口的顶部金属层和直接接触的插塞使多晶硅层通过开口接触。

4. 发明申请

US20110031559A1 SEMICONDUCTOR DEVICES IN WHICH A CELL GATE PATTERN AND A RESISTOR PATTERN ARE FORMED OF A SAME MATERIAL AND METHODS OF FORMING THE SAME 审中-公开
标题翻译：细胞栅格图案和电阻图案的半导体器件形成相同的材料及其形成方法
公开(公告)号：US20110031559A1
公开(公告)日：2011-02-10
申请号：US12905517
申请日：2010-10-15
申请人： Jong-Sun Sel , Jung-Dal Choi
发明人： Jong-Sun Sel , Jung-Dal Choi
IPC分类号： H01L27/06
CPC分类号： H01L27/0629 , H01L27/105 , H01L27/11526 , H01L27/11568 , H01L28/20
摘要： A semiconductor device is formed by providing a semiconductor substrate comprising a cell region, a peripheral circuit region, and a resistor region, forming a device isolation layer on the semiconductor substrate so as to define an active region, forming a first insulating layer and a polysilicon pattern on the active region of the peripheral circuit region, forming a second insulating layer, a charge storage layer, and a third insulating layer on the active region of the cell region, farming a conductive layer on the semiconductor substrate, and patterning the conductive layer to form conductive patterns on the third insulating layer of the cell region, the polysilicon pattern of the active region of peripheral circuit region, and the semiconductor substrate of the resistor region, respectively.
摘要翻译：通过提供包括单元区域，外围电路区域和电阻器区域的半导体衬底形成半导体器件，在半导体衬底上形成器件隔离层以限定有源区，形成第一绝缘层和多晶硅在外围电路区域的有源区上形成图案，在单元区域的有源区上形成第二绝缘层，电荷存储层和第三绝缘层，在半导体衬底上耕作导电层，并且使导电层以在单元区域的第三绝缘层上形成导电图案，分别形成外围电路区域的有源区域的多晶硅图案和电阻器区域的半导体衬底。

5. 发明授权

US07816245B2 Method of forming semiconductor devices in which a cell gate pattern and a resistor pattern are formed of a same material 有权
标题翻译：形成其中单元栅极图案和电阻器图案由相同材料形成的半导体器件的方法
公开(公告)号：US07816245B2
公开(公告)日：2010-10-19
申请号：US11648992
申请日：2007-01-03
申请人： Jong-Sun Sel , Jung-Dal Choi
发明人： Jong-Sun Sel , Jung-Dal Choi
IPC分类号： H01L21/3205
CPC分类号： H01L27/0629 , H01L27/105 , H01L27/11526 , H01L27/11568 , H01L28/20
摘要： A semiconductor device is formed by providing a semiconductor substrate comprising a cell region, a peripheral circuit region, and a resistor region, forming a device isolation layer on the semiconductor substrate so as to define an active region, forming a first insulating layer and a polysilicon pattern on the active region of the peripheral circuit region, forming a second insulating layer, a charge storage layer, and a third insulating layer on the active region of the cell region, forming a conductive layer on the semiconductor substrate, and patterning the conductive layer to form conductive patterns on the third insulating layer of the cell region, the polysilicon pattern of the active region of peripheral circuit region, and the semiconductor substrate of the resistor region, respectively.
摘要翻译：通过提供包括单元区域，外围电路区域和电阻器区域的半导体衬底形成半导体器件，在半导体衬底上形成器件隔离层以限定有源区，形成第一绝缘层和多晶硅在外围电路区域的有源区上形成图案，在单元区域的有源区上形成第二绝缘层，电荷存储层和第三绝缘层，在半导体衬底上形成导电层，并且使导电层以在单元区域的第三绝缘层上形成导电图案，分别形成外围电路区域的有源区域的多晶硅图案和电阻器区域的半导体衬底。

6. 发明授权

US07666717B2 Non-volatile memory devices including fuse covered field regions 失效
标题翻译：非易失性存储器件包括保险丝覆盖的场区域
公开(公告)号：US07666717B2
公开(公告)日：2010-02-23
申请号：US11538839
申请日：2006-10-05
申请人： Jong-Sun Sel , Sung-Nam Chang , Dae-Woong Kang , Bong-Tae Park
发明人： Jong-Sun Sel , Sung-Nam Chang , Dae-Woong Kang , Bong-Tae Park
IPC分类号： H01L21/82
CPC分类号： H01L27/11521 , H01L23/5258 , H01L27/115 , H01L2924/0002 , H01L2924/00
摘要： A non-volatile device includes a semiconductor substrate having a fuse window region. At least one fuse crosses the fuse window region. Field regions are arranged outside of the fuse window region and arranged under end portions of the at least one fuse. An isolation layer is configured to isolate the field regions. A fuse insulating layer is interposed between the at least one fuse and the field regions.
摘要翻译：非易失性器件包括具有熔丝窗口区域的半导体衬底。至少有一个保险丝穿过保险丝窗口区域。场区域布置在保险丝窗口区域的外部并且布置在至少一个保险丝的端部下方。隔离层被配置为隔离场区域。保险丝绝缘层介于至少一个保险丝和场区之间。

7. 发明授权

US07645644B2 Data line layout in semiconductor memory device and method of forming the same 有权
标题翻译：半导体存储器件中的数据线布局及其形成方法
公开(公告)号：US07645644B2
公开(公告)日：2010-01-12
申请号：US12113994
申请日：2008-05-02
申请人： Jong-Sun Sel , Jung-Dal Choi
发明人： Jong-Sun Sel , Jung-Dal Choi
IPC分类号： H01L21/82
CPC分类号： H01L27/115 , H01L27/105 , H01L27/1052
摘要： In one aspect, a semiconductor device is provided which includes a data block including M parallel and sequentially arranged data lines numbered {0, 1, 2, . . . n, n+1, . . . , m−1, m}, where M, n and m are positive integers, and where n
摘要翻译：在一个方面，提供了一种半导体器件，其包括数据块，该数据块包括M个并行且顺序排列的数字线，编号为{0,1,2。。。 n，n + 1，。。。，m-1，m}，其中M，n和m是正整数，并且其中n

8. 发明授权

US07605430B2 Nonvolatile memory devices having a fin shaped active region and methods of fabricating the same 失效
标题翻译：具有鳍状有源区的非易失性存储器件及其制造方法
公开(公告)号：US07605430B2
公开(公告)日：2009-10-20
申请号：US11474699
申请日：2006-06-23
申请人： Chang-Hyun Lee , Jung-Dal Choi , Chang-Seok Kang , Yoo-Cheol Shin , Jong-Sun Sel
发明人： Chang-Hyun Lee , Jung-Dal Choi , Chang-Seok Kang , Yoo-Cheol Shin , Jong-Sun Sel
IPC分类号： H01L29/76
CPC分类号： H01L27/115 , H01L27/11521
摘要： A nonvolatile memory device includes a semiconductor substrate and a device isolation layer on the semiconductor substrate. A fin-shaped active region is formed between portions of the device isolation layer. A sidewall protection layer is formed on the sidewall of the fin-shaped active region where source and drain regions are formed. Thus, it may be possible to reduce the likelihood of an undesirable connection between an interconnection layer connected to the source and drain regions and a lower sidewall of the active region so that charge leakage from the interconnection layer to a substrate can be prevented or reduced. The sidewall protection layer may be formed using the device isolation layer. Alternatively, an insulating layer having an etch selectivity with respect to an interlayer insulating layer may be formed on the device isolation layer so as to cover the sidewall of the active region.
摘要翻译：非易失性存储器件包括半导体衬底和半导体衬底上的器件隔离层。翅片形有源区形成在器件隔离层的各部分之间。侧壁保护层形成在形成源区和漏区的鳍状有源区的侧壁上。因此，可以降低连接到源极和漏极区域的互连层和有源区域的下侧壁之间的不期望的连接的可能性，从而可以防止或减少从互连层到衬底的电荷泄漏。侧壁保护层可以使用器件隔离层形成。或者，可以在器件隔离层上形成具有相对于层间绝缘层的蚀刻选择性的绝缘层，以覆盖有源区的侧壁。

9. 发明授权

US07572684B2 Nonvolatile memory devices and methods of forming the same 失效
标题翻译：非易失存储器件及其形成方法
公开(公告)号：US07572684B2
公开(公告)日：2009-08-11
申请号：US11646217
申请日：2006-12-27
申请人： Jung-Dal Chol , Jong-Sun Sel , Chang-Seok Kang
发明人： Jung-Dal Chol , Jong-Sun Sel , Chang-Seok Kang
IPC分类号： H01L21/335
CPC分类号： H01L21/823462 , H01L21/823456 , H01L21/823475 , H01L27/105 , H01L27/11526 , H01L27/11529 , H01L27/11546 , Y10S257/903
摘要： Nonvolatile memory devices, and methods of forming the same are disclosed. A memory device includes a substrate having a cell region, a low voltage region and a high voltage region. A ground selection transistor, a string selection transistor and a cell transistor are in the cell region, a low voltage transistor is in the low voltage region, and a high voltage transistor is in the high voltage region. A common source contact is on the ground selection transistor and a low voltage contact is on the low voltage transistor. A bit line contact is on the string selection transistor, a high voltage contact is on the high voltage transistor, and a bit line is on the bit line contact. A first insulating layer is on the substrate, and a second insulating layer is on the first insulating layer. The common source contact and the first low voltage contact extend to a height of the first insulating layer, and the bit line contact and the first high voltage contact extend to a height of the second insulating layer.
摘要翻译：公开了非易失性存储器件及其形成方法。存储器件包括具有单元区域，低电压区域和高电压区域的衬底。接地选择晶体管，串选择晶体管和单元晶体管在单元区域中，低电压晶体管处于低电压区域，高压晶体管处于高电压区域。公共源触点位于接地选择晶体管上，低压触点位于低压晶体管上。串行选择晶体管上有一个位线接点，高电压晶体管上有高压触点，位线接触位线。第一绝缘层在基板上，第二绝缘层位于第一绝缘层上。共源极接触和第一低电压接触延伸到第一绝缘层的高度，并且位线接触和第一高电压接触延伸到第二绝缘层的高度。

10. 发明申请

US20080206932A1 DATA LINE LAYOUT IN SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FORMING THE SAME 有权
标题翻译：半导体存储器件中的数据线布局及其形成方法
公开(公告)号：US20080206932A1
公开(公告)日：2008-08-28
申请号：US12113994
申请日：2008-05-02
申请人： Jong-Sun SEL , Jung-Dal CHOI
发明人： Jong-Sun SEL , Jung-Dal CHOI
IPC分类号： H01L21/82
CPC分类号： H01L27/115 , H01L27/105 , H01L27/1052
摘要： In one aspect, a semiconductor device is provided which includes a data block including M parallel and sequentially arranged data lines numbered {0, 1, 2, . . . n, n+1, . . . , m−1, m}, where M, n and m are positive integers, and where n
摘要翻译：在一个方面，提供了一种半导体器件，其包括数据块，该数据块包括M个并行且顺序排列的数字线，编号为{0,1,2。。。 n，n + 1，。。。，m-1，m}，其中M，n和m是正整数，并且其中n

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