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1. 发明授权

US08045383B2 Non-volatile memory devices including dummy word lines and related structures and methods 有权
标题翻译：包括虚拟字线和相关结构和方法的非易失性存储器件
公开(公告)号：US08045383B2
公开(公告)日：2011-10-25
申请号：US11729169
申请日：2007-03-28
申请人： Jong-Sun Sel , Jung-Dal Choi , Young-Woo Park , Jin-Taek Park
发明人： Jong-Sun Sel , Jung-Dal Choi , Young-Woo Park , Jin-Taek Park
IPC分类号： G11C11/34
CPC分类号： G11C16/0483 , G11C16/3427
摘要： A non-volatile memory device may include a semiconductor substrate including an active region at a surface thereof, a first memory cell string on the active region, and a second memory cell string on the active region. The first memory cell string may include a first plurality of word lines crossing the active region between a first ground select line and a first string select line, and about a same first spacing may be provided between adjacent ones of the first plurality of word lines. The second memory cell string may include a second plurality of word lines crossing the active region between a second ground select line and a second string select line, and about the same first spacing may be provided between adjacent ones of the second plurality of word lines. Moreover, the first ground select line may be between the second ground select line and the first plurality of word lines, and the second ground select line may be between the first ground select line and the second plurality of word lines. Moreover, portions of the active region between the first and second ground select lines may be free of word lines, and a second spacing between the first and second ground select lines may be at least about 3 times greater than the first spacing. Related methods are also discussed.
摘要翻译：非易失性存储器件可以包括半导体衬底，其包括其表面处的有源区，有源区上的第一存储单元串和有源区上的第二存储单元串。第一存储单元串可以包括与第一地选择线和第一串选择线之间的有源区域交叉的第一多个字线，并且可以在第一多个字线中相邻的字线之间提供约相同的第一间隔。第二存储单元串可以包括与第二接地选择线和第二串选择线之间的有源区域交叉的第二多个字线，并且可以在相邻的第二多个字线之间提供约相同的第一间隔。此外，第一接地选择线可以在第二接地选择线和第一多个字线之间，并且第二接地选择线可以在第一接地选择线和第二多个字线之间。此外，第一和第二接地选择线之间的有源区域的部分可以没有字线，并且第一和第二接地选择线之间的第二间隔可以比第一间隔大至少约3倍。还讨论了相关方法。

2. 发明授权

US08198157B2 Methods of forming non-volatile memory devices including dummy word lines 有权
标题翻译：形成包括虚拟字线的非易失性存储器件的方法
公开(公告)号：US08198157B2
公开(公告)日：2012-06-12
申请号：US13236913
申请日：2011-09-20
申请人： Jong-Sun Sel , Jung-Dal Choi , Young-Woo Park , Jin-Taek Park
发明人： Jong-Sun Sel , Jung-Dal Choi , Young-Woo Park , Jin-Taek Park
IPC分类号： H01L21/82 , H01L21/336 , H01L21/4763 , H01L21/44
CPC分类号： G11C16/0483 , G11C16/3427
摘要： A non-volatile memory device may include a semiconductor substrate including an active region at a surface thereof, a first memory cell string on the active region, and a second memory cell string on the active region. The first memory cell string may include a first plurality of word lines crossing the active region between a first ground select line and a first string select line, and about a same first spacing may be provided between adjacent ones of the first plurality of word lines. The second memory cell string may include a second plurality of word lines crossing the active region between a second ground select line and a second string select line, and about the same first spacing may be provided between adjacent ones of the second plurality of word lines. Related methods are also discussed.
摘要翻译：非易失性存储器件可以包括半导体衬底，其包括其表面处的有源区，有源区上的第一存储单元串和有源区上的第二存储单元串。第一存储单元串可以包括与第一地选择线和第一串选择线之间的有源区域交叉的第一多个字线，并且可以在第一多个字线中相邻的字线之间提供约相同的第一间隔。第二存储单元串可以包括与第二接地选择线和第二串选择线之间的有源区域交叉的第二多个字线，并且可以在相邻的第二多个字线之间提供约相同的第一间隔。还讨论了相关方法。

3. 发明申请

US20120045890A1 Methods Of Forming Non-Volatile Memory Devices Including Dummy Word Lines 有权
标题翻译：形成包含虚拟字线的非易失性存储器件的方法
公开(公告)号：US20120045890A1
公开(公告)日：2012-02-23
申请号：US13236913
申请日：2011-09-20
申请人： Jong-Sun Sel , Jung-Dal Choi , Young-Woo Park , Jin-Taek Park
发明人： Jong-Sun Sel , Jung-Dal Choi , Young-Woo Park , Jin-Taek Park
IPC分类号： H01L21/28
CPC分类号： G11C16/0483 , G11C16/3427
摘要： A non-volatile memory device may include a semiconductor substrate including an active region at a surface thereof, a first memory cell string on the active region, and a second memory cell string on the active region. The first memory cell string may include a first plurality of word lines crossing the active region between a first ground select line and a first string select line, and about a same first spacing may be provided between adjacent ones of the first plurality of word lines. The second memory cell string may include a second plurality of word lines crossing the active region between a second ground select line and a second string select line, and about the same first spacing may be provided between adjacent ones of the second plurality of word lines. Related methods are also discussed.
摘要翻译：非易失性存储器件可以包括半导体衬底，其包括其表面处的有源区，有源区上的第一存储单元串和有源区上的第二存储单元串。第一存储单元串可以包括与第一地选择线和第一串选择线之间的有源区域交叉的第一多个字线，并且可以在第一多个字线中相邻的字线之间提供约相同的第一间隔。第二存储单元串可以包括与第二接地选择线和第二串选择线之间的有源区域交叉的第二多个字线，并且可以在相邻的第二多个字线之间提供约相同的第一间隔。还讨论了相关方法。

4. 发明申请

US20080013377A1 Non-volatile memory devices including dummy word lines and related structures and methods 有权
标题翻译：包括虚拟字线和相关结构和方法的非易失性存储器件
公开(公告)号：US20080013377A1
公开(公告)日：2008-01-17
申请号：US11729169
申请日：2007-03-28
申请人： Jong-Sun Sel , Jung-Dal Choi , Young-Woo Park , Jin-Taek Park
发明人： Jong-Sun Sel , Jung-Dal Choi , Young-Woo Park , Jin-Taek Park
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C16/3427
摘要： A non-volatile memory device may include a semiconductor substrate including an active region at a surface thereof, a first memory cell string on the active region, and a second memory cell string on the active region. The first memory cell string may include a first plurality of word lines crossing the active region between a first ground select line and a first string select line, and about a same first spacing may be provided between adjacent ones of the first plurality of word lines. The second memory cell string may include a second plurality of word lines crossing the active region between a second ground select line and a second string select line, and about the same first spacing may be provided between adjacent ones of the second plurality of word lines. Moreover, the first ground select line may be between the second ground select line and the first plurality of word lines, and the second ground select line may be between the first ground select line and the second plurality of word lines. Moreover, portions of the active region between the first and second ground select lines may be free of word lines, and a second spacing between the first and second ground select lines may be at least about 3 times greater than the first spacing. Related methods are also discussed.
摘要翻译：非易失性存储器件可以包括半导体衬底，其包括其表面处的有源区，有源区上的第一存储单元串和有源区上的第二存储单元串。第一存储单元串可以包括与第一地选择线和第一串选择线之间的有源区域交叉的第一多个字线，并且可以在第一多个字线中相邻的字线之间提供约相同的第一间隔。第二存储单元串可以包括与第二接地选择线和第二串选择线之间的有源区域交叉的第二多个字线，并且可以在相邻的第二多个字线之间提供约相同的第一间隔。此外，第一接地选择线可以在第二接地选择线和第一多个字线之间，并且第二接地选择线可以在第一接地选择线和第二多个字线之间。此外，第一和第二接地选择线之间的有源区域的部分可以没有字线，并且第一和第二接地选择线之间的第二间隔可以比第一间隔大至少约3倍。还讨论了相关方法。

5. 发明申请

US20120218816A1 Non-Volatile Memory Devices 有权
标题翻译：非易失性存储器件
公开(公告)号：US20120218816A1
公开(公告)日：2012-08-30
申请号：US13463060
申请日：2012-05-03
申请人： Jong-Sun Sel , Jung-Dal Choi , Young-Woo Park , Jin-Taek Park
发明人： Jong-Sun Sel , Jung-Dal Choi , Young-Woo Park , Jin-Taek Park
IPC分类号： G11C11/34
CPC分类号： G11C16/0483 , G11C16/3427
摘要： A non-volatile memory device may include a semiconductor substrate including an active region at a surface thereof, a ground select line crossing the active region, and a string select line crossing the active region and spaced apart from the ground select line. A plurality of memory cell word lines may cross the active region between the ground select line and the string select line with about a same first spacing provided between adjacent ones of the plurality of word lines and between a last of the plurality of memory cell word lines and the string select line. A second spacing may be provided between the ground select line and a first of the plurality of memory cell word lines.
摘要翻译：非易失性存储器件可以包括半导体衬底，其包括其表面处的有源区，与有源区交叉的接地选择线，以及与有源区交叉并与地选线相隔的串选择线。多个存储单元字线可以与地线选择线和弦选择线之间的有源区域相交，并且与多个字线中的相邻字线之间以及多个存储单元字线中的最后一个之间提供大致相同的第一间隔和字符串选择行。可以在接地选择线和多个存储单元字线中的第一个之间提供第二间隔。

6. 发明授权

US08675409B2 Non-volatile memory devices 有权
标题翻译：非易失性存储器件
公开(公告)号：US08675409B2
公开(公告)日：2014-03-18
申请号：US13463060
申请日：2012-05-03
申请人： Jong-Sun Sel , Jung-Dal Choi , Young-Woo Park , Jin-Taek Park
发明人： Jong-Sun Sel , Jung-Dal Choi , Young-Woo Park , Jin-Taek Park
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/0483 , G11C16/3427
摘要： A non-volatile memory device may include a semiconductor substrate including an active region at a surface thereof, a ground select line crossing the active region, and a string select line crossing the active region and spaced apart from the ground select line. A plurality of memory cell word lines may cross the active region between the ground select line and the string select line with about a same first spacing provided between adjacent ones of the plurality of word lines and between a last of the plurality of memory cell word lines and the string select line. A second spacing may be provided between the ground select line and a first of the plurality of memory cell word lines.
摘要翻译：非易失性存储器件可以包括半导体衬底，其包括其表面处的有源区，与有源区交叉的接地选择线，以及与有源区交叉并与地选线相隔的串选择线。多个存储单元字线可以与地线选择线和弦选择线之间的有源区域相交，并且与多个字线中的相邻字线之间以及多个存储单元字线中的最后一个之间提供大致相同的第一间隔和字符串选择行。可以在接地选择线和多个存储单元字线中的第一个之间提供第二间隔。

7. 发明授权

US08048746B2 Method of making flash memory cells and peripheral circuits having STI, and flash memory devices and computer systems having the same 失效
公开(公告)号：US08048746B2
公开(公告)日：2011-11-01
申请号：US12979890
申请日：2010-12-28
申请人： Jin-Taek Park , Young-Woo Park , Jang-Hyun You , Jung-Dal Choi
发明人： Jin-Taek Park , Young-Woo Park , Jang-Hyun You , Jung-Dal Choi
IPC分类号： H01L21/336
CPC分类号： H01L27/11573 , H01L27/11526 , H01L27/11546 , H01L27/11592 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit includes flash memory cells, and peripheral circuitry including low voltage transistors (LVT) and high voltage transistors (HVT). The integrated circuit includes a tunnel barrier layer comprising SiON, SiN or other high-k material. The tunnel barrier layer may comprise a part of the gate dielectric of the HVTs. The tunnel barrier layer may constitute the entire gate dielectric of the HVTs. The corresponding tunnel barrier layer may be formed between or upon shallow trench isolation (STIs). Therefore, the manufacturing efficiency of a driver chip IC may be increased.

8. 发明申请

US20090315099A1 METHOD OF MAKING FLASH MEMORY CELLS AND PERIPHERAL CIRCUITS HAVING STI, AND FLASH MEMORY DEVICES AND COMPUTER SYSTEMS HAVING THE SAME 有权
标题翻译：制造闪速存储器细胞的方法和具有STI的外围电路以及具有该闪存存储器的闪速存储器件和计算机系统
公开(公告)号：US20090315099A1
公开(公告)日：2009-12-24
申请号：US12367988
申请日：2009-02-09
申请人： Jin-Taek Park , Young-Woo Park , Jang-Hyun You , Jung-Dal Choi
发明人： Jin-Taek Park , Young-Woo Park , Jang-Hyun You , Jung-Dal Choi
IPC分类号： H01L25/07 , H01L21/76
CPC分类号： H01L27/11573 , H01L27/11526 , H01L27/11546 , H01L27/11592 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit includes flash memory cells, and peripheral circuitry including low voltage transistors (LVT) and high voltage transistors (HVT). The integrated circuit includes a tunnel barrier layer comprising SiON, SiN or other high-k material. The tunnel barrier layer may comprise a part of the gate dielectric of the HVTs. The tunnel barrier layer may constitute the entire gate dielectric of the HVTs. The corresponding tunnel barrier layer may be formed between or upon shallow trench isolation (STIs). Therefore, the manufacturing efficiency of a driver chip IC may be increased.
摘要翻译：集成电路包括闪存单元，以及包括低压晶体管（LVT）和高压晶体管（HVT））的外围电路。集成电路包括包含SiON，SiN或其它高k材料的隧道势垒层。隧道势垒层可以包括HVT的栅极电介质的一部分。隧道势垒层可以构成HVT的整个栅电介质。相应的隧道势垒层可以形成在浅沟槽隔离（STI）之间或之间。因此，可以提高驱动器芯片IC的制造效率。

9. 发明申请

US20090212340A1 FLASH MEMORY DEVICES 审中-公开
标题翻译：闪存存储器件
公开(公告)号：US20090212340A1
公开(公告)日：2009-08-27
申请号：US12392656
申请日：2009-02-25
申请人： Chang-Hyun Lee , Young-Woo Park , Jung-Dal Choi , Chang-Seok Kang , Jin-Taek Park
发明人： Chang-Hyun Lee , Young-Woo Park , Jung-Dal Choi , Chang-Seok Kang , Jin-Taek Park
IPC分类号： H01L29/788
CPC分类号： H01L27/11568 , H01L27/11521
摘要： A gate electrode line which extends in a second direction crossing a first direction on a substrate including an active region which is defined by a device isolation layer and extends in the first direction and a charge trap layer disposed between the active region and the gate electrode line, wherein a bottom surface of the gate electrode line disposed on the device isolation layer is lower than a top surface of the charge trap layer disposed on the active region and higher than a top surface of the active region.
摘要翻译：一种栅极电极线，其在包括由器件隔离层限定并在第一方向上延伸的有源区域和设置在有源区域和栅电极线之间的电荷陷阱层的基板上沿与第一方向交叉的第二方向延伸其特征在于，设置在所述器件隔离层上的所述栅电极线的底面低于设置在所述有源区上并高于所述有源区的顶面的所述电荷陷阱层的顶面。

10. 发明授权

US07799645B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07799645B2
公开(公告)日：2010-09-21
申请号：US12232148
申请日：2008-09-11
申请人： Jung-Dal Choi , Young-Woo Park , Jin-Taek Park , Chung-Il Hyun
发明人： Jung-Dal Choi , Young-Woo Park , Jin-Taek Park , Chung-Il Hyun
IPC分类号： H01L21/8236
CPC分类号： H01L21/8236 , H01L27/105 , H01L27/11568 , H01L27/11573
摘要： An embodiment of a semiconductor device includes a substrate including a cell region and a peripheral region; a cell gate pattern on the cell region; and a peripheral gate pattern on the peripheral region, wherein a first cell insulation layer, a second cell insulation layer, and a third cell insulation layer may be between the substrate and the cell gate pattern, a first peripheral insulation layer, a second peripheral insulation layer, and a third peripheral insulation layer may be between the substrate and the peripheral gate pattern, and the second cell insulation layer and the third cell insulation layer include the same material as the respective second peripheral insulation layer and third peripheral insulation layer.
摘要翻译：半导体器件的实施例包括：包括单元区域和周边区域的衬底; 单元格区域上的单元格栅图案; 以及周边区域上的外围栅极图案，其中第一电池绝缘层，第二电池绝缘层和第三电池绝缘层可以在衬底和电池栅极图案之间，第一外围绝缘层，第二外围绝缘层层和第三外围绝缘层可以在基板和外围栅极图案之间，并且第二电池绝缘层和第三电池绝缘层包括与相应的第二外围绝缘层和第三外围绝缘层相同的材料。

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