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1. 发明授权

US09570467B2 High voltage three-dimensional devices having dielectric liners 有权
标题翻译：具有电介质衬垫的高压三维器件
公开(公告)号：US09570467B2
公开(公告)日：2017-02-14
申请号：US14641117
申请日：2015-03-06
申请人： Walid M. Hafez , Jeng-Ya D. Yeh , Curtis Tsai , Joodong Park , Chia-Hong Jan , Gopinath Bhimarasetti
发明人： Walid M. Hafez , Jeng-Ya D. Yeh , Curtis Tsai , Joodong Park , Chia-Hong Jan , Gopinath Bhimarasetti
IPC分类号： H01L21/84 , H01L27/12 , H01L29/66 , H01L21/8234 , H01L21/02 , H01L21/28 , H01L29/423 , H01L29/51
CPC分类号： H01L27/1211 , H01L21/02164 , H01L21/0228 , H01L21/02532 , H01L21/02598 , H01L21/28158 , H01L21/823412 , H01L21/823418 , H01L21/823431 , H01L21/823437 , H01L21/823462 , H01L21/823468 , H01L21/845 , H01L29/42356 , H01L29/51 , H01L29/513 , H01L29/66545 , H01L29/6656 , H01L29/6681
摘要： High voltage three-dimensional devices having dielectric liners and methods of forming high voltage three-dimensional devices having dielectric liners are described. For example, a semiconductor structure includes a first fin active region and a second fin active region disposed above a substrate. A first gate structure is disposed above a top surface of, and along sidewalls of, the first fin active region. The first gate structure includes a first gate dielectric, a first gate electrode, and first spacers. The first gate dielectric is composed of a first dielectric layer disposed on the first fin active region and along sidewalls of the first spacers, and a second, different, dielectric layer disposed on the first dielectric layer and along sidewalls of the first spacers. The semiconductor structure also includes a second gate structure disposed above a top surface of, and along sidewalls of, the second fin active region. The second gate structure includes a second gate dielectric, a second gate electrode, and second spacers. The second gate dielectric is composed of the second dielectric layer disposed on the second fin active region and along sidewalls of the second spacers.
摘要翻译：描述了具有电介质衬垫的高压三维器件和形成具有电介质衬垫的高电压三维器件的方法。例如，半导体结构包括设置在基板上方的第一鳍状物活性区域和第二鳍状物活性区域。第一栅极结构设置在第一鳍片活动区域的顶表面之上并且沿着第一鳍片活动区域的侧壁的上方。第一栅极结构包括第一栅极电介质，第一栅极电极和第一间隔物。第一栅极电介质由设置在第一鳍状物活性区域上并沿着第一间隔物的侧壁的第一介电层和设置在第一介电层上并沿着第一间隔物的侧壁的第二不同介电层组成。半导体结构还包括第二栅极结构，其设置在第二鳍片活动区域的顶表面之上并且沿着第二鳍片活动区域的侧壁的上方。第二栅极结构包括第二栅极电介质，第二栅电极和第二间隔物。第二栅极电介质由设置在第二鳍状物活性区域和第二间隔物的侧壁上的第二介电层构成。

2. 发明申请

US20140308785A1 PRECISION RESISTOR FOR NON-PLANAR SEMICONDUCTOR DEVICE ARCHITECTURE 有权
公开(公告)号：US20140308785A1
公开(公告)日：2014-10-16
申请号：US14313678
申请日：2014-06-24
申请人： Jeng-Ya D. Yeh , Peter J. Vandervoorn , Walid M. Hafez , Chia-Hong Jan , Curtis Tsai , Joodong Park
发明人： Jeng-Ya D. Yeh , Peter J. Vandervoorn , Walid M. Hafez , Chia-Hong Jan , Curtis Tsai , Joodong Park
IPC分类号： H01L21/8234 , H01L29/66 , H01L49/02
CPC分类号： H01L21/823431 , H01L27/0629 , H01L27/0886 , H01L28/20 , H01L29/66545 , H01L29/66795
摘要： Precision resistors for non-planar semiconductor device architectures are described. In a first example, a semiconductor structure includes first and second semiconductor fins disposed above a substrate. A resistor structure is disposed above the first semiconductor fin but not above the second semiconductor fin. A transistor structure is formed from the second semiconductor fin but not from the first semiconductor fin. In a second example, a semiconductor structure includes first and second semiconductor fins disposed above a substrate. An isolation region is disposed above the substrate, between the first and second semiconductor fins, and at a height less than the first and second semiconductor fins. A resistor structure is disposed above the isolation region but not above the first and second semiconductor fins. First and second transistor structures are formed from the first and second semiconductor fins, respectively.

3. 发明申请

US20140319623A1 METHODS OF INTEGRATING MULTIPLE GATE DIELECTRIC TRANSISTORS ON A TRI-GATE (FINFET) PROCESS 审中-公开
标题翻译：在三极（FINFET）工艺上集成多个栅极介质晶体管的方法
公开(公告)号：US20140319623A1
公开(公告)日：2014-10-30
申请号：US13997624
申请日：2011-12-28
申请人： Curtis Tsai , Chia-Hong Jan , Jeng-Ya David Yeh , Joodong Park , Walid M. Hafez
发明人： Curtis Tsai , Chia-Hong Jan , Jeng-Ya David Yeh , Joodong Park , Walid M. Hafez
IPC分类号： H01L21/8234 , H01L29/423 , H01L27/088
摘要： Two or more types of fin-based transistors having different gate structures and formed on a single integrated circuit are described. The gate structures for each type of transistor are distinguished at least by the thickness or composition of the gate dielectric layer(s) or the composition of the work function metal layer(s) in the gate electrode. Methods are also provided for fabricating an integrated circuit having at least two different types of fin-based transistors, where the transistor types are distinguished by the thickness and composition of the gate dielectric layer(s) and/or the thickness and composition of the work function metal in the gate electrode.
摘要翻译：描述了具有不同栅极结构并形成在单个集成电路上的两种或多种类型的鳍式晶体管。每种类型的晶体管的栅极结构至少区别于栅极电介质层的厚度或组成或栅电极中功函数金属层的组成。还提供了用于制造具有至少两种不同类型的基于鳍的晶体管的集成电路的方法，其中晶体管类型通过栅极电介质层的厚度和组成和/或工件的厚度和组成来区分功能金属在栅电极。

4. 发明授权

US08796772B2 Precision resistor for non-planar semiconductor device architecture 有权
公开(公告)号：US08796772B2
公开(公告)日：2014-08-05
申请号：US13625698
申请日：2012-09-24
申请人： Jeng-Ya D. Yeh , Peter J. Vandervoorn , Walid M. Hafez , Chia-Hong Jan , Curtis Tsai , Joodong Park
发明人： Jeng-Ya D. Yeh , Peter J. Vandervoorn , Walid M. Hafez , Chia-Hong Jan , Curtis Tsai , Joodong Park
IPC分类号： H01L21/70
CPC分类号： H01L21/823431 , H01L27/0629 , H01L27/0886 , H01L28/20 , H01L29/66545 , H01L29/66795
摘要： Precision resistors for non-planar semiconductor device architectures are described. In a first example, a semiconductor structure includes first and second semiconductor fins disposed above a substrate. A resistor structure is disposed above the first semiconductor fin but not above the second semiconductor fin. A transistor structure is formed from the second semiconductor fin but not from the first semiconductor fin. In a second example, a semiconductor structure includes first and second semiconductor fins disposed above a substrate. An isolation region is disposed above the substrate, between the first and second semiconductor fins, and at a height less than the first and second semiconductor fins. A resistor structure is disposed above the isolation region but not above the first and second semiconductor fins. First and second transistor structures are formed from the first and second semiconductor fins, respectively.

5. 发明申请

US20130270559A1 ANTIFUSE ELEMENT UTILIZING NON-PLANAR TOPOLOGY 有权
标题翻译：使用非平面拓扑学的抗体元件
公开(公告)号：US20130270559A1
公开(公告)日：2013-10-17
申请号：US13976087
申请日：2011-10-18
申请人： Walid M. Hafez , Chia-Hong Jan , Curtis Tsai , Joodong Park , Jeng-Ya D. Yeh
发明人： Walid M. Hafez , Chia-Hong Jan , Curtis Tsai , Joodong Park , Jeng-Ya D. Yeh
IPC分类号： H01L27/112
CPC分类号： H01L27/11206 , H01L21/823821 , H01L23/5252 , H01L27/0924 , H01L29/7853 , H01L2924/0002 , H01L2924/00
摘要： Techniques for providing non-volatile antifuse memory elements and other antifuse links are disclosed herein. In sonic embodiments, the antifuse memory elements are configured with non-planar topology such as FinFET topology. In some such embodiments, the fin topology can be manipulated and used to effectively promote lower breakdown voltage transistors, by creating enhanced-emission sites which are suitable for use in lower voltage non-volatile antifuse memory elements. In one example embodiment, a semiconductor antifuse device is provided that includes a non-planar diffusion area having a fin configured with a tapered portion, a dielectric isolation layer on the fin including the tapered portion, and a gate material on the dielectric isolation layer. The tapered portion of the fin may be formed, for instance, by oxidation, etching, and/or ablation, and in some cases includes a base region and a thinned region, and the thinned region is at least 50% thinner than the base region.
摘要翻译：本文公开了用于提供非易失性反熔丝存储元件和其它反熔丝链路的技术。在声音实施例中，反熔丝存储器元件被配置为具有诸如FinFET拓扑的非平面拓扑。在一些这样的实施例中，可以通过产生适合用于较低电压非易失性反熔丝存储器元件的增强发射位点来操纵翅片拓扑并用于有效地促进较低击穿电压晶体管。在一个示例实施例中，提供了一种半导体反熔丝装置，其包括具有锥形部分的翅片的非平面扩散区域，在包括锥形部分的鳍片上的介电隔离层和介电隔离层上的栅极材料。翅片的锥形部分可以例如通过氧化，蚀刻和/或烧蚀形成，并且在一些情况下包括基底区域和变薄区域，并且变薄区域比基底区域薄至少50％。

6. 发明授权

US08889508B2 Precision resistor for non-planar semiconductor device architecture 有权
标题翻译：用于非平面半导体器件结构的精密电阻器
公开(公告)号：US08889508B2
公开(公告)日：2014-11-18
申请号：US14313678
申请日：2014-06-24
申请人： Jeng-Ya D. Yeh , Peter J. Vandervoorn , Walid M. Hafez , Chia-Hong Jan , Curtis Tsai , Joodong Park
发明人： Jeng-Ya D. Yeh , Peter J. Vandervoorn , Walid M. Hafez , Chia-Hong Jan , Curtis Tsai , Joodong Park
IPC分类号： H01L21/8234 , H01L29/66 , H01L49/02
CPC分类号： H01L21/823431 , H01L27/0629 , H01L27/0886 , H01L28/20 , H01L29/66545 , H01L29/66795
摘要： Precision resistors for non-planar semiconductor device architectures are described. In a first example, a semiconductor structure includes first and second semiconductor fins disposed above a substrate. A resistor structure is disposed above the first semiconductor fin but not above the second semiconductor fin. A transistor structure is formed from the second semiconductor fin but not from the first semiconductor fin. In a second example, a semiconductor structure includes first and second semiconductor fins disposed above a substrate. An isolation region is disposed above the substrate, between the first and second semiconductor fins, and at a height less than the first and second semiconductor fins. A resistor structure is disposed above the isolation region but not above the first and second semiconductor fins. First and second transistor structures are formed from the first and second semiconductor fins, respectively.
摘要翻译：描述了用于非平面半导体器件结构的精密电阻器。在第一示例中，半导体结构包括设置在基板上方的第一和第二半导体翅片。电阻器结构设置在第一半导体鳍片上方，但不在第二半导体鳍片之上。晶体管结构由第二半导体鳍形成，但不由第一半导体鳍形成。在第二示例中，半导体结构包括设置在基板上方的第一和第二半导体翅片。隔离区设置在基板之上，位于第一和第二半导体鳍之间，并且在小于第一和第二半导体鳍片的高度处。电阻结构设置在隔离区域上方，但不在第一和第二半导体鳍片之上。第一和第二晶体管结构分别由第一和第二半导体鳍形成。

7. 发明授权

US08669617B2 Multi-gate transistors 有权
标题翻译：多栅极晶体管
公开(公告)号：US08669617B2
公开(公告)日：2014-03-11
申请号：US12978182
申请日：2010-12-23
申请人： Chia-Hong Jan , Curtis Tsai , Joodong Park , Jeng-Ya D. Yeh , Walid M. Hafez
发明人： Chia-Hong Jan , Curtis Tsai , Joodong Park , Jeng-Ya D. Yeh , Walid M. Hafez
IPC分类号： H01L27/088
CPC分类号： H01L21/823857 , H01L21/26506 , H01L21/28158 , H01L21/2822 , H01L21/823462 , H01L29/495 , H01L29/513 , H01L29/517 , H01L29/66545 , H01L29/78
摘要： Provided are devices having at least three and at least four different types of transistors wherein the transistors are distinguished at least by the thicknesses and or compositions of the gate dielectric regions. Methods for making devices having three and at least four different types of transistors that are distinguished at least by the thicknesses and or compositions of the gate dielectric regions are also provided.
摘要翻译：提供了具有至少三种和至少四种不同类型的晶体管的器件，其中晶体管至少区别于栅极电介质区域的厚度和/或组成。还提供了制造具有三个至少四种不同类型晶体管的器件的方法，其至少区别于栅极电介质区域的厚度和/或组成。

8. 发明申请

US20140001569A1 HIGH VOLTAGE THREE-DIMENSIONAL DEVICES HAVING DIELECTRIC LINERS 有权
标题翻译：具有电介质衬底的高电压三维器件
公开(公告)号：US20140001569A1
公开(公告)日：2014-01-02
申请号：US13536732
申请日：2012-06-28
申请人： Walid M. Hafez , Jeng-Ya D. Yeh , Curtis Tsai , Joodong Park , Chia-Hong Jan , Gopinath Bhimarasetti
发明人： Walid M. Hafez , Jeng-Ya D. Yeh , Curtis Tsai , Joodong Park , Chia-Hong Jan , Gopinath Bhimarasetti
IPC分类号： H01L27/088 , H01L21/28
CPC分类号： H01L27/1211 , H01L21/02164 , H01L21/0228 , H01L21/02532 , H01L21/02598 , H01L21/28158 , H01L21/823412 , H01L21/823418 , H01L21/823431 , H01L21/823437 , H01L21/823462 , H01L21/823468 , H01L21/845 , H01L29/42356 , H01L29/51 , H01L29/513 , H01L29/66545 , H01L29/6656 , H01L29/6681
摘要： High voltage three-dimensional devices having dielectric liners and methods of forming high voltage three-dimensional devices having dielectric liners are described. For example, a semiconductor structure includes a first fin active region and a second fin active region disposed above a substrate. A first gate structure is disposed above a top surface of, and along sidewalls of, the first fin active region. The first gate structure includes a first gate dielectric composed of a first dielectric layer disposed on the first fin active region, and a second, different, dielectric layer disposed on the first dielectric layer. The semiconductor structure also includes a second gate structure disposed above a top surface of, and along sidewalls of, the second fin active region. The second gate structure includes a second gate dielectric composed of the second dielectric layer disposed on the second fin active region.
摘要翻译：描述了具有电介质衬垫的高压三维器件和形成具有电介质衬垫的高电压三维器件的方法。例如，半导体结构包括设置在基板上方的第一鳍状物活性区域和第二鳍状物活性区域。第一栅极结构设置在第一鳍片活动区域的顶表面之上并且沿着第一鳍片活动区域的侧壁的上方。第一栅极结构包括由设置在第一鳍片有源区上的第一介电层和设置在第一介电层上的第二不同介电层构成的第一栅极电介质。半导体结构还包括第二栅极结构，其设置在第二鳍片活动区域的顶表面之上并且沿着第二鳍片活动区域的侧壁的上方。第二栅极结构包括由设置在第二鳍片有源区上的第二介电层构成的第二栅极电介质。

9. 发明授权

US07691718B2 Dual layer hard mask for block salicide poly resistor (BSR) patterning 失效
标题翻译：双层硬掩模用于块状硅化物电阻（BSR）图案化
公开(公告)号：US07691718B2
公开(公告)日：2010-04-06
申请号：US12005944
申请日：2007-12-27
申请人： Joodong Park , Chia-Hong Jan , Paul Reese
发明人： Joodong Park , Chia-Hong Jan , Paul Reese
IPC分类号： H01L21/20
CPC分类号： H01L29/8605 , H01L28/24
摘要： In general, in one aspect, a method includes forming a semiconductor substrate having an N+ diffusion region, a shallow trench isolation (STI) region adjacent to the N+ diffusion region, and a blocked salicide poly resistor (BSR) region over the STI region. An oxide layer is over the substrate. A nitride layer is formed over the oxide layer and is annealed. A resist layer is patterned on the annealed nitride layer, wherein the resist layer covers a portion of the BSR region. The annealed nitride layer is etched using the resist layer as a pattern. The resist layer is removed and the oxide layer is etched using the annealed nitride layer as a pattern. Germanium pre-amorphization is implanted into the substrate, wherein the oxide and the annealed nitride layers protect a portion of the BSR region from the implanting.
摘要翻译：通常，在一个方面，一种方法包括形成具有N +扩散区域，与N +扩散区域相邻的浅沟槽隔离（STI）区域和在STI区域上的封闭的自对准硅化物多晶硅电阻器（BSR）区域的半导体衬底。氧化物层在衬底上。在氧化物层上形成氮化物层并进行退火。在退火的氮化物层上图案化抗蚀剂层，其中抗蚀剂层覆盖BSR区域的一部分。使用抗蚀剂层作为图案蚀刻退火的氮化物层。去除抗蚀剂层，并使用退火的氮化物层作为图案来蚀刻氧化物层。将锗预非晶化植入衬底中，其中氧化物和退火的氮化物层保护BSR区域的一部分免受植入。

10. 发明申请

US20160056162A1 CMOS-COMPATIBLE POLYCIDE FUSE STRUCTURE AND METHOD OF FABRICATING SAME 有权
标题翻译： CMOS兼容聚合物熔丝结构及其制造方法
公开(公告)号：US20160056162A1
公开(公告)日：2016-02-25
申请号：US14780222
申请日：2013-06-25
申请人： JENG-YA D. YEH , CHIA-HONG JAN , WALID M. HAFEZ , JOODONG PARK
发明人： JENG-YA D. YEH , CHIA-HONG JAN , WALID M. HAFEZ , JOODONG PARK
IPC分类号： H01L27/112 , H01L27/088 , H01L29/78 , H01L23/525
CPC分类号： H01L27/11206 , H01L21/823431 , H01L23/5256 , H01L27/0886 , H01L27/0924 , H01L29/66545 , H01L29/66795 , H01L29/78 , H01L29/785 , H01L2924/0002 , H01L2924/00
摘要： CMOS-compatible polycide fuse structures and methods of fabricating CMOS-compatible polycide fuse structures are described. In an example, a semiconductor structure includes a substrate. A polycide fuse structure is disposed above the substrate and includes silicon and a metal. A metal oxide semiconductor (MOS) transistor structure is disposed above the substrate and includes a metal gate electrode.
摘要翻译：描述了CMOS兼容多晶硅熔丝结构和制造CMOS兼容多晶硅熔丝结构的方法。在一个示例中，半导体结构包括衬底。多晶硅熔丝结构设置在基板上方并且包括硅和金属。金属氧化物半导体（MOS）晶体管结构设置在基板上方并且包括金属栅电极。

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