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1. 发明授权

US08049548B2 Digital synchronous circuit 有权
标题翻译：数字同步电路
公开(公告)号：US08049548B2
公开(公告)日：2011-11-01
申请号：US12643654
申请日：2009-12-21
申请人： Joong-Sug Gil
发明人： Joong-Sug Gil
IPC分类号： G06F1/04
CPC分类号： G06F1/06
摘要： A digital synchronous circuit includes a clock generator for generating a reference clock signal, a plurality of delays for delaying the reference clock signal by predetermined different times, a transition varying buffer for controlling input transitions of the clock signals received from the plurality of the delays, a transition controller for controlling operation of the transition varying buffer, and a plurality of registers driven by the clock signals from the plurality of delays.
摘要翻译：数字同步电路包括用于产生参考时钟信号的时钟发生器，用于将参考时钟信号延迟预定不同时间的多个延迟，用于控制从多个延迟接收的时钟信号的输入转变的转变变化缓冲器，用于控制转变变化缓冲器的操作的转换控制器和由多个延迟的时钟信号驱动的多个寄存器。

2. 发明申请

US20100164587A1 DIGITAL SYNCHRONOUS CIRCUIT 有权
标题翻译：数字同步电路
公开(公告)号：US20100164587A1
公开(公告)日：2010-07-01
申请号：US12643654
申请日：2009-12-21
申请人： Joong-Sug Gil
发明人： Joong-Sug Gil
IPC分类号： G06F1/04
CPC分类号： G06F1/06
摘要： A digital synchronous circuit includes a clock generator for generating a reference clock signal, a plurality of delays for delaying the reference clock signal by predetermined different times, a transition varying buffer for controlling input transitions of the clock signals received from the plurality of the delays, a transition controller for controlling operation of the transition varying buffer, and a plurality of registers driven by the clock signals from the plurality of delays.
摘要翻译：数字同步电路包括用于产生参考时钟信号的时钟发生器，用于将参考时钟信号延迟预定不同时间的多个延迟，用于控制从多个延迟接收的时钟信号的输入转变的转变变化缓冲器，用于控制转变变化缓冲器的操作的转换控制器和由多个延迟的时钟信号驱动的多个寄存器。

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