专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20190042329A1 SYSTEM WITH PROGRAMMABLE MULTI-CONTEXT ACCELERATOR CIRCUITRY 审中-公开
公开(公告)号：US20190042329A1
公开(公告)日：2019-02-07
申请号：US16024563
申请日：2018-06-29
申请人： Utkarsh Y. Kakaiya , Pratik Marolia , Joshua David Fender , Sundar Nadathur , Nagabhushan Chitlur , Yuling Yang , David Alexander Munday
发明人： Utkarsh Y. Kakaiya , Pratik Marolia , Joshua David Fender , Sundar Nadathur , Nagabhushan Chitlur , Yuling Yang , David Alexander Munday
IPC分类号： G06F9/50 , G06F13/42
摘要： A system is provided that includes a host processor coupled to a programmable acceleration coprocessor. The coprocessor may include logic for implementing a physical function and multiple associated virtual functions. The coprocessor may include a static programmable resource interface circuit (PIC) configured to perform management functions and one or more partial reconfiguration regions, each of which can be loaded with an accelerator function unit (AFU). An AFU may further be partitioned into AFU contexts (AFCs), each of which can be mapped to one of the virtual functions. The PIC enables hardware discovery/enumeration and loading of device drivers such that security isolation and interface performance are maintained.

2. 发明授权

US08190418B1 Producing integrated circuits with time-dependent-impedance elements 有权
标题翻译：生产具有时间依赖阻抗元件的集成电路
公开(公告)号：US08190418B1
公开(公告)日：2012-05-29
申请号：US12407770
申请日：2009-03-19
申请人： Joshua David Fender
发明人： Joshua David Fender
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F17/5054 , G06F17/5068 , G06F2217/84
摘要： Methods, systems and computer programs for producing integrated circuits (IC) that contain an electronic component with time-dependent impedance are provided. According to one method, time-dependent impedance values for the electronic component are obtained. These time-dependent impedance values are time-dependent because they can change over time, such as when an input/output buffer starts switching, and are used to create a model of the electronic component. The model includes a variable impedance and a variable voltage source. The model is created by calculating a current through the variable impedance and then assigning the obtained impedance values to the impedance. Additionally, values are assigned to the variable voltage source such that the current through the variable impedance with the new assigned values is equal to the current thorough the variable impedance before the assignment of the time-dependent impedance values. Results from multiple simulations of the IC are compared to select the IC layout that generates the lowest noise profile and the IC is produced with the selected layout.
摘要翻译：提供了用于制造包含具有时间依赖阻抗的电子部件的集成电路（IC）的方法，系统和计算机程序。根据一种方法，获得电子部件的时间依赖阻抗值。这些时间依赖阻抗值是时间依赖性的，因为它们可以随时间而改变，例如当输入/输出缓冲器开始切换时，并且用于创建电子部件的模型。该模型包括可变阻抗和可变电压源。该模型是通过计算通过可变阻抗的电流，然后将获得的阻抗值分配给阻抗来创建的。此外，将值分配给可变电压源，使得通过具有新分配值的可变阻抗的电流在分配时间相关阻抗值之前等于电流通过可变阻抗。将来自IC的多次模拟的结果进行比较，以选择产生最低噪声分布的IC布局，并且使用所选择的布局生成IC。

3. 发明申请

US20110299346A1 APPARATUS FOR SOURCE-SYNCHRONOUS INFORMATION TRANSFER AND ASSOCIATED METHODS 审中-公开
标题翻译：用于源同步信息传输和相关方法的装置
公开(公告)号：US20110299346A1
公开(公告)日：2011-12-08
申请号：US12793583
申请日：2010-06-03
申请人： Ryan Fung , Joshua David Fender
发明人： Ryan Fung , Joshua David Fender
IPC分类号： G11C7/00 , H03K19/00
CPC分类号： G11C7/222 , G11C7/1036 , G11C7/1078 , G11C7/1093
摘要： An apparatus includes an interface circuit coupled to an electronic device. The interface circuit provides source synchronous communication with the electronic device using a strobe signal. The interface circuit is configured to gate the strobe signal in order to successfully communicate with the electronic device.
摘要翻译：一种装置包括耦合到电子装置的接口电路。接口电路使用选通信号提供与电子设备的源同步通信。接口电路被配置为对选通信号进行门控，以便与电子设备成功通信。

4. 发明授权

US07983880B1 Simultaneous switching noise analysis using superposition techniques 有权
标题翻译：使用叠加技术进行同步开关噪声分析
公开(公告)号：US07983880B1
公开(公告)日：2011-07-19
申请号：US12034400
申请日：2008-02-20
申请人： Joshua David Fender , Paul Leventis
发明人： Joshua David Fender , Paul Leventis
IPC分类号： G06G7/00
CPC分类号： G06F17/5036 , G06F17/504 , G06F2217/82
摘要： Extended linear superposition methods, computer program products and systems to calculate Simultaneous Switching Noise (SSN) on victim Input/Output (I/O) pins of an electronic component caused by aggressor I/O pins is provided. A method includes calculating the quiet output voltage on a victim pin caused by the power supply only, and then calculating an aggressor noise response induced on the victim pin caused by a single aggressor pin and the power supply. To calculate SSN for a combination of aggressors, the SSNs for the different aggressors are linearly combined, and then the effects of the power supply are discounted by using the calculated quiet output voltage. Additionally, a linear victim substitution model is introduced to replace a full buffer model for a victim pin with a resistor with different resistance values depending on the induced voltage. Further, an alternate transmission line model is introduced to simplify SSN simulations of transmission lines.
摘要翻译：提供扩展线性叠加方法，计算机程序产品和系统，用于计算由侵入者I / O引脚引起的电子元件的受害者输入/输出（I / O）引脚上的同时开关噪声（SSN）。一种方法包括计算仅由电源引起的受害者引脚上的安静输出电压，然后计算由单个攻击者引脚和电源引起的受害者引脚上的侵扰者噪声响应。为了计算攻击者组合的SSN，不同攻击者的SSN线性组合，然后使用计算出的静音输出电压对电源的影响进行折扣。另外，引入线性受害者替代模型，以根据感应电压用具有不同电阻值的电阻替代受害针的完整缓冲器模型。此外，引入替代传输线模型以简化传输线的SSN仿真。

5. 发明授权

US08181130B1 Method for jitter reduction by shifting current consumption 有权
标题翻译：通过移动电流消耗来减少抖动的方法
公开(公告)号：US08181130B1
公开(公告)日：2012-05-15
申请号：US12564654
申请日：2009-09-22
申请人： Joshua David Fender
发明人： Joshua David Fender
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F2217/78 , G06F2217/84
摘要： A method for jitter reduction in a path of an integrated circuit design is presented. The path is first analyzed to identify a combinatorial logic element bounded between a source element and a destination element. The arrival time of the input signal to the combinatorial logic element is shifted by inserting a logic element at the input of the combinatorial logic element. The insertion of the logic element is performed such that the arrival time of a signal to the input of the inserted logic element occurs before half of a clock cycle and the propagation time of the input signal from the inserted logic element to the destination element is less than half the clock cycle. The modified netlist of the path of the integrated circuit incorporating the inserted logic element is stored in memory of a computing system.
摘要翻译：提出了一种集成电路设计路径中抖动降低的方法。首先分析该路径以识别在源元素和目的地元素之间限定的组合逻辑元素。输入信号到组合逻辑元件的到达时间通过在组合逻辑元件的输入处插入逻辑元件来移位。执行逻辑元件的插入使得信号到插入的逻辑元件的输入的到达时间发生在时钟周期的一半之前，并且输入信号从插入的逻辑元件到目的地元件的传播时间较少超过了一半的时钟周期。将插入的逻辑元件的集成电路的路径的修改网表存储在计算系统的存储器中。

6. 发明授权

US08929162B1 Gating and sampling a data strobe signal using a shared enable signal 有权
标题翻译：使用共享使能信号对数据选通信号进行选通和采样
公开(公告)号：US08929162B1
公开(公告)日：2015-01-06
申请号：US13531430
申请日：2012-06-22
申请人： Joshua David Fender , Gordon Raymond Chiu , Ryan Fung
发明人： Joshua David Fender , Gordon Raymond Chiu , Ryan Fung
IPC分类号： G11C7/22 , G11C7/10
CPC分类号： G11C7/1051 , G11C7/1066
摘要： In a memory interface circuit (e.g., a programmable logic device), a clock or strobe (DQS) signal can be gated using a clock-like signal that can also be used to sample the DQS signal. Furthermore, both the rising and falling edges of the DQS signal can be sampled using the clock-like signal.
摘要翻译：在存储器接口电路（例如，可编程逻辑器件）中，时钟或选通（DQS）信号可以使用也可用于采样DQS信号的类似时钟的信号来选通。此外，可以使用类似时钟的信号对DQS信号的上升沿和下降沿进行采样。

7. 发明授权

US08694946B1 Simultaneous switching noise optimization 有权
标题翻译：同时开关噪声优化
公开(公告)号：US08694946B1
公开(公告)日：2014-04-08
申请号：US12465452
申请日：2009-05-13
申请人： Joshua David Fender , Navid Azizi , Paul Leventis
发明人： Joshua David Fender , Navid Azizi , Paul Leventis
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F17/504 , G06F2217/82
摘要： This invention provides methods, computer program products, and systems to guide a user in optimizing the Simultaneous Switching Noise (SSN) of an electronic device by using visual approaches on a graphical user interface (GUI). Also provided is an interactive feedback mechanism that enables the user to evaluate the effectiveness of an optimization method. A matrix representation of the different I/O pins on the device shows the level of SSN at different victim pins caused by switching aggressor pins. The SSN is depicted using different graphical representations. Associated with the SSN of each victim pin is the graphical representation of its accuracy. The accuracy rating denotes the reliability of the SSN and is an indication of how sensitive a victim pin is to errors. In the interactive feedback mechanism, user input on SSN optimization is received and used to calculate the new SSN and accuracy rating of different victim pins on the device. The new data is then updated in a timely manner on the GUI.
摘要翻译：本发明提供了通过使用图形用户界面（GUI）上的可视方法来指导用户优化电子设备的同时切换噪声（SSN）的方法，计算机程序产品和系统。还提供了一种交互式反馈机制，使得用户能够评估优化方法的有效性。设备上不同I / O引脚的矩阵表示显示了由切换引脚引起的不同受扰引脚上的SSN电平。使用不同的图形表示描绘SSN。与每个受害者引脚的SSN相关联的是其精度的图形表示。精度等级表示SSN的可靠性，并且表示受害者引脚对错误的敏感程度。在交互式反馈机制中，接收SSN优化用户输入，用于计算设备上不同受害引脚的新SSN和精度等级。然后在GUI上及时更新新数据。

8. 发明授权

US08499201B1 Methods and systems for measuring and presenting performance data of a memory controller system 有权
标题翻译：用于测量和呈现存储器控制器系统的性能数据的方法和系统
公开(公告)号：US08499201B1
公开(公告)日：2013-07-30
申请号：US12841762
申请日：2010-07-22
申请人： Gordon Raymond Chiu , Joshua David Fender , Clement C. Tse , Deshanand Singh
发明人： Gordon Raymond Chiu , Joshua David Fender , Clement C. Tse , Deshanand Singh
IPC分类号： G06F11/00
CPC分类号： G06F11/3037 , G06F11/32 , G06F11/3419 , G06F11/3471 , G06F11/349 , G06F2201/88
摘要： Mechanisms for measuring, analyzing, and presenting performance data associated with a memory controller system are described. The mechanisms include a performance monitor that detects and analyzes performance including efficiency and latency of a memory controller system. In addition to determining performance, the systems identifies reasons for loss of memory controller system efficiency. Moreover, the reasons, the efficiency, and the latency are analyzed and presented in a manner easily understandable to a user.
摘要翻译：描述了与存储器控制器系统相关联的测量，分析和呈现性能数据的机制。这些机制包括一个性能监视器，用于检测和分析性能，包括内存控制器系统的效率和延迟。除了确定性能外，系统还确定了内存控制器系统效率损失的原因。此外，原因，效率和延迟以对用户容易理解的方式进行分析和呈现。

9. 发明授权

US08443321B1 Pessimism removal in the modeling of simultaneous switching noise 有权
标题翻译：同步开关噪声建模中的悲观消除
公开(公告)号：US08443321B1
公开(公告)日：2013-05-14
申请号：US12137407
申请日：2008-06-11
申请人： Joshua David Fender , Kamal Patel , Navid Azizi , Paul Leventis
发明人： Joshua David Fender , Kamal Patel , Navid Azizi , Paul Leventis
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F2217/82
摘要： Methods for determining induced noise on a given victim by a set of aggressor signals are presented, and for identifying the worst case aggressor switching time alignment that causes the worst case victim noise. The method removes circuit analysis pessimism related to simultaneous switching noise (SSN) in a circuit design tool by determining physically impossible combinations of victim-aggressor input/output (I/O) pins in a circuit design and culling out the impossible combinations from the list of possible victim-aggressor combinations. The method further performs a switching window SSN analysis of the circuit design with a common uncertainty removal algorithm taking into consideration the list of possible victim-aggressor combinations, and determines the maximum voltage noise induced on I/O pins of the circuit design. The results of the noise analysis are displayed to the user.
摘要翻译：提出了通过一组侵略者信号确定给定受害者的感应噪声的方法，并且用于识别导致最坏情况的受害者噪声的最坏情况侵权者切换时间对准。该方法通过确定电路设计中的受害者 - 侵入者输入/输出（I / O）引脚的物理不可能组合，并从列表中剔除不可能的组合，从而消除了电路设计工具中与同时开关噪声（SSN）相关的电路分析悲观情绪可能的受害者 - 侵略者组合。该方法还考虑到可能的受害者 - 侵略者组合的列表，执行具有公共不确定性去除算法的电路设计的切换窗口SSN分析，并且确定在电路设计的I / O引脚上引起的最大电压噪声。噪声分析的结果显示给用户。

10. 发明授权

US08402402B1 Method for calculating a mixed I/O standard simultaneous switching noise (SSN) using a non-mixed I/O standard SSN model 有权
标题翻译：使用非混合I / O标准SSN模型计算混合I / O标准同时开关噪声（SSN）的方法
公开(公告)号：US08402402B1
公开(公告)日：2013-03-19
申请号：US11946380
申请日：2007-11-28
申请人： Joshua David Fender
发明人： Joshua David Fender
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F2217/82
摘要： A method for determining simultaneous switching noise for multiple Input/Output (I/O) standards is provided by calculating incremental noise for the multiple I/O standards by considering a cumulative amount of noise contributed by previously assigned pins. In another embodiment, the number of pins being placed is considered rather than the cumulative amount of noise. When considering the cumulative amount of noise the I/O noise from corresponding I/O standards are characterized and a greater contributor is identified so that the I/O standard associated with the greater contributor can be assigned.
摘要翻译：通过考虑由先前分配的引脚贡献的累积噪声量，通过计算多个I / O标准的增量噪声来提供用于确定多个输入/输出（I / O）标准的同时开关噪声的方法。在另一个实施例中，考虑放置的引脚的数量而不是累积的噪声量。当考虑累积噪声量时，对来自相应I / O标准的I / O噪声进行了表征，并且识别出更大的贡献者，从而可以分配与较大贡献者相关联的I / O标准。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式