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1. 发明申请

US20100205399A1 PERFORMANCE COUNTER FOR MICROCODE INSTRUCTION EXECUTION 审中-公开
标题翻译： MICROCODE指令执行性能计数器
公开(公告)号：US20100205399A1
公开(公告)日：2010-08-12
申请号：US12370586
申请日：2009-02-12
申请人： Brent Bean , Jui-Shuan Chen , G. Glenn Henry , Terry Parks
发明人： Brent Bean , Jui-Shuan Chen , G. Glenn Henry , Terry Parks
IPC分类号： G06F9/32
CPC分类号： G06F11/3466 , G06F11/3471 , G06F2201/88
摘要： An apparatus for counting microcode instruction execution in a microprocessor includes a first register, a second register, a comparator, and a counter. The first register stores an address of a microcode instruction. The microcode instruction is stored in a microcode memory of the microprocessor. The second register stores an address of the next microcode instruction to be retired by a retire unit of the microprocessor. The comparator compares the addresses stored in the first and second registers to indicate a match between them. The counter counts the number of times the comparator indicates a match between the addresses stored in the first register and the second register. The first register is user-programmable and the counter is user-readable. A mask register may be included to create a range of microcode memory addresses so that executions of microcode instructions within the range are counted.
摘要翻译：用于计数微处理器中微代码指令执行的装置包括第一寄存器，第二寄存器，比较器和计数器。第一个寄存器存储微码指令的地址。微代码指令存储在微处理器的微代码存储器中。第二寄存器存储由微处理器的退出单元退出的下一微代码指令的地址。比较器比较存储在第一和第二寄存器中的地址，以指示它们之间的匹配。计数器计数比较器指示存储在第一个寄存器和第二个寄存器中的地址之间的匹配次数。第一个寄存器是用户可编程的，计数器是用户可读的。可以包括掩码寄存器来创建微码存储器地址的范围，从而对范围内的微代码指令的执行进行计数。

2. 发明授权

US08443175B2 Microprocessor with first processor for debugging second processor 有权
标题翻译：具有第一处理器的微处理器用于调试第二处理器
公开(公告)号：US08443175B2
公开(公告)日：2013-05-14
申请号：US12748753
申请日：2010-03-29
申请人： G. Glenn Henry , Jui-Shuan Chen
发明人： G. Glenn Henry , Jui-Shuan Chen
IPC分类号： G06F15/00 , G06F15/76 , G06F9/44 , G06F9/00 , G06F7/38 , G06F11/00
CPC分类号： G06F11/362
摘要： A microprocessor integrated circuit includes first and second processors, an internal memory accessible by the first and second processors, and a bus interface unit configured to interface to a bus external to the microprocessor for providing access to a memory external to the microprocessor. The bus interface unit, external bus, and external memory are accessible by the second processor but are inaccessible by the first processor. The first processor writes debug information to the internal memory. The first processor detects an event and provides a notification of the event to the second processor. The second processor, coupled to the bus interface unit, executes microcode in response to the event notification received from the first processor. The microcode reads the debug information from the internal memory and writes the debug information to the external memory via the bus interface unit and external bus for use in debugging the second processor.
摘要翻译：微处理器集成电路包括第一和第二处理器，由第一和第二处理器可访问的内部存储器，以及总线接口单元，被配置为与微处理器外部的总线接口以提供对微处理器外部的存储器的访问。总线接口单元，外部总线和外部存储器可由第二处理器访问，但由第一处理器无法访问。第一个处理器将调试信息写入内部存储器。第一处理器检测事件并向第二处理器提供事件的通知。耦合到总线接口单元的第二处理器响应于从第一处理器接收到的事件通知而执行微代码。微代码从内部存储器读取调试信息，并通过总线接口单元和外部总线将调试信息写入外部存储器，用于调试第二个处理器。

3. 发明授权

US08495344B2 Simultaneous execution resumption of multiple processor cores after core state information dump to facilitate debugging via multi-core processor simulator using the state information 有权
标题翻译：在核心状态信息转储后同时执行多个处理器核心，以便通过使用状态信息的多核处理器模拟器进行调试
公开(公告)号：US08495344B2
公开(公告)日：2013-07-23
申请号：US12748929
申请日：2010-03-29
申请人： G. Glenn Henry , Jui-Shuan Chen
发明人： G. Glenn Henry , Jui-Shuan Chen
IPC分类号： G06F7/38 , G06F9/00 , G06F9/44 , G06F11/00
CPC分类号： G06F9/3885 , G06F9/3861 , G06F11/3636
摘要： A multi-core microprocessor includes first and second processing cores and a bus coupling the first and second processing cores. The bus conveys messages between the first and second processing cores. The cores are configured such that: the first core stops executing user instructions and interrupts the second core via the bus, in response to detecting a predetermined event; the second core stops executing user instructions, in response to being interrupted by the first core; each core outputs its state after it stops executing user instructions; and each core waits to begin fetching and executing user instructions until it receives a notification from the other core via the bus that the other core is ready to begin fetching and executing user instructions. In one embodiment, the predetermined event comprises detecting that the first core has retired a predetermined number of instructions. In one embodiment, microcode waits for the notification.
摘要翻译：多核微处理器包括第一和第二处理核心以及耦合第一和第二处理核心的总线。总线在第一和第二处理核之间传送消息。核心被配置为：响应于检测到预定事件，第一核心停止执行用户指令并经由总线中断第二核心; 第二核心响应于被第一核心中断而停止执行用户指令; 每个核心在停止执行用户指令后输出其状态; 并且每个核心等待开始获取和执行用户指令，直到其经由总线从另一个核心接收到另一个核心准备开始获取和执行用户指令的通知。在一个实施例中，预定事件包括检测第一核已经退出预定数量的指令。在一个实施例中，微代码等待通知。

4. 发明授权

US08464032B2 Microprocessor integrated circuit with first processor that outputs debug information in response to reset by second processor of the integrated circuit 有权
标题翻译：具有第一处理器的微处理器集成电路，其响应于集成电路的第二处理器的复位而输出调试信息
公开(公告)号：US08464032B2
公开(公告)日：2013-06-11
申请号：US12748846
申请日：2010-03-29
申请人： G. Glenn Henry , Jui-Shuan Chen
发明人： G. Glenn Henry , Jui-Shuan Chen
IPC分类号： G06F7/38 , G06F9/00 , G06F9/44 , G06F11/00
CPC分类号： G06F11/362
摘要： A microprocessor integrated circuit includes first and second processors. The first processor is configured to detect that the second processor has not retired an instruction for a predetermined amount of clock cycles and to responsively reset the second processor. The microprocessor integrated circuit also includes microcode. The second processor is configured to execute the microcode in response to a reset of the second processor. The microcode is configured to read debug information within the microprocessor integrated circuit and to output the debug information external to the microprocessor integrated circuit in response to determining that the reset was performed by the first processor.
摘要翻译：微处理器集成电路包括第一和第二处理器。第一处理器被配置为检测第二处理器没有退出用于预定量的时钟周期的指令并且响应地重置第二处理器。微处理器集成电路还包括微码。第二处理器被配置为响应于第二处理器的复位来执行微代码。微代码被配置为读取微处理器集成电路内的调试信息，并响应于确定由第一处理器执行复位而将微处理器集成电路外部的调试信息输出。

5. 发明申请

US20110010531A1 DEBUGGABLE MICROPROCESSOR 有权
标题翻译：可调式微处理器
公开(公告)号：US20110010531A1
公开(公告)日：2011-01-13
申请号：US12748846
申请日：2010-03-29
申请人： G. Glenn Henry , Jui-Shuan Chen
发明人： G. Glenn Henry , Jui-Shuan Chen
IPC分类号： G06F9/30
CPC分类号： G06F11/362
摘要： A microprocessor integrated circuit includes first and second processors. The first processor is configured to detect that the second processor has not retired an instruction for a predetermined amount of clock cycles and to responsively reset the second processor. The microprocessor integrated circuit also includes microcode. The second processor is configured to execute the microcode in response to a reset of the second processor. The microcode is configured to read debug information within the microprocessor integrated circuit and to output the debug information external to the microprocessor integrated circuit in response to determining that the reset was performed by the first processor.
摘要翻译：微处理器集成电路包括第一和第二处理器。第一处理器被配置为检测第二处理器没有退出用于预定量的时钟周期的指令并且响应地重置第二处理器。微处理器集成电路还包括微码。第二处理器被配置为响应于第二处理器的复位来执行微代码。微代码被配置为读取微处理器集成电路内的调试信息，并响应于确定由第一处理器执行复位而将微处理器集成电路外部的调试信息输出。

6. 发明申请

US20110010530A1 MICROPROCESSOR WITH INTEROPERABILITY BETWEEN SERVICE PROCESSOR AND MICROCODE-BASED DEBUGGER 有权
标题翻译：在服务处理器和基于微处理器的调试器之间具有互操作性的微处理器
公开(公告)号：US20110010530A1
公开(公告)日：2011-01-13
申请号：US12748753
申请日：2010-03-29
申请人： G. Glenn Henry , Jui-Shuan Chen
发明人： G. Glenn Henry , Jui-Shuan Chen
IPC分类号： G06F9/30
CPC分类号： G06F11/362
摘要： A microprocessor integrated circuit includes first and second processors, an internal memory accessible by the first and second processors, and a bus interface unit configured to interface to a bus external to the microprocessor for providing access to a memory external to the microprocessor. The bus interface unit, external bus, and external memory are accessible by the second processor but are inaccessible by the first processor. The first processor writes debug information to the internal memory. The first processor detects an event and provides a notification of the event to the second processor. The second processor, coupled to the bus interface unit, executes microcode in response to the event notification received from the first processor. The microcode reads the debug information from the internal memory and writes the debug information to the external memory via the bus interface unit and external bus for use in debugging the second processor.
摘要翻译：微处理器集成电路包括第一和第二处理器，由第一和第二处理器可访问的内部存储器，以及总线接口单元，被配置为与微处理器外部的总线接口以提供对微处理器外部的存储器的访问。总线接口单元，外部总线和外部存储器可由第二处理器访问，但由第一处理器无法访问。第一个处理器将调试信息写入内部存储器。第一处理器检测事件并向第二处理器提供事件的通知。耦合到总线接口单元的第二处理器响应于从第一处理器接收到的事件通知而执行微代码。微代码从内部存储器读取调试信息，并通过总线接口单元和外部总线将调试信息写入外部存储器，用于调试第二个处理器。

7. 发明申请

US20110185153A1 SIMULTANEOUS EXECUTION RESUMPTION OF MULTIPLE PROCESSOR CORES AFTER CORE STATE INFORMATION DUMP TO FACILITATE DEBUGGING VIA MULTI-CORE PROCESSOR SIMULATOR USING THE STATE INFORMATION 有权
标题翻译：核心国家信息通过使用状态信息的多核处理器模拟器进行调试来同时调试多个处理器之间的同时执行恢复
公开(公告)号：US20110185153A1
公开(公告)日：2011-07-28
申请号：US12748929
申请日：2010-03-29
申请人： G. Glenn Henry , Jui-Shuan Chen
发明人： G. Glenn Henry , Jui-Shuan Chen
IPC分类号： G06F15/76 , G06F9/02
CPC分类号： G06F9/3885 , G06F9/3861 , G06F11/3636
摘要： A multi-core microprocessor includes first and second processing cores and a bus coupling the first and second processing cores. The bus conveys messages between the first and second processing cores. The cores are configured such that: the first core stops executing user instructions and interrupts the second core via the bus, in response to detecting a predetermined event; the second core stops executing user instructions, in response to being interrupted by the first core; each core outputs its state after it stops executing user instructions; and each core waits to begin fetching and executing user instructions until it receives a notification from the other core via the bus that the other core is ready to begin fetching and executing user instructions. In one embodiment, the predetermined event comprises detecting that the first core has retired a predetermined number of instructions. In one embodiment, microcode waits for the notification.
摘要翻译：多核微处理器包括第一和第二处理核心以及耦合第一和第二处理核心的总线。总线在第一和第二处理核之间传送消息。核心被配置为：响应于检测到预定事件，第一核心停止执行用户指令并经由总线中断第二核心; 第二核心响应于被第一核心中断而停止执行用户指令; 每个核心在停止执行用户指令后输出其状态; 并且每个核心等待开始获取和执行用户指令，直到其经由总线从另一个核心接收到另一个核心准备开始获取和执行用户指令的通知。在一个实施例中，预定事件包括检测第一核已经退出预定数量的指令。在一个实施例中，微代码等待通知。

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