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1. 外观设计

USD739412S1 Portable electronic device with GUI 有权
标题翻译：带GUI的便携式电子设备
公开(公告)号：USD739412S1
公开(公告)日：2015-09-22
申请号：US29425904
申请日：2012-06-28
申请人： Hang Sik Shin , Jung Hoon Park , Hyun Gok Yoo , Sungjoo Ahn
设计人： Hang Sik Shin , Jung Hoon Park , Hyun Gok Yoo , Sungjoo Ahn

2. 发明授权

US08612841B2 Error code pattern generation circuit and semiconductor memory device including the same 有权
标题翻译：误差码图案生成电路和包括其的半导体存储器件
公开(公告)号：US08612841B2
公开(公告)日：2013-12-17
申请号：US12980450
申请日：2010-12-29
申请人： Jung-Hoon Park
发明人： Jung-Hoon Park
IPC分类号： G06F11/00
CPC分类号： G06F11/1004 , G11C2029/0411
摘要： An error code pattern generation circuit includes a first storage unit configured to store at least one bit of an error code, and output error data for a first time period; and a second storage unit configured to store at least one remaining bit of the error code and output the error data for a second time period which is different from the first time period.
摘要翻译：错误码图案生成电路包括被配置为存储错误代码的至少一个位的第一存储单元，以及第一时间段的输出错误数据; 以及第二存储单元，被配置为存储错误代码的至少一个剩余位，并且输出与第一时间段不同的第二时间段的错误数据。

3. 发明授权

US08570808B2 Nonvolatile memory device with 3D memory cell array 有权
标题翻译：具有3D存储单元阵列的非易失性存储器件
公开(公告)号：US08570808B2
公开(公告)日：2013-10-29
申请号：US13186987
申请日：2011-07-20
申请人： Jung-hoon Park , Kyung-Hwa Kang , Chi-Weon Yoon , Sang-Wan Nam , Sung-Won Yun
发明人： Jung-hoon Park , Kyung-Hwa Kang , Chi-Weon Yoon , Sang-Wan Nam , Sung-Won Yun
IPC分类号： G11C16/04
CPC分类号： G11C11/5642 , G11C16/0483 , G11C16/06 , G11C16/3454 , H01L27/11582 , H01L29/7926
摘要： A nonvolatile memory device includes a 3D memory cell array having words lines that extend from a lowest memory cell array layer closest to a substrate to a highest memory cell array layer farthest from the substrate, a voltage generator circuit generating first and second voltage signals, and a row selecting circuit that simultaneously applies the first voltage signal to a selected word line and the second voltage signal to an unselected word line. The selected word line and the unselected word line have different resistances, yet the first voltage signal is applied to the selected word line and the second voltage signal is applied to the unselected word line with a same rising slope over a defined period of time.
摘要翻译：非易失性存储器件包括具有从最靠近衬底的最低存储单元阵列层延伸到离衬底最远的最高存储单元阵列层的字线的3D存储单元阵列，产生第一和第二电压信号的电压发生器电路，以及行选择电路，其将所述第一电压信号同时施加到所选择的字线，并将所述第二电压信号施加到未选择的字线。所选择的字线和未选字线具有不同的电阻，而第一电压信号被施加到所选择的字线，并且第二电压信号在规定的时间段内以相同的上升斜率施加到未选择的字线。

4. 发明授权

US08476943B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08476943B2
公开(公告)日：2013-07-02
申请号：US12345079
申请日：2008-12-29
申请人： Jung-Hoon Park
发明人： Jung-Hoon Park
IPC分类号： H04L7/00
CPC分类号： G11C7/22 , G11C7/222 , G11C2207/2254
摘要： A semiconductor device includes: a clock input unit configured to receive a system clock and a data clock externally; a phase dividing unit configured to generate a plurality of multi-system clocks in response to the system clock, wherein each of the multi-system clocks has an individual phase difference; a phase detecting unit configured to detect phase differences between the plurality of multi-system clock and the data clock and to generating generate a training information signal in response to the detection result; and a signal transmitting unit configured to transmit the training information signal.
摘要翻译：半导体器件包括：时钟输入单元，被配置为从外部接收系统时钟和数据时钟; 相位分离单元，被配置为响应于系统时钟产生多个多系统时钟，其中每个多系统时钟具有单独的相位差; 相位检测单元，被配置为检测所述多个多系统时钟与所述数据时钟之间的相位差，并响应于所述检测结果产生生成训练信息信号; 以及信号发送单元，被配置为发送训练信息信号。

5. 发明授权

US08320205B2 Semiconductor memory device, semiconductor system including the semiconductor memory device, and method for operating the semiconductor memory device 有权
标题翻译：半导体存储器件，包括半导体存储器件的半导体系统以及用于操作半导体存储器件的方法
公开(公告)号：US08320205B2
公开(公告)日：2012-11-27
申请号：US12832815
申请日：2010-07-08
申请人： Jung-Hoon Park
发明人： Jung-Hoon Park
IPC分类号： G11C7/00
CPC分类号： G11C7/04 , G11C7/1051 , G11C7/1066 , G11C7/1078 , G11C7/1093 , G11C29/022 , G11C29/023 , G11C29/028 , G11C2207/2254
摘要： A semiconductor memory device includes a first data input/output unit configured to receive a normal training data, whose data window is scanned based on an edge of a source clock, in response to a training input command, and output a data in a state where an edge of the data window is synchronized with the edge of the source clock in response to a training output command, and a second data input/output unit configured to receive a recovery information training data, whose data window is scanned based on the edge of the source clock, in response to the training input command, and output a data in a state where an edge of a data window is synchronized with the edge of the source clock in response to the training output command.
摘要翻译：半导体存储器件包括：第一数据输入/输出单元，被配置为响应于训练输入命令接收基于源时钟的边缘扫描其数据窗口的正常训练数据，并且在以下状态下输出数据：响应于训练输出命令，数据窗口的边缘与源时钟的边沿同步，以及第二数据输入/输出单元，被配置为接收恢复信息训练数据，该数据窗口的数据窗口基于源时钟，响应于训练输入命令，并且响应于训练输出命令，在数据窗口的边缘与源时钟的边沿同步的状态下输出数据。

6. 发明申请

US20120262999A1 SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF 有权
标题翻译：半导体存储器件及其工作方法
公开(公告)号：US20120262999A1
公开(公告)日：2012-10-18
申请号：US13334023
申请日：2011-12-21
申请人： Jung-Hoon PARK
发明人： Jung-Hoon PARK
IPC分类号： G11C8/18
CPC分类号： G11C8/18
摘要： A semiconductor memory device includes a system clock input block configured to be inputted with a system clock, a data clock input block configured to be inputted with a data clock, a first phase detection block configured to compare a phase of the system clock, generate a first phase detection signal, and determine a logic level of a reverse control signal in response to the first phase detection signal, a second phase detection block configured to compare a phase of a clock acquired by delaying the system clock by a correction time, generate a second phase detection signal, and determine a logic level of a clock select signal in response to the first and second phase detection signals, and a clock select block configured to select and output the data clock or a clock acquired by delaying the data clock.
摘要翻译：一种半导体存储器件，包括被配置为输入系统时钟的系统时钟输入块，被配置为输入数据时钟的数据时钟输入块，被配置为比较系统时钟的相位的第一相位检测块，第一相位检测信号，并且响应于第一相位检测信号确定反向控制信号的逻辑电平;第二相位检测块，被配置为通过将系统时钟延迟校正时间来获取的时钟的相位进行比较，生成第二相位检测信号，并且响应于第一和第二相位检测信号确定时钟选择信号的逻辑电平;以及时钟选择块，被配置为选择和输出数据时钟或通过延迟数据时钟获取的时钟。

7. 发明申请

US20120201417A1 APPARATUS AND METHOD FOR PROCESSING SENSORY EFFECT OF IMAGE DATA 有权
标题翻译：用于处理图像数据的感觉效应的装置和方法
公开(公告)号：US20120201417A1
公开(公告)日：2012-08-09
申请号：US13368820
申请日：2012-02-08
申请人： Jung-Hoon PARK , Kwang-Cheol CHOI , Je-Han YOON
发明人： Jung-Hoon PARK , Kwang-Cheol CHOI , Je-Han YOON
IPC分类号： G06K9/62
CPC分类号： G06F3/0304 , G06F3/016 , G06F3/017
摘要： A method and apparatus is capable of processing a sensory effect of image data. The apparatus includes an image analyzer that analyzes depth information and texture information about at least one object included in an image. A motion analyzer analyzes a motion of a user. An image matching processor matches the motion of the user to the image. An image output unit outputs the image to which the motion of the user is matched, and a sensory effect output unit outputs a texture of an object touched by the body of the user to the body of the user.
摘要翻译：一种方法和装置能够处理图像数据的感觉效果。该装置包括分析关于包括在图像中的至少一个对象的深度信息和纹理信息的图像分析器。运动分析仪分析用户的运动。图像匹配处理器将用户的运动与图像相匹配。图像输出单元输出用户的运动匹配的图像，感觉效果输出单元将用户身体触摸的对象的纹理输出到用户的身体。

8. 发明申请

US20120144278A1 ERROR CODE PATTERN GENERATION CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME 有权
标题翻译：错误代码图案生成电路和包括其的半导体存储器件
公开(公告)号：US20120144278A1
公开(公告)日：2012-06-07
申请号：US12980450
申请日：2010-12-29
申请人： Jung-Hoon PARK
发明人： Jung-Hoon PARK
IPC分类号： H03M13/09 , G06F11/10
CPC分类号： G06F11/1004 , G11C2029/0411
摘要： An error code pattern generation circuit includes a first storage unit configured to store at least one bit of an error code, and output error data for a first time period; and a second storage unit configured to store at least one remaining bit of the error code and output the error data for a second time period which is different from the first time period.
摘要翻译：错误码图案生成电路包括被配置为存储错误代码的至少一个位的第一存储单元，以及第一时间段的输出错误数据; 以及第二存储单元，被配置为存储错误代码的至少一个剩余位，并且输出与第一时间段不同的第二时间段的错误数据。

9. 发明授权

US08115524B2 Semiconductor device having auto clock alignment training mode circuit 有权
标题翻译：具有自动时钟对准训练模式电路的半导体器件
公开(公告)号：US08115524B2
公开(公告)日：2012-02-14
申请号：US12630518
申请日：2009-12-03
申请人： Young-Ran Kim , Jung-Hoon Park
发明人： Young-Ran Kim , Jung-Hoon Park
IPC分类号： G11C8/18 , H03L7/00
CPC分类号： G06F1/12 , G06F1/06
摘要： A semiconductor device for applying an auto clock alignment training mode to reduce the time required for a clock alignment training operation. The semiconductor device adjusts the entry time of the auto clock alignment training mode to prevent the clock alignment training operation from malfunctioning. The semiconductor device includes a clock division block configured to divide a data clock to generate a data division clock, a phase multiplex block configured to generate a plurality of multiple data division clocks in response to the data division clock, a logic level control block configured to set a period, in which a division control signal is changeable, depending on the data division clock, and a first phase detection block configured to detect a phase of a system clock on the basis of the multiple data division clocks in the period, and to generate the division control signal corresponding to a detection result.
摘要翻译：一种用于施加自动时钟对准训练模式以减少时钟对准训练操作所需时间的半导体器件。半导体器件调整自动时钟对准训练模式的进入时间，以防止时钟对准训练操作发生故障。半导体器件包括：时钟分割块，被配置为分割数据时钟以产生数据分时钟;相位多路复用块，被配置为响应于所述数据分时钟产生多个多个数据分时钟;逻辑电平控制模块，被配置为根据数据分时钟设定分割控制信号可变的周期，以及第一相位检测块，被配置为基于该周期中的多个数据分时钟来检测系统时钟的相位，并且将第一相位检测块生成与检测结果对应的分割控制信号。

10. 发明申请

US20120033501A1 NONVOLATILE MEMORY DEVICE WITH 3D MEMORY CELL ARRAY 有权
标题翻译：具有3D存储单元阵列的非易失性存储器件
公开(公告)号：US20120033501A1
公开(公告)日：2012-02-09
申请号：US13186987
申请日：2011-07-20
申请人： Jung-hoon Park , Kyung-Hwa Kang , Chi-Weon Yoon , Sang-Wan Nam , Sung-Won Yun
发明人： Jung-hoon Park , Kyung-Hwa Kang , Chi-Weon Yoon , Sang-Wan Nam , Sung-Won Yun
IPC分类号： G11C16/10 , G11C16/04
CPC分类号： G11C11/5642 , G11C16/0483 , G11C16/06 , G11C16/3454 , H01L27/11582 , H01L29/7926
摘要： Disclosed is a nonvolatile memory device which includes a 3D memory cell array having words lines that extend from a lowest memory cell array layer closest to a substrate to a highest memory cell array layer farthest from the substrate, a voltage generator circuit generating first and second voltage signals, and a row selecting circuit that simultaneously applies the first voltage signal to a selected word line and the second voltage signal to an unselected word line. The selected word line and the unselected word line have different resistances, yet the first voltage signal is applied to the selected word line and the second voltage signal is applied to the unselected word line with a same rising slope over a defined period of time.
摘要翻译：公开了一种非易失性存储器件，其包括具有从最靠近衬底的最低存储单元阵列层延伸到离衬底最远的最高存储单元阵列层的字线的3D存储单元阵列，产生第一和第二电压的电压发生器电路信号和行选择电路，其将第一电压信号同时施加到所选字线，并将第二电压信号施加到未选字线。所选择的字线和未选择的字线具有不同的电阻，但是第一电压信号被施加到所选择的字线，并且第二电压信号在规定的时间段内以相同的上升斜率施加到未选择的字线。

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