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1. 发明授权

US08258568B2 Semiconductor device having an oxide film formed on a semiconductor substrate sidewall of an element region and on a sidewall of a gate electrode 有权
标题翻译：具有形成在元件区域的半导体衬底侧壁上和栅电极的侧壁上的氧化膜的半导体器件
公开(公告)号：US08258568B2
公开(公告)日：2012-09-04
申请号：US13044102
申请日：2011-03-09
申请人： Toshitake Yaegashi , Junichi Shiozawa
发明人： Toshitake Yaegashi , Junichi Shiozawa
IPC分类号： H01L29/788
CPC分类号： H01L29/78 , H01L27/105 , H01L27/11526 , H01L27/11529
摘要： A first isolation is formed on a semiconductor substrate, and a first element region is isolated via the first isolation. A first gate insulating film is formed on the first element region, and a first gate electrode is formed on the first gate insulating film. A second isolation is formed on the semiconductor substrate, and a second element region is isolated via the second isolation. A second gate insulating film is formed on the second element region, and a second gate electrode is formed on the second gate insulating film. A first oxide film is formed between the first isolation and the first element region. A second oxide film is formed between the second isolation and the second element region. The first isolation has a width narrower than the second isolation, and the first oxide film has a thickness thinner than the second oxide film.
摘要翻译：第一隔离形成在半导体衬底上，第一元件区通过第一隔离隔离。第一栅绝缘膜形成在第一元件区上，第一栅电极形成在第一栅极绝缘膜上。第二隔离形成在半导体衬底上，第二元件区通过第二隔离隔离。第二栅极绝缘膜形成在第二元件区域上，第二栅电极形成在第二栅极绝缘膜上。在第一隔离和第一元件区之间形成第一氧化膜。在第二隔离和第二元件区之间形成第二氧化膜。第一隔离物的宽度比第二隔离宽，第一氧化膜的厚度比第二氧化膜薄。

2. 发明授权

US08097503B2 Method of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08097503B2
公开(公告)日：2012-01-17
申请号：US12926357
申请日：2010-11-12
申请人： Isao Kamioka , Junichi Shiozawa , Ryu Kato , Yoshio Ozawa
发明人： Isao Kamioka , Junichi Shiozawa , Ryu Kato , Yoshio Ozawa
IPC分类号： H01L21/337 , H01L21/8236
CPC分类号： H01L29/7881 , H01L21/76208 , H01L27/11521 , H01L29/66825
摘要： A method of manufacturing a semiconductor device according to an embodiment of the present invention includes forming, on a surface of a semiconductor substrate, an isolation trench including sidewall parts and a bottom part, or a stepped structure including a first planar part, a second planar part, and a step part located at a boundary between the first planar part and the second planar part, and supplying oxidizing ions or nitriding ions contained in plasma generated by a microwave, a radio-frequency wave, or electron cyclotron resonance to the sidewall parts and the bottom part of the isolation trench or the first and second planar parts and the step part of the stepped structure by applying a predetermined voltage to the semiconductor substrate, to perform anisotropic oxidation or anisotropic nitridation of the sidewall parts and the bottom part of the isolation trench or the first and second planar parts and the step part of the stepped structure.
摘要翻译：根据本发明实施例的制造半导体器件的方法包括在半导体衬底的表面上形成包括侧壁部分和底部的隔离沟槽，或者包括第一平面部分，第二平面部分部分和位于第一平面部分和第二平面部分之间的边界处的阶梯部分，并且将由微波产生的等离子体中产生的等离子体中的氧离子或氮化离子，射频波或电子回旋共振提供给侧壁部分以及通过向半导体衬底施加预定电压来隔离沟槽的底部或第一和第二平面部分和台阶部分的台阶部分，以进行侧壁部分和底部部分的各向异性氧化或各向异性氮化隔离沟槽或第一和第二平面部分以及台阶结构的阶梯部分。

3. 发明授权

US07927949B2 Semiconductor memory device and method of manufacturing the same 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US07927949B2
公开(公告)日：2011-04-19
申请号：US12755532
申请日：2010-04-07
申请人： Yoshio Ozawa , Isao Kamioka , Junichi Shiozawa , Akihito Yamamoto , Ryota Fujitsuka , Yoshihiro Ogawa , Katsuaki Natori , Katsuyuki Sekine , Masayuki Tanaka , Daisuke Nishida
发明人： Yoshio Ozawa , Isao Kamioka , Junichi Shiozawa , Akihito Yamamoto , Ryota Fujitsuka , Yoshihiro Ogawa , Katsuaki Natori , Katsuyuki Sekine , Masayuki Tanaka , Daisuke Nishida
IPC分类号： H01L21/336 , H01L21/8238 , H01L21/3205 , H01L21/4763
CPC分类号： H01L27/115 , H01L27/11521
摘要： A semiconductor memory device manufacturing method includes forming a floating gate electrode above a semiconductor substrate, forming an interelectrode insulating film above the floating gate electrode, forming a first radical nitride film on a surface of the interelectrode insulating film by first radical nitriding, and forming a control gate electrode on the first radical nitride film.
摘要翻译：一种半导体存储器件制造方法，包括在半导体衬底上形成浮置栅电极，在浮置栅电极上形成电极间绝缘膜，通过第一自由基氮化在电极间绝缘膜的表面上形成第一自由基氮化物膜，第一自由基氮化物膜上的控制栅电极。

4. 发明授权

US07679127B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07679127B2
公开(公告)日：2010-03-16
申请号：US11769304
申请日：2007-06-27
申请人： Junichi Shiozawa , Takeo Furuhata , Akiko Sekihara
发明人： Junichi Shiozawa , Takeo Furuhata , Akiko Sekihara
IPC分类号： H01L29/423 , H01L21/28
CPC分类号： H01L29/42324 , H01L21/28273 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L29/513
摘要： A semiconductor device including a semiconductor substrate; a first gate insulating film formed on the semiconductor substrate; a first gate electrode layer formed on the first gate insulating film; an element isolation insulating film formed so as to isolate a plurality of the first gate electrode layers; a second gate insulating film layer formed so as to cover upper surfaces of the plurality of first gate electrode layers and the element isolation insulating films; and a second gate electrode layer formed on the second gate insulating film layer; and the second gate insulating film layer includes a NONON stacked film structure and a nitride film layer contacting the first gate electrode layer and constituting a lowermost layer of the NONON stack film structure is separated at a portion interposing the plurality of neighboring first gate electrode layers.
摘要翻译：一种半导体器件，包括半导体衬底; 形成在所述半导体基板上的第一栅极绝缘膜; 形成在所述第一栅极绝缘膜上的第一栅极电极层; 形成为隔离多个第一栅极电极层的元件隔离绝缘膜; 形成为覆盖多个第一栅电极层和元件隔离绝缘膜的上表面的第二栅极绝缘膜层; 以及形成在所述第二栅极绝缘膜层上的第二栅极电极层; 并且第二栅极绝缘膜层包括NONON层叠膜结构和与第一栅极电极层接触并构成NONON叠层膜结构的最下层的氮化物膜层在插入多个相邻的第一栅极电极层的部分处被分离。

5. 发明申请

US20100045982A1 PARTICLE COUNTER AND PARTICLE COUNTING DEVICE HAVING PARTICLE COUNTER, AND PARTICLE COUNTING SYSTEM AND ITS USE METHOD 审中-公开
标题翻译：具有颗粒计数器的颗粒计数器和颗粒计数装置，以及颗粒计数系统及其使用方法
公开(公告)号：US20100045982A1
公开(公告)日：2010-02-25
申请号：US12095465
申请日：2006-11-28
申请人： Haruhiro Tsuneta , Eiichi Sugioka , Hiroshi Tonouchi , Junichi Shiozawa , Kenichi Hayashi , Tetsuo Momose , Hiroaki Furihata
发明人： Haruhiro Tsuneta , Eiichi Sugioka , Hiroshi Tonouchi , Junichi Shiozawa , Kenichi Hayashi , Tetsuo Momose , Hiroaki Furihata
IPC分类号： G01N21/00 , G06F19/00 , G08B21/00
CPC分类号： G01N15/14 , G01N35/00613 , G01N2035/009
摘要： A particle counting device 11 for detecting and counting particles in a fluid to be measured comprises a measuring section 13 for detecting particles and a control section 12 for processing the output signal from the measuring section 13. When an abnormality occurs, a signal to issue a warning is generated. With this, a constant monitoring or observation is possible. Also, a particle counting system comprising a plurality of particle counting devices 11 and an information processing device 17 for processing the results of the counting by the particle processing devices 11 is also provided. The plurality of particle counting devices 11 are electrically connected to the information processing device 17 in multiple and in parallel. Alternately, a particle counting system comprising a plurality of particle counting devices 11 for detecting and counting particles in a fluid to be measured is also provided. To one of the plurality of particle counting devices 11, the other particle counting devices 11 are electrically connected in multiple and in parallel. Therefore, a particle counting system, the measurement time of which can be shortened while maintaining the accuracy of the measurement results, and its use method are provided relatively inexpensively.
摘要翻译：用于检测和计数待测流体中的颗粒的颗粒计数装置11包括用于检测颗粒的测量部分13和用于处理来自测量部分13的输出信号的控制部分12.当异常发生时，发出信号生成警告。因此，可以进行不断的监视或观察。此外，还提供了包括多个粒子计数装置11和用于处理粒子处理装置11的计数结果的信息处理装置17的粒子计数系统。多个粒子计数装置11以多个并行的方式与信息处理装置17电连接。或者，还提供了包括用于检测和计数待测量流体中的颗粒的多个颗粒计数装置11的颗粒计数系统。对于多个粒子计数装置11之一，其他粒子计数装置11以多个并联方式电连接。因此，在保持测定结果的精度的同时可以缩短测定时间的粒子计数系统及其使用方法相对便宜。

6. 发明授权

US07315073B2 Semiconductor device having an oxide film formed on a semiconductor substrate sidewall of an element region and on a sidewall of a gate electrode 有权
标题翻译：具有形成在元件区域的半导体衬底侧壁上和栅电极的侧壁上的氧化膜的半导体器件
公开(公告)号：US07315073B2
公开(公告)日：2008-01-01
申请号：US11109763
申请日：2005-04-20
申请人： Toshitake Yaegashi , Junichi Shiozawa
发明人： Toshitake Yaegashi , Junichi Shiozawa
IPC分类号： H01L21/336 , H01L29/76
CPC分类号： H01L29/78 , H01L27/105 , H01L27/11526 , H01L27/11529
摘要： A first isolation is formed on a semiconductor substrate, and a first element region is isolated via the first isolation. A first gate insulating film is formed on the first element region, and a first gate electrode is formed on the first gate insulating film. A second isolation is formed on the semiconductor substrate, and a second element region is isolated via the second isolation. A second gate insulating film is formed on the second element region, and a second gate electrode is formed on the second gate insulating film. A first oxide film is formed between the first isolation and the first element region. A second oxide film is formed between the second isolation and the second element region. The first isolation has a width narrower than the second isolation, and the first oxide film has a thickness thinner than the second oxide film.
摘要翻译：第一隔离形成在半导体衬底上，第一元件区通过第一隔离隔离。第一栅绝缘膜形成在第一元件区上，第一栅电极形成在第一栅极绝缘膜上。第二隔离形成在半导体衬底上，第二元件区通过第二隔离隔离。第二栅极绝缘膜形成在第二元件区域上，第二栅电极形成在第二栅极绝缘膜上。在第一隔离和第一元件区之间形成第一氧化膜。在第二隔离和第二元件区之间形成第二氧化膜。第一隔离物的宽度比第二隔离宽，第一氧化膜的厚度比第二氧化膜薄。

7. 发明申请

US20060157817A1 Semiconductor device having an oxide film formed on a semiconductor substrate sidewall of an element region and on a sidewall of a gate electrode 有权
标题翻译：具有形成在元件区域的半导体衬底侧壁上和栅电极的侧壁上的氧化膜的半导体器件
公开(公告)号：US20060157817A1
公开(公告)日：2006-07-20
申请号：US11109763
申请日：2005-04-20
申请人： Toshitake Yaegashi , Junichi Shiozawa
发明人： Toshitake Yaegashi , Junichi Shiozawa
IPC分类号： H01L21/336 , H01L29/76
CPC分类号： H01L29/78 , H01L27/105 , H01L27/11526 , H01L27/11529
摘要： A first isolation is formed on a semiconductor substrate, and a first element region is isolated via the first isolation. A first gate insulating film is formed on the first element region, and a first gate electrode is formed on the first gate insulating film. A second isolation is formed on the semiconductor substrate, and a second element region is isolated via the second isolation. A second gate insulating film is formed on the second element region, and a second gate electrode is formed on the second gate insulating film. A first oxide film is formed between the first isolation and the first element region. A second oxide film is formed between the second isolation and the second element region. The first isolation has a width narrower than the second isolation, and the first oxide film has a thickness thinner than the second oxide film.
摘要翻译：第一隔离形成在半导体衬底上，第一元件区通过第一隔离隔离。第一栅绝缘膜形成在第一元件区上，第一栅电极形成在第一栅极绝缘膜上。第二隔离形成在半导体衬底上，第二元件区通过第二隔离隔离。第二栅极绝缘膜形成在第二元件区域上，第二栅电极形成在第二栅极绝缘膜上。在第一隔离和第一元件区之间形成第一氧化膜。在第二隔离和第二元件区之间形成第二氧化膜。第一隔离物的宽度比第二隔离宽，第一氧化膜的厚度比第二氧化膜薄。

8. 发明授权

US5543348A Controlled recrystallization of buried strap in a semiconductor memory device 失效
标题翻译：半导体存储器件中埋置带的可控再结晶
公开(公告)号：US5543348A
公开(公告)日：1996-08-06
申请号：US412442
申请日：1995-03-29
申请人： Erwin Hammerl , Jack A. Mandelman , Herbert L. Ho , Junichi Shiozawa , Reinhard J. Stengl
发明人： Erwin Hammerl , Jack A. Mandelman , Herbert L. Ho , Junichi Shiozawa , Reinhard J. Stengl
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10861
摘要： A method of forming a coupled capacitor and transistor is provided. A trench is formed in a semiconductor substrate and an impurity-doped first conductive region is then formed by filling the trench with an impurity-doped first conductive material. The impurity-doped first conductive region is etched back to a first level within the trench. An insulating layer is then formed on a sidewall of the portion of the trench opened by the etching back of the impurity-doped first conductive region and a second conductive region is formed by filling the remainder of the trench with a second conductive material. The insulating layer and the second conductive region are etched back to a second level within the trench and an amorphous silicon layer is formed in the portion of the trench opened by the etching back of the insulating layer and the second conductive region. The undoped amorphous silicon layer is etched back to a third a level within the trench. The undoped amorphous silicon layer is then recrystallized. Impurities are outdiffused from the impurity-doped first conductive region to the semiconductor substrate through the recrystallized silicon layer. A source/drain region of the transistor is formed adjacent to an intersection of the trench and the surface of the semiconductor substrate. The outdiffused impurities and the recrystallized silicon layer constitute a buried strap for electrically connecting the first and second conductive layers in the trench to the source/drain region.
摘要翻译：提供一种形成耦合电容器和晶体管的方法。在半导体衬底中形成沟槽，然后通过用杂质掺杂的第一导电材料填充沟槽来形成杂质掺杂的第一导电区域。杂质掺杂的第一导电区域被回蚀刻到沟槽内的第一水平。然后在通过杂质掺杂的第一导电区域的蚀刻开口的沟槽部分的侧壁上形成绝缘层，并且通过用第二导电材料填充沟槽的其余部分形成第二导电区域。将绝缘层和第二导电区域回蚀刻到沟槽内的第二层，并且在通过绝缘层和第二导电区域的蚀刻打开的沟槽部分中形成非晶硅层。未掺杂的非晶硅层在沟槽内回蚀刻到第三级。然后将未掺杂的非晶硅层重结晶。杂质通过再结晶硅层从杂质掺杂的第一导电区向外延伸到半导体衬底。晶体管的源极/漏极区域形成为与沟槽和半导体衬底的表面的交点相邻。超扩散杂质和再结晶硅层构成用于将沟槽中的第一和第二导电层电连接到源极/漏极区域的掩埋带。

9. 发明授权

US5389570A Method of forming boron doped silicon layer and semiconductor 失效
标题翻译：硼掺杂硅层和半导体的形成方法
公开(公告)号：US5389570A
公开(公告)日：1995-02-14
申请号：US931787
申请日：1992-08-18
申请人： Junichi Shiozawa
发明人： Junichi Shiozawa
IPC分类号： C23C16/04 , C23C16/24 , H01L21/02 , H01L21/20 , H01L21/205 , H01L21/285 , H01L21/3105 , H01L21/3205 , H01L21/336 , H01L21/763 , H01L21/768 , H01L21/8242 , H01L23/522 , H01L27/10 , H01L27/108 , H01L29/78
CPC分类号： H01L21/76889 , C23C16/045 , C23C16/24 , H01L21/02381 , H01L21/0245 , H01L21/02488 , H01L21/02532 , H01L21/02579 , H01L21/0262 , H01L21/28525 , H01L21/3105 , H01L21/32055 , H01L21/763 , H01L21/76877 , H01L28/82 , H01L2924/0002
摘要： A semiconductor layer forming method including depositing a boron doped amorphous silicon layer on a substrate having many steps, projections or cavities, by thermal decomposition of a higher order silane gas and diborane gas at 150.degree.-450.degree. C. The diborane gas is supplied to the substrate in a reaction limited.
摘要翻译：一种半导体层形成方法，包括在150-450℃下通过高分子量的硅烷气体和乙硼烷气体的热分解，在具有多个台阶的基板上沉积硼掺杂的非晶硅层。将乙硼烷气体供应至反应中的底物受限制。

10. 发明授权

US4887345A Turret apparatus 失效
标题翻译：炮塔装置
公开(公告)号：US4887345A
公开(公告)日：1989-12-19
申请号：US106308
申请日：1987-10-09
申请人： Kazuharu Saito , Masao Hiraguri , Sadao Yamada , Junichi Shiozawa
发明人： Kazuharu Saito , Masao Hiraguri , Sadao Yamada , Junichi Shiozawa
IPC分类号： B23Q3/157 , B23Q39/02
CPC分类号： B23Q39/02 , B23Q3/15713 , B23Q2220/002 , Y10T29/5155 , Y10T483/1755 , Y10T483/176
摘要： In a turret apparatus with an automatic tool changer a turret head is rotatably provided on a body. The turret head has two main shafts arranged with an interval of 180 degrees about a rotary shaft. The two main shafts being disposed with an intersectional angle of 90 degrees therebetween so as to horizontally direct in an indexing position of the turret head. A rotary center of said turret head is horizontally directed so as to have an intersectional angle of 45 degrees with respect to each of said two main shafts. One of the main shafts is in on the working side when the other main shaft is on the stand-by side. An automatic tool changing arm and a tool stocker are arranged on the horizontal side portion of the main shaft on the stand-by side.
摘要翻译：在具有自动换刀器的转塔装置中，转塔头部可旋转地设置在主体上。转塔头部具有两个以旋转轴为间隔180度的主轴。两个主轴在其间具有90度的相交角度设置，以便水平地引导在转台头的分度位置。所述转塔头的旋转中心被水平地定向成相对于所述两个主轴中的每一个具有45度的相交角。当另一个主轴处于待机时，其中一个主轴处于工作侧。在待机主轴的水平侧部分上布置有自动换刀臂和工具储料器。

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