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1. 发明授权

US07266624B1 Programmable layered sub-system interface 有权
标题翻译：可编程分层子系统接口
公开(公告)号：US07266624B1
公开(公告)日：2007-09-04
申请号：US10177449
申请日：2002-06-20
申请人： Justin L. Gaither , Amjad Odet-Allah
发明人： Justin L. Gaither , Amjad Odet-Allah
IPC分类号： G06F13/12
CPC分类号： G06F13/12
摘要： A programmable layered sub-system interface includes an extension sub-layer module, a physical coding sub-layer module, a physical media attachment module, an input module, an output module, a 1st switch module and a 2nd switch module. The 1st switch module is coupled between the physical media attachment module and the physical coding sub-layer module. The 2nd switch module is operably coupled between the physical coding sub-layer module and the extension sub-layer module. The input and output modules are operably coupled to the 1st and 2nd switch modules. The 1st switch module provides various combinations of coupling between the physical media attachment module, the physical coding sub-layer module, the input module and the output module. The 2nd switch module provides combinations of coupling between the extension sub-layer module, the physical coding sub-layer module, the input module and the output module.
摘要翻译：可编程分层子系统接口包括扩展子层模块，物理编码子层模块，物理介质连接模块，输入模块，输出模块，第一交换模块和一个2 开关模块。第一交换模块耦合在物理介质连接模块和物理编码子层模块之间。第二开关模块可操作地耦合在物理编码子层模块和扩展子层模块之间。输入和输出模块可操作地耦合到第一和第二和第二开关模块。第一交换模块提供物理介质连接模块，物理编码子层模块，输入模块和输出模块之间的耦合的各种组合。第二开关模块提供扩展子层模块，物理编码子层模块，输入模块和输出模块之间的耦合的组合。

2. 发明授权

US07398341B1 Method and system for programmable input/output transceiver wherein transceiver is configurable to support a plurality of interface standards 有权
标题翻译：可编程输入/输出收发器的方法和系统，其中收发器可配置为支持多个接口标准
公开(公告)号：US07398341B1
公开(公告)日：2008-07-08
申请号：US10754683
申请日：2004-01-09
申请人： Justin L. Gaither
发明人： Justin L. Gaither
IPC分类号： G06F3/00 , H04B1/38 , H04M9/00
CPC分类号： H04L25/0298 , H03L7/091 , H04B1/406 , H04L7/0079 , H04L25/0278
摘要： A method and system for a programmable input/output transceiver is disclosed. A circuit in accordance with the invention includes a programmable transceiver. The programmable transceiver is configured and/or controlled to support an interface standard. A system according to the present invention includes a programmable transceiver and a field-programmable gate array (FPGA) core coupled to program the programmable transceiver.
摘要翻译：公开了一种用于可编程输入/输出收发器的方法和系统。根据本发明的电路包括可编程收发器。可编程收发器被配置和/或控制以支持接口标准。根据本发明的系统包括可编程收发器和耦合以编程可编程收发器的现场可编程门阵列（FPGA）核。

3. 发明授权

US06826658B1 Method and apparatus for managing an optical transceiver 有权
标题翻译：用于管理光收发器的方法和装置
公开(公告)号：US06826658B1
公开(公告)日：2004-11-30
申请号：US10177441
申请日：2002-06-20
申请人： Justin L. Gaither , Amjad Odet-Allah
发明人： Justin L. Gaither , Amjad Odet-Allah
IPC分类号： G06F1318
CPC分类号： G06F13/1605 , H04B10/40
摘要： A method and apparatus for managing an optical transceiver includes processing that begins by transceiving management data with modules external to the optical transceiver. The processing then continues by converting the management data transceived with the external modules between a 1st data format (e.g., MDIO interface compatible) and a generic data format (e.g., a format convenient for reading data to and writing data from a random access memory). The processing continues by transceiving management data with modules internal to the optical transceiver. The processing continues by converting the management data transceived with the internal modules between the generic data format and a 2nd data format (e.g., I2C). The processing continues by arbitrating access to a shared memory, which stores the management data in the generic format, between requests from internal modules via the second controller and requests from external modules via the first controller.
摘要翻译：用于管理光收发器的方法和装置包括通过用光收发器外部的模块收发管理数据开始的处理。然后，通过将外部模块收发的管理数据转换为数据格式（例如，与MDIO接口兼容）和通用数据格式（例如，便于将数据从随机读取数据读取和写入数据的格式）访问内存）。通过用光收发器内部的模块收发管理数据，继续处理。通过将通用数据格式和第二个数据格式（例如，I 2 C）之间的内部模块收发的管理数据进行转换，继续处理。通过仲裁对通过第二控制器的来自内部模块的请求之间的通用格式的存储管理数据的共享存储器的访问以及经由第一控制器来自外部模块的请求进行处理。

4. 发明授权

US07830986B1 Method and apparatus for a phase/frequency locked loop 有权
标题翻译：相位/频率锁定环路的方法和装置
公开(公告)号：US07830986B1
公开(公告)日：2010-11-09
申请号：US11388349
申请日：2006-03-24
申请人： Justin L. Gaither
发明人： Justin L. Gaither
IPC分类号： H04L27/00
CPC分类号： H03L7/1077 , H03L7/085 , H03L7/091 , H03L7/093 , H03L7/1075 , Y10S388/911
摘要： A phase/frequency detector module allows operation as either a phase locked loop or a frequency locked loop. As a phased locked loop (PLL), the phase detector module is configured to decode phase differences between a reference signal and a voltage controlled oscillator (VCO) signal into phase correction signals that are updated at the rate of the VCO signal. An accumulation of the phase correction signals is implemented to form an accumulated phase error signal, which is then sampled at a lower rate than the VCO signal to accommodate slower components of the PLL, such as a digital to analog converter (DAC). As a frequency locked loop (FLL), the phase detector module is configured with frequency counters, so that frequency error may instead be detected. Any reduction of gain caused by the frequency counters is inherently equalized by the phase detector module.
摘要翻译：相位/频率检测器模块允许作为锁相环或锁频环路进行操作。作为相位锁定环（PLL），相位检测器模块被配置为将参考信号和压控振荡器（VCO）信号之间的相位差解码为以VCO信号的速率更新的相位校正信号。实施相位校正信号的累积以形成累积的相位误差信号，然后以比VCO信号更低的速率采样以适应PLL的较慢分量，例如数模转换器（DAC）。作为锁相环（FLL），相位检测器模块配置有频率计数器，因此可以改为检测频率误差。由频率计数器引起的增益的任何减少由相位检测器模块固有地均衡。

5. 发明授权

US07685340B1 Method and system for programmable input/output transceiver wherein transceiver in configurable to support a plurality of interface standards 有权
标题翻译：可编程输入/输出收发器的方法和系统，其中可配置为支持多个接口标准的收发器
公开(公告)号：US07685340B1
公开(公告)日：2010-03-23
申请号：US12145294
申请日：2008-06-24
申请人： Justin L. Gaither
发明人： Justin L. Gaither
IPC分类号： G06F3/00 , H04B1/38 , H04M9/00
CPC分类号： H04L25/0298 , H03L7/091 , H04B1/406 , H04L7/0079 , H04L25/0278
摘要： A method and system for a programmable input/output transceiver is disclosed. A circuit in accordance with the invention includes a programmable transceiver. The programmable transceiver is configured and/or controlled to support an interface standard. A system according to the present invention includes a programmable transceiver and a field-programmable gate array (FPGA) core coupled to program the programmable transceiver.
摘要翻译：公开了一种用于可编程输入/输出收发器的方法和系统。根据本发明的电路包括可编程收发器。可编程收发器被配置和/或控制以支持接口标准。根据本发明的系统包括可编程收发器和耦合以编程可编程收发器的现场可编程门阵列（FPGA）核。

6. 发明授权

US06653827B2 Analog signal test circuit and method 失效
公开(公告)号：US06653827B2
公开(公告)日：2003-11-25
申请号：US10261464
申请日：2002-09-30
申请人： Justin L. Gaither , Marwan M. Hassoun
发明人： Justin L. Gaither , Marwan M. Hassoun
IPC分类号： G01R3126
CPC分类号： G01R31/3167 , G01R31/2884
摘要： An integrated circuit includes analog test cells to determine if an analog signal is within a predetermined voltage or current range. The test cell uses one or more analog reference signals to establish boundaries of a test range. Different embodiments of the analog test cells selectively test multiple analog signals provided in an integrated circuit. A test system can be provided to test multiple analog signals of an integrated circuit by scanning multiple analog test cells distributed throughout the integrated circuit and providing the test data for analysis. An analog circuit of an integrated circuit can be tested at different stages in manufacturing, including during a wafer stage prior to separation of individual circuit dice. Further, analog circuitry can be tested and characterized without the need for analog or digital/analog testers. In contrast, a digital only tester can be used to test analog circuitry.

7. 发明授权

US07366803B1 Integrated circuit for buffering data by removing idle blocks to create a modified data stream when memory device is not near empty 有权
标题翻译：集成电路，用于通过消除空闲块来缓冲数据，以在存储器件不接近空时创建修改的数据流
公开(公告)号：US07366803B1
公开(公告)日：2008-04-29
申请号：US11063489
申请日：2005-02-23
申请人： Justin L. Gaither , Alexander Linn Iles
发明人： Justin L. Gaither , Alexander Linn Iles
IPC分类号： G06F13/00 , G06F3/00 , H04L12/28
CPC分类号： H04L12/433
摘要： A circuit for buffering data is disclosed. The circuit comprises a first circuit which is coupled to receive a stream of data blocks using a first clock signal. The first circuit removes data blocks, such as idle data blocks or a sequence ordered set of a pair of consecutive sequence ordered sets, from the stream of data blocks to create a first modified data stream which is coupled to a memory device. Finally, a second circuit coupled to the memory device generates a second modified data stream using a second clock signal. The second modified data stream preferably comprises the data blocks of the first modified data stream and idle data blocks inserted among the data blocks of the first modified data stream. Methods of buffering data received in a first clock domain and output in a second clock domain are also disclosed.
摘要翻译：公开了一种用于缓冲数据的电路。电路包括第一电路，其被耦合以使用第一时钟信号接收数据块流。第一电路从数据块流中去除数据块，例如空闲数据块或一对连续序列有序集合的序列有序集合，以创建耦合到存储器件的第一修改数据流。最后，耦合到存储器件的第二电路使用第二时钟信号产生第二修改的数据流。第二修改数据流优选地包括第一修改数据流的数据块和插入在第一修改数据流的数据块之间的空闲数据块。还公开了缓冲在第一时钟域中接收并在第二时钟域中输出的数据的方法。

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