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1. 发明授权

US08766354B2 Semiconductor devices including vertical channel transistors and methods of manufacturing the same 有权
标题翻译：包括垂直沟道晶体管的半导体器件及其制造方法
公开(公告)号：US08766354B2
公开(公告)日：2014-07-01
申请号：US13185961
申请日：2011-07-19
申请人： Hyun-woo Chung , Hyeong-sun Hong , Yong-chul Oh , Yoo-sang Hwang , Cheol-ho Baek , Kang-uk Kim
发明人： Hyun-woo Chung , Hyeong-sun Hong , Yong-chul Oh , Yoo-sang Hwang , Cheol-ho Baek , Kang-uk Kim
IPC分类号： H01L29/66
CPC分类号： H01L27/10876 , H01L27/10882 , H01L27/10885 , H01L27/10891 , H01L29/66666 , H01L29/7827
摘要： A semiconductor device including a plurality of buried word lines extending in a first direction and a plurality of buried bit lines extending in a second direction. Upper surfaces of the plurality of buried word lines and the plurality of buried bit lines are lower than an upper surface of a substrate. The distance between two active regions that constitute a pair of first active regions from among a plurality of first active regions included in a first group of active regions is less than the distance between two adjacent active regions having the plurality of buried bit lines therebetween. A method of manufacturing a semiconductor device includes forming a plurality of first trenches in a substrate, forming a plurality of first conductive patterns in the plurality of first trenches in such a manner that a pair of first conductive patterns is disposed in each of the plurality of first trenches, forming a plurality of first buried patterns in the plurality of first trenches to cover the plurality of first conductive patterns, forming a plurality of second trenches by etching the substrate between the plurality of first trenches, and forming a plurality of second buried patterns in the plurality of second trenches.
摘要翻译：一种半导体器件，包括沿第一方向延伸的多个掩埋字线和沿第二方向延伸的多个掩埋位线。多个掩埋字线和多个掩埋位线的上表面比衬底的上表面低。构成第一组有源区域中的多个第一有源区域中的构成一对第一有源区域的两个有源区域之间的距离小于其间具有多个掩埋位线的两个相邻有源区域之间的距离。一种制造半导体器件的方法包括在衬底中形成多个第一沟槽，在多个第一沟槽中形成多个第一导电图案，使得一对第一导电图案设置在多个第一沟槽中的每一个中第一沟槽，在所述多个第一沟槽中形成多个第一掩埋图案以覆盖所述多个第一导电图案，通过在所述多个第一沟槽之间蚀刻所述衬底形成多个第二沟槽，以及形成多个第二掩埋图案在多个第二沟槽中。

2. 发明授权

US08294131B2 Integrated circuit devices including low-resistivity conductive patterns in recessed regions 有权
标题翻译：集成电路器件包括凹陷区域中的低电阻率导电图案
公开(公告)号：US08294131B2
公开(公告)日：2012-10-23
申请号：US12826896
申请日：2010-06-30
申请人： Kang-Uk Kim , Yongchul Oh , Hui-Jung Kim , Hyun-Woo Chung , Hyun-Gi Kim
发明人： Kang-Uk Kim , Yongchul Oh , Hui-Jung Kim , Hyun-Woo Chung , Hyun-Gi Kim
IPC分类号： H01L29/02
CPC分类号： H01L27/228 , H01L27/0207 , H01L27/10876 , H01L27/10885 , H01L27/2454 , H01L27/2463
摘要： An integrated circuit device includes a device isolation pattern on a semiconductor substrate to define an active area therein. The active area includes a doped region therein. A conductive pattern extends on the active area and electrically contacts the doped region. The conductive pattern has a lower resistivity than the doped region. The conductive pattern may be disposed in a recessed region having a bottom surface lower than a top surface of the active area. A channel pillar electrically contacts to the doped region and extends therefrom in a direction away from the substrate. A conductive gate electrode is disposed on a sidewall of the channel pillar, and a gate dielectric layer is disposed between the gate electrode and the sidewall of the channel pillar.
摘要翻译：集成电路器件包括在半导体衬底上的器件隔离图案，以在其中限定有效区域。有源区域包括其中的掺杂区域。导电图案在有源区上延伸并与掺杂区电接触。导电图案具有比掺杂区域更低的电阻率。导电图案可以设置在具有低于有源区域的顶表面的底表面的凹陷区域中。通道柱与掺杂区电接触并从远离衬底的方向从其延伸。导电栅电极设置在通道柱的侧壁上，并且栅极电介质层设置在沟道柱的栅电极和侧壁之间。

3. 发明申请

US20090242975A1 Vertical pillar transistor 有权
标题翻译：立柱晶体管
公开(公告)号：US20090242975A1
公开(公告)日：2009-10-01
申请号：US12382898
申请日：2009-03-26
申请人： Hui-Jung Kim , Yong-Chul Oh , Jae-Man Yoon , Hyun-Woo Chung , Hyun-Gi Kim , Kang-Uk Kim
发明人： Hui-Jung Kim , Yong-Chul Oh , Jae-Man Yoon , Hyun-Woo Chung , Hyun-Gi Kim , Kang-Uk Kim
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L27/10882 , H01L21/76232 , H01L21/823481 , H01L21/823487 , H01L27/10876 , H01L29/66666 , H01L29/7827
摘要： A vertical pillar transistor may include a plurality of lower pillars, a plurality of upper pillars, a first insulation part, a second insulation part and a word line. The plurality of lower pillars protrudes substantially perpendicular to a substrate and is defined by a plurality of trenches. The plurality of lower pillars extends along a second direction and may be separated from each other along a first direction substantially perpendicular to the second direction. The plurality of upper pillars may be formed on the plurality of lower pillars. The plurality of upper pillars has a width substantially smaller than that of the plurality of lower pillars. The first insulation part has a substantially uniform thickness on a sidewall of each of the plurality of lower pillars. The second insulation part may be formed on the first insulation part to fill a gap between the adjacent upper pillars. The word line may be formed on the second insulation part and may extend between facing sidewalls of the adjacent pair of upper pillars along the first direction.
摘要翻译：垂直柱状晶体管可以包括多个下部支柱，多个上部支柱，第一绝缘部分，第二绝缘部分和字线。多个下支柱基本上垂直于基板突出并且由多个沟槽限定。多个下柱沿着第二方向延伸并且可以沿着基本上垂直于第二方向的第一方向彼此分离。多个上柱可以形成在多个下支柱上。多个上支柱具有比多个下支柱的宽度更小的宽度。第一绝缘部件在多个下支柱中的每一个的侧壁上具有基本均匀的厚度。第二绝缘部件可以形成在第一绝缘部分上以填充相邻的上部支柱之间的间隙。字线可以形成在第二绝缘部分上，并且可以沿着第一方向在相邻的一对上柱的相对侧壁之间延伸。

4. 发明授权

US08304824B2 Semiconductor device comprising buried word lines 有权
标题翻译：包括掩埋字线的半导体器件
公开(公告)号：US08304824B2
公开(公告)日：2012-11-06
申请号：US12719493
申请日：2010-03-08
申请人： Hui-Jung Kim , Yong-Chul Oh , Hyun-Woo Chung , Hyun-Gi Kim , Kang-Uk Kim
发明人： Hui-Jung Kim , Yong-Chul Oh , Hyun-Woo Chung , Hyun-Gi Kim , Kang-Uk Kim
IPC分类号： H01L27/108 , H01L29/94
CPC分类号： H01L27/10891 , H01L27/0207 , H01L27/10817 , H01L27/10885 , H01L29/4236
摘要： A semiconductor device includes: an isolation layer for defining a plurality of active areas of a substrate, where the isolation layer is disposed on the substrate; a plurality of buried word lines having upper surfaces that are lower than the upper surfaces of the active areas, being surrounded by the active areas, and extending in a first direction parallel to a main surface of the substrate; a gate dielectric film interposed between the buried word lines and the active areas; and a plurality of buried bit lines having upper surfaces that are lower than the upper surfaces of the plurality of buried word lines and extending parallel to the main surface of the substrate in a second direction that differs from the first direction.
摘要翻译：半导体器件包括：用于限定衬底的多个有源区的隔离层，其中隔离层设置在衬底上; 具有比有源区域的上表面低的上表面的多个掩埋字线被有源区域包围，并且沿与基板的主表面平行的第一方向延伸; 介于掩埋字线和有源区之间的栅介质膜; 以及多个掩埋位线，其具有比所述多个掩埋字线的上表面低的上表面，并且在与所述第一方向不同的第二方向上平行于所述基板的主表面延伸。

5. 发明授权

US08105904B2 Method of manufacturing semiconductor devices 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08105904B2
公开(公告)日：2012-01-31
申请号：US12704233
申请日：2010-02-11
申请人： Yong-Chul Oh , Kang-Uk Kim
发明人： Yong-Chul Oh , Kang-Uk Kim
IPC分类号： H01L21/336
CPC分类号： H01L21/84 , H01L27/10876 , H01L27/10885 , H01L27/10894
摘要： A semiconductor device includes an insulation layer disposed on a substrate having a first area and a second area, a first wiring disposed on the insulation layer in the first area, a first active structure disposed on the first wiring, a first gate insulation layer enclosing the first upper portion, a first gate electrode disposed on the first gate insulation layer, a first impurity region disposed at the first lower portion, and a second impurity region disposed at the first upper portion. The first wiring may extend in a first direction. The first active structure includes a first lower portion extending in the first direction and a first upper portion protruding from the first lower portion. The first gate electrode may extend in a second direction. The first impurity region may be electrically connected to the first wiring.
摘要翻译：半导体器件包括设置在具有第一区域和第二区域的衬底上的绝缘层，设置在第一区域中的绝缘层上的第一布线，设置在第一布线上的第一有源结构，第一栅极绝缘层，第一上部，设置在第一栅极绝缘层上的第一栅极电极，设置在第一下部的第一杂质区域和设置在第一上部的第二杂质区域。第一布线可以沿第一方向延伸。第一主动结构包括沿第一方向延伸的第一下部部分和从第一下部部分突出的第一上部部分。第一栅电极可以在第二方向上延伸。第一杂质区域可以电连接到第一布线。

6. 发明授权

US08053316B2 Method of fabricating vertical channel transistor 有权
标题翻译：制造垂直沟道晶体管的方法
公开(公告)号：US08053316B2
公开(公告)日：2011-11-08
申请号：US12953785
申请日：2010-11-24
申请人： Kang-Uk Kim , Yongchul Oh , Hui-Jung Kim , Hyun-Woo Chung , Hyun-Gi Kim
发明人： Kang-Uk Kim , Yongchul Oh , Hui-Jung Kim , Hyun-Woo Chung , Hyun-Gi Kim
IPC分类号： H01L21/336
CPC分类号： H01L27/10876 , H01L27/10823 , H01L27/10885 , H01L29/66666 , H01L29/7827
摘要： A method of fabricating a vertical channel transistor includes: forming a line type active pattern on a substrate so as to extend in a first horizontal direction; forming a vertical channel isolating the active pattern in a second horizontal direction intersecting the first horizontal direction and extending vertically on the substrate; forming a buried bit line extending in the first horizontal direction on the substrate; and forming a word line extending in the second horizontal direction along at least one side surface of the vertical channel.
摘要翻译：制造垂直沟道晶体管的方法包括：在衬底上形成线状有源图案，以沿第一水平方向延伸; 形成在与所述第一水平方向相交并在所述基板上垂直延伸的第二水平方向隔离所述有源图案的垂直通道; 形成在所述基板上沿所述第一水平方向延伸的掩埋位线; 以及沿所述垂直通道的至少一个侧表面在所述第二水平方向上形成字线。

7. 发明申请

US20110111568A1 METHODS OF FABRICATING VERTICAL CHANNEL TRANSISTORS 有权
标题翻译：制造垂直通道晶体管的方法
公开(公告)号：US20110111568A1
公开(公告)日：2011-05-12
申请号：US12906630
申请日：2010-10-18
申请人： Kang-Uk Kim , Hyun-Woo Chung , Youngchul Oh , Hui-Jung Kim , Hyun-Gi Kim
发明人： Kang-Uk Kim , Hyun-Woo Chung , Youngchul Oh , Hui-Jung Kim , Hyun-Gi Kim
IPC分类号： H01L21/336
CPC分类号： H01L29/7827 , H01L21/2815 , H01L27/0207 , H01L27/10876 , H01L27/10885 , H01L29/0657 , H01L29/41741 , H01L29/42376 , H01L29/4238 , H01L29/66666
摘要： Methods of fabricating vertical channel transistors may include forming an active region on a substrate, patterning the active region to form vertical channels at sides of the active region, forming a buried bit line in the active region between the vertical channels, and forming a word line facing a side of the vertical channel.
摘要翻译：制造垂直沟道晶体管的方法可以包括在衬底上形成有源区域，图案化有源区域以在有源区域的侧面形成垂直沟道，在垂直沟道之间的有源区域中形成掩埋位线，并形成字线面向垂直通道的一侧。

8. 发明申请

US20090250736A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20090250736A1
公开(公告)日：2009-10-08
申请号：US12385433
申请日：2009-04-08
申请人： Jae-Man Yoon , Yong-Chul Oh , Hui-Jung Kim , Hyun-Woo Chung , Hyun-Gi Kim , Kang-Uk Kim
发明人： Jae-Man Yoon , Yong-Chul Oh , Hui-Jung Kim , Hyun-Woo Chung , Hyun-Gi Kim , Kang-Uk Kim
IPC分类号： H01L29/94 , H01L29/78
CPC分类号： H01L27/0688 , H01L21/8221
摘要： In a semiconductor device and associated methods, the semiconductor device includes a substrate, an insulation layer on the substrate, a conductive structure on the insulation layer, the conductive structure including at least one metal silicide film pattern, a semiconductor pattern on the conductive structure, the semiconductor pattern protruding upwardly from the conductive structure, a gate electrode at least partially enclosing the semiconductor pattern, the gate electrode being spaced apart from the conductive structure, a first impurity region at a lower portion of the semiconductor pattern, and a second impurity region at an upper portion of the semiconductor pattern.
摘要翻译：在半导体器件和相关方法中，半导体器件包括衬底，衬底上的绝缘层，绝缘层上的导电结构，导电结构包括至少一种金属硅化物膜图案，导电结构上的半导体图案，所述半导体图案从所述导电结构向上突出，栅电极至少部分地封装所述半导体图案，所述栅电极与所述导电结构间隔开，所述半导体图案的下部的第一杂质区域和所述第二杂质区域在半导体图案的上部。

9. 发明授权

US09337199B2 Semiconductor device and method of fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US09337199B2
公开(公告)日：2016-05-10
申请号：US14089356
申请日：2013-11-25
申请人： Jiyoung Kim , Sungho Jang , Kang-Uk Kim , Kyung-Eun Kim , Daeik Kim , Hyoungsub Kim , Nakjin Son , Dong Jin Lee , Yoosang Hwang , Jihye Hwang
发明人： Jiyoung Kim , Sungho Jang , Kang-Uk Kim , Kyung-Eun Kim , Daeik Kim , Hyoungsub Kim , Nakjin Son , Dong Jin Lee , Yoosang Hwang , Jihye Hwang
IPC分类号： H01L27/108 , H01L27/088
CPC分类号： H01L27/10826 , H01L27/0886 , H01L27/10894
摘要： A semiconductor device may include a substrate having a first region and a second region on a surface thereof, and a first semiconductor fin on the first region of the substrate with the first semiconductor fin including a first trench therethrough. A first gate electrode may be provided in the first trench, and first and second source/drain regions may be provided in the first semiconductor fin, with the first gate electrode between the first and second source/drain regions. A second semiconductor fin may be provided on the second region of the substrate with the second semiconductor fin including a second trench therethrough, a second gate electrode may be provided in the second trench, and third and fourth source/drain regions may be provided in the second semiconductor fin with the second gate electrode being between the third and fourth source/drain regions.
摘要翻译：半导体器件可以包括其表面上具有第一区域和第二区域的衬底，以及在衬底的第一区域上的第一半导体鳍片，其中第一半导体鳍片包括穿过其的第一沟槽。第一栅电极可以设置在第一沟槽中，第一和第二源极/漏极区可以设置在第一半导体鳍片中，第一栅极电极在第一和第二源极/漏极区域之间。可以在衬底的第二区域上设置第二半导体鳍片，其中第二半导体鳍片包括穿过其中的第二沟槽，第二栅电极可以设置在第二沟槽中，第三和第四源极/漏极区域可以设置在第二半导体鳍片，第二栅极电极位于第三和第四源极/漏极区域之间。

10. 发明授权

US08247856B2 Semiconductor device including a capacitor electrically connected to a vertical pillar transistor 有权
标题翻译：半导体器件包括电连接到垂直柱晶体管的电容器
公开(公告)号：US08247856B2
公开(公告)日：2012-08-21
申请号：US12728596
申请日：2010-03-22
申请人： Hui-Jung Kim , Yong-Chul Oh , Jae-Man Yoon , Hyun-Woo Chung , Hyun-Gi Kim , Kang-Uk Kim
发明人： Hui-Jung Kim , Yong-Chul Oh , Jae-Man Yoon , Hyun-Woo Chung , Hyun-Gi Kim , Kang-Uk Kim
IPC分类号： H01L27/06
CPC分类号： H01L27/10817 , H01L27/10852 , H01L27/10876 , H01L27/10894 , H01L28/91 , H01L29/78
摘要： A semiconductor device includes a first transistor, a second transistor, an insulation interlayer pattern and a capacitor. The first transistor is formed in a first region of a substrate. The first transistor has a pillar protruding upwardly from the substrate and an impurity region provided in an upper portion of the pillar. The second transistor is formed in a second region of the substrate. The insulation interlayer pattern is formed on the first region and the second region to cover the second transistor and expose an upper surface of the pillar. The insulation interlayer pattern has an upper surface substantially higher than the upper surface of the pillar in the first region. The capacitor is formed on the impurity region in the upper portion of the pillar and is electrically connected to the impurity region.
摘要翻译：半导体器件包括第一晶体管，第二晶体管，绝缘层间图案和电容器。第一晶体管形成在衬底的第一区域中。第一晶体管具有从基板向上突出的柱和设置在柱的上部的杂质区。第二晶体管形成在衬底的第二区域中。绝缘层间图案形成在第一区域和第二区域上以覆盖第二晶体管并暴露柱的上表面。绝缘层间图案具有比第一区域中的柱的上表面大得多的上表面。电容器形成在柱的上部的杂质区上并与杂质区电连接。

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