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1. 发明授权

US07536514B2 Early return indication for read exclusive requests in shared memory architecture 有权
标题翻译：在共享内存架构中读取独占请求的早期返回指示
公开(公告)号：US07536514B2
公开(公告)日：2009-05-19
申请号：US11225655
申请日：2005-09-13
申请人： Wayne Melvin Barrett , Kenneth Michael Valk , Brian T. Vanderpool
发明人： Wayne Melvin Barrett , Kenneth Michael Valk , Brian T. Vanderpool
IPC分类号： G06F12/06
CPC分类号： G06F13/1663 , G06F12/0817
摘要： An early return indication is used to notify a first communications interface, prior to a response being received from any of a plurality of sources coupled to a second communications interface, that the return data can be used by the first communications interface when it is received thereby from a source of the return data if the source has an exclusive copy of the return data. By doing so, the first communications interface can often prepare for forwarding the return data over its associated communication link such that the data can be forwarded with little or no latency once the data is retrieved from its source, and may be able to initiate the return of data over the communication link prior to all responses being received from the other sources. The early return indication may also serves as an early coherency indication in that the first communications interface is no longer required to wait for updating of a coherency directory to complete prior to forwarding the return data over the communication link.
摘要翻译：早期返回指示用于在从与第二通信接口耦合的多个源中的任一个接收到响应之前通知第一通信接口，使得第一通信接口在接收时可以由第一通信接口使用返回数据来自返回数据的源，如果源具有返回数据的排他副本。通过这样做，第一通信接口通常可以准备通过其相关联的通信链路转发返回数据，使得一旦数据从源中检索出来，数据可以很少或没有等待时间转发，并且可能能够启动返回在从其他来源接收到所有响应之前通过通信链路的数据。早期返回指示还可以用作早期一致性指示，因为在通过通信链路转发返回数据之前，第一通信接口不再需要等待更新相干性目录来完成。

2. 发明授权

US06754753B2 Atomic ownership change operation for input/output (I/O) bridge device in clustered computer system 失效
标题翻译：集群计算机系统中输入/输出（I / O）桥接器件的原子所有权更改操作
公开(公告)号：US06754753B2
公开(公告)日：2004-06-22
申请号：US09844584
申请日：2001-04-27
申请人： Bruce Leroy Beukema , Richard Charles Booth , David Robert Engebretsen , Thomas Rembert Sand , Kenneth Michael Valk
发明人： Bruce Leroy Beukema , Richard Charles Booth , David Robert Engebretsen , Thomas Rembert Sand , Kenneth Michael Valk
IPC分类号： G06F1516
CPC分类号： G06F9/52
摘要： A clustered computer system, bridge device and method include support for an atomic ownership change operation that ensures orderly and reliable ownership management of an input/output (I/O) bridge device. A lock indicator is associated with a bridge device, and is used to indicate a “locked” or “unlocked” status of the bridge device. Whenever the lock indicator indicates that the bridge device is unlocked, an atomic operation such as a read request to a lock indicator register is utilized to both set the indicator to indicate a locked status for the bridge device, and to associate the bridge device with a source node that initiated the atomic operation. In connection with the lock indicator, write access to one or more configuration parameter registers is controlled such that only the node that is associated with the bridge device is permitted to update such configuration parameter registers.
摘要翻译：集群计算机系统，桥接器件和方法包括支持原子所有权更改操作，确保输入/输出（I / O）桥接器件的有序可靠的所有权管理。锁定指示器与桥接设备相关联，并用于指示桥接设备的“锁定”或“解锁”状态。每当锁定指示器指示桥接设备被解锁时，利用诸如对锁定指示器寄存器的读取请求的原子操作来将指示器设置为指示桥接设备的锁定状态，并且将桥接设备与源节点启动原子操作。与锁定指示器相关联，控制对一个或多个配置参数寄存器的写入访问，使得仅允许与桥接设备相关联的节点更新这样的配置参数寄存器。

3. 发明授权

US06643818B1 Storing and using the history of data transmission errors to assure data integrity 有权
标题翻译：存储和使用数据传输错误的历史以确保数据完整性
公开(公告)号：US06643818B1
公开(公告)日：2003-11-04
申请号：US09443521
申请日：1999-11-19
申请人： Kenneth Michael Valk
发明人： Kenneth Michael Valk
IPC分类号： H04L100
CPC分类号： H04L1/0063
摘要： A method and apparatus is disclosed which enhances the integrity of transmitted data or detects when random data is being received which might indicate that a receiver or a transmitter is open or that random data is otherwise being transmitted. A stream of data transmitted in packets having an error code associated with each packet is received into a receiver. The receiver has an error code checker to check the error code of each packet to determine if the data packet has been transmitted error-free. The results of the error checks for n sequential packets are stored in a shift register or counter. An incoming packet then undergoes an error code check and the results of the previous n sequential packets are considered. If a predetermined number of the previous n sequential packets has a transmission error n, then the method decides to reject or accept the error packet based on the quality of data integrity. When a 32-bit CRC error code is used, an 8-bit shift register is sufficient to prevent the acceptance of a packet of random data that may otherwise be accepted.
摘要翻译：公开了一种增强传输数据的完整性或检测何时正在接收可能指示接收机或发射机打开或者随机数据被另外传输的随机数据的方法和装置。在具有与每个分组相关联的错误代码的分组中传输的数据流被接收到接收机中。接收机有一个错误代码检查器，用于检查每个数据包的错误代码，以确定数据包是否已经无误传输。 n个顺序包的错误检查结果存储在移位寄存器或计数器中。然后，传入的数据包经历错误代码检查，并考虑先前的n个顺序数据包的结果。如果预定数量的先前n个顺序分组具有传输错误n，则该方法基于数据完整性的质量决定拒绝或接受错误分组。当使用32位CRC错误代码时，8位移位寄存器足以防止接受可能被接受的随机数据包。

4. 发明授权

US08275922B2 Implementing serial link training patterns separated by random data for training a serial link in an interconnect system 有权
标题翻译：实现由随机数据分离的串行链路训练模式，用于训练互连系统中的串行链路
公开(公告)号：US08275922B2
公开(公告)日：2012-09-25
申请号：US12709733
申请日：2010-02-22
申请人： Wayne Melvin Barrett , Kenneth Michael Valk
发明人： Wayne Melvin Barrett , Kenneth Michael Valk
IPC分类号： G06F13/42
CPC分类号： H04L5/1438
摘要： A method and circuit for implementing serial link training sequences, and a design structure on which the subject circuit resides are provided. A transmitter device transmits a training sequence (TS) pattern; then the transmitter device transmits random data for a predefined time duration. The steps of transmitting the TS-pattern, then transmitting the random data for the fixed time duration are repeated. A receiver device detecting a plurality of the TS-patterns separated by the predefined time interval of random data, performs receiver initialization steps. The receiver device performs a plurality of receiver initialization steps including, for example, acquiring byte lock, and a link width determination.
摘要翻译：一种用于实现串行链路训练序列的方法和电路，以及设置该对象电路所在的设计结构。发射机设备发送训练序列（TS）模式; 则发射机设备在预定义的持续时间内发送随机数据。重复发送TS模式，然后发送固定持续时间的随机数据的步骤。检测分离了随机数据的预定时间间隔的多个TS模式的接收机设备执行接收机初始化步骤。接收机装置执行多个接收机初始化步骤，包括例如获取字节锁定和链路宽度确定。

5. 发明申请

US20110243154A1 USING VARIABLE LENGTH PACKETS TO EMBED EXTRA NETWORK CONTROL INFORMATION 失效
标题翻译：使用可变长度包装嵌入额外的网络控制信息
公开(公告)号：US20110243154A1
公开(公告)日：2011-10-06
申请号：US12749812
申请日：2010-03-30
申请人： William Thomas Flynn , David Alan Shedivy , Kenneth Michael Valk
发明人： William Thomas Flynn , David Alan Shedivy , Kenneth Michael Valk
IPC分类号： H04J3/22 , H03M13/00
CPC分类号： H04L1/0079 , H03M13/09 , H04L1/0072
摘要： A method and circuit for implementing variable length packets to embed extra control information in an interconnect system, and a design structure on which the subject circuit resides are provided. Packets are defined to include an End-to-End (ETE) Flow Unit within packet (Flit) count field in the packet header. The packet header also includes its own CRC field. When a nonzero ETE flit count field is received in an incoming packet from an incoming link, the specified number of embedded ETE flits is removed from the packet and is used the same as if the control information arrived in its own packet.
摘要翻译：一种用于实现可变长度分组以在互连系统中嵌入额外控制信息的方法和电路，以及提供了主题电路所在的设计结构。分组被定义为在分组报头中的分组（Flit）计数字段内包括端到端（ETE）流单元。分组报头还包括其自己的CRC字段。当在来自传入链路的传入分组中接收到非零的ETE飞行计数字段时，从分组中删除指定数量的嵌入式ETE飞行，并且与控制信息到达自己的分组一样被使用。

6. 发明授权

US08358658B2 Implementing ordered and reliable transfer of packets while spraying packets over multiple links 失效
标题翻译：在多个链路上分发数据包时，实现有序可靠的数据包传输
公开(公告)号：US08358658B2
公开(公告)日：2013-01-22
申请号：US12727545
申请日：2010-03-19
申请人： William Thomas Flynn , Phillip Rogers Hillier, III , David Alan Shedivy , Kenneth Michael Valk
发明人： William Thomas Flynn , Phillip Rogers Hillier, III , David Alan Shedivy , Kenneth Michael Valk
IPC分类号： H04L12/28
CPC分类号： G06F13/4022 , G06F2213/0026
摘要： A method and circuit for implementing ordered and reliable transfer of packets while spraying packets over multiple links, and a design structure on which the subject circuit resides are provided. Each source interconnect chip maintains a spray mask including multiple available links for each destination chip for spraying packets across multiple links of a local rack interconnect system. Each packet is assigned an End-to-End (ETE) sequence number in the source interconnect chip that represents the packet position in an ordered packet stream from the source device. The destination interconnect chip uses the ETE sequence numbers to reorder the received sprayed packets into the correct order before sending the packets to the destination device.
摘要翻译：一种用于在通过多个链路喷射分组时实现分组的有序和可靠传送的方法和电路，并且提供了主题电路所在的设计结构。每个源互连芯片保持喷射掩模，其包括用于每个目的地芯片的多个可用链路，用于在本地机架互连系统的多个链路上喷射分组。每个数据包被分配在源互连芯片中的端到端（ETE）序列号，其表示来自源设备的有序分组流中的分组位置。目的互连芯片在将数据包发送到目标设备之前，使用ETE序列号将接收到的喷射数据包重新排序为正确的顺序。

7. 发明申请

US20090019228A1 Data Cache Invalidate with Data Dependent Expiration Using a Step Value 有权
标题翻译：数据缓存使用步进值与数据相关到期失效
公开(公告)号：US20090019228A1
公开(公告)日：2009-01-15
申请号：US11776731
申请日：2007-07-12
申请人： Jeffrey Douglas Brown , Russell Dean Hoover , Eric Oliver Mejdrich , Kenneth Michael Valk
发明人： Jeffrey Douglas Brown , Russell Dean Hoover , Eric Oliver Mejdrich , Kenneth Michael Valk
IPC分类号： G06F12/12
CPC分类号： G06F12/0895 , Y02D10/13
摘要： According to embodiments of the invention, a step value and a step-interval cache coherency protocol may be used to update and invalidate data stored within cache memory. A step value may be an integer value and may be stored within a cache directory entry associated with data in the memory cache. Upon reception of a cache read request, along with the normal address comparison to determine if the data is located within the cache a current step value may be compared with the stored step value to determine if the data is current. If the step values match, the data may be current and a cache hit may occur. However, if the step values do not match, the requested data may be provided from another source. Furthermore, an application may update the current step value to invalidate old data stored within the cache and associated with a different step value.
摘要翻译：根据本发明的实施例，可以使用步长值和步进间隔高速缓存一致性协议来更新和使存储在高速缓冲存储器中的数据无效。步数值可以是整数值，并且可以存储在与存储器高速缓存中的数据相关联的高速缓存目录条目中。在接收到缓存读取请求时，连同正常地址比较以确定数据是否位于高速缓存内，可以将当前步长值与存储的步长值进行比较，以确定数据是否为当前值。如果步数值匹配，数据可能是当前的，并且可能会发生高速缓存命中。然而，如果步骤值不匹配，则可以从另一个源提供所请求的数据。此外，应用程序可以更新当前步骤值以使存储在高速缓存中并与不同步长值相关联的旧数据无效。

8. 发明授权

US06275876B1 Specifying wrap register for storing memory address to store completion status of instruction to external device 失效
标题翻译：指定用于存储存储器地址的包装寄存器，以将指令的完成状态存储到外部设备
公开(公告)号：US06275876B1
公开(公告)日：2001-08-14
申请号：US09316243
申请日：1999-05-21
申请人： Kenneth Michael Valk , Thomas Rembert Sand , Ronald Edward Fuhs , Gregory Michael Nordstrom , Bruce Leroy Beukema
发明人： Kenneth Michael Valk , Thomas Rembert Sand , Ronald Edward Fuhs , Gregory Michael Nordstrom , Bruce Leroy Beukema
IPC分类号： G06F1312
CPC分类号： G06F13/126
摘要： A computing system includes a processing system, at least a first register, and a control system. The processing system generates a first instruction set and a first address for storing a first completion status for the first instruction set. The first register receives the first address from the processing system. The control system communicates the first instruction set received from the processing system to an external device. The control system receives the first completion status from the external device, accesses the first register to determine the first address for the first instruction set, and stores the first completion status in the determined first address.
摘要翻译：计算系统包括处理系统，至少第一寄存器和控制系统。处理系统产生第一指令集和第一地址，用于存储第一指令集的第一完成状态。第一个寄存器从处理系统接收第一个地址。控制系统将从处理系统接收的第一指令集传送到外部设备。控制系统从外部设备接收第一完成状态，访问第一寄存器以确定第一指令集的第一地址，并将第一完成状态存储在所确定的第一地址中。

9. 发明授权

US5787094A Test and diagnostics for a self-timed parallel interface 失效
标题翻译：自定时并行接口的测试和诊断
公开(公告)号：US5787094A
公开(公告)日：1998-07-28
申请号：US656950
申请日：1996-06-06
申请人： Delbert Raymond Cecchi , Marius V. Dina , Curtis Walter Preuss , Kenneth Michael Valk
发明人： Delbert Raymond Cecchi , Marius V. Dina , Curtis Walter Preuss , Kenneth Michael Valk
IPC分类号： G06F11/263 , G06F11/267 , G06F11/10 , H03M13/00
CPC分类号： G06F11/221 , G01R31/318385 , G06F11/263
摘要： A method and apparatus that can test self-timed parallel interfaces operating at system speed. An output stage is provided for queuing a test packet and providing the test packet to an input stage. The packet contains a data bit stream and error detection code such as cyclic redundancy check code. The input stage is coupled to the output stage and receives the test packet to determine the correctness of the data bit stream. On the input stage, the error detection code verifier recalculates the error detection code and compares the recalculated error detection code with the error detection code attached to the data bit stream to determine the correctness of the data bit steam. The output queue has a first input port for receiving data from drivers on the interface and a second input port for receiving a pseudo random data bit stream. A pseudo random data generator generates a pseudo random data bit stream. The data bit stream may be packetized according to a predetermined protocol. An off-chip signal of the output stage may be provided to the inputs of the input stage to produce an on-chip copy of off-chip data.
摘要翻译：可以测试以系统速度运行的自定时并行接口的方法和装置。提供输出级用于排队测试分组并将测试分组提供给输入级。分组包含数据比特流和诸如循环冗余校验码的错误检测码。输入级耦合到输出级并接收测试数据包以确定数据位流的正确性。在输入级上，错误检测码验证器重新计算错误检测码，并将重新计算的错误检测码与附加到数据比特流的错误检测码进行比较，以确定数据比特流的正确性。输出队列具有用于从接口上的驱动器接收数据的第一输入端口和用于接收伪随机数据位流的第二输入端口。伪随机数据生成器生成伪随机数据比特流。可以根据预定协议对数据比特流进行分组化。可以将输出级的片外信号提供给输入级的输入，以产生片外数据的片上拷贝。

10. 发明授权

US08340112B2 Implementing enhanced link bandwidth in a headless interconnect chip 失效
标题翻译：在无头互连芯片中实现增强的链路带宽
公开(公告)号：US08340112B2
公开(公告)日：2012-12-25
申请号：US12731715
申请日：2010-03-25
申请人： Phillip Rogers Hillier, III , David Alan Shedivy , Kenneth Michael Valk
发明人： Phillip Rogers Hillier, III , David Alan Shedivy , Kenneth Michael Valk
IPC分类号： H04L12/54
CPC分类号： G06F13/4022 , H04L49/1523 , H04L49/251 , H04L49/252
摘要： A method and circuit for implementing enhanced link bandwidth for a headless interconnect chip in a local rack interconnect system, and a design structure on which the subject circuit resides are provided. The headless interconnect chip includes a cut through switch and a store and forward switch. A packet is received from an incoming link to be transmitted on an outgoing link on the headless interconnect chip. Both the cut through switch and the store and forward switch are selectively used for moving packets received from the incoming link to the outgoing link on the headless interconnect chip.
摘要翻译：一种用于实现本地机架互连系统中的无头互连芯片的增强的链路带宽的方法和电路，以及提供了所述主题电路所在的设计结构。无头互连芯片包括切断开关和存储和正向开关。从在无头互连芯片上的输出链路上传送的传入链路接收分组。切断开关和存储和正向开关都有选择地用于将从进入链路接收的分组移动到无头互连芯片上的输出链路。

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