专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08593459B2 Tree insertion depth adjustment based on view frustum and distance culling 有权
标题翻译：基于视锥截面和距离剔除的树插入深度调整
公开(公告)号：US08593459B2
公开(公告)日：2013-11-26
申请号：US13476876
申请日：2012-05-21
申请人： Eric Oliver Mejdrich , Paul Emery Schardt , Robert Allen Shearer , Matthew Ray Tubbs
发明人： Eric Oliver Mejdrich , Paul Emery Schardt , Robert Allen Shearer , Matthew Ray Tubbs
IPC分类号： G06T15/50 , G06T15/00 , G06T15/40 , G06T15/10 , G06T15/20 , G06T15/06
CPC分类号： G06T15/06 , G06T17/005
摘要： A computer-implemented method includes initializing a driver associated with an input/output adapter in response to receiving an initialize driver request from a client application. The computer-implemented method includes initializing the input/output adapter to enable adapter capabilities of the input/output adapter to be determined. The computer-implemented method also includes determining the adapter capabilities of the input/output adapter. The computer-implemented method further includes determining slot capabilities of a slot associated with the input/output adapter. The computer-implemented method also includes setting configurable capabilities of the input/output adapter based on the adapter capabilities and the slot capabilities.
摘要翻译：计算机实现的方法包括初始化与输入/输出适配器相关联的驱动程序以响应于从客户端应用程序接收到初始化驱动程序请求。计算机实现的方法包括初始化输入/输出适配器以确定输入/输出适配器的适配器能力。计算机实现的方法还包括确定输入/输出适配器的适配器能力。计算机实现的方法还包括确定与输入/输出适配器相关联的时隙的时隙能力。计算机实现的方法还包括基于适配器能力和时隙能力来设置输入/输出适配器的可配置功能。

2. 发明授权

US08259130B2 Color buffer contrast threshold for adaptive anti-aliasing 有权
标题翻译：用于自适应抗锯齿的彩色缓冲区对比度阈值
公开(公告)号：US08259130B2
公开(公告)日：2012-09-04
申请号：US11693221
申请日：2007-03-29
申请人： Jeffrey Douglas Brown , Russell Dean Hoover , Eric Oliver Mejdrich
发明人： Jeffrey Douglas Brown , Russell Dean Hoover , Eric Oliver Mejdrich
IPC分类号： G09G5/00
CPC分类号： G06T15/06
摘要： According to one embodiment of the invention, by increasing the number of rays issued through adjacent pixels with colors of high contrast while maintaining the number of rays issued through adjacent pixels which do not have colors of high contrast, a ray tracing image processing system may render an anti-aliased image while minimizing the increase in workload experienced by the image processing system. Additionally, according to another embodiment of the invention, by maintaining the number of rays issued through adjacent pixels which have colors of low contrast while increasing the number of rays issued through adjacent pixels which do not have colors of low contrast, the image processing system may reduce workload experienced while performing ray tracing while maintaining the quality of the rendered image.
摘要翻译：根据本发明的一个实施例，通过在保持通过不具有高对比度的颜色的相邻像素发出的光线的数量的同时增加通过相邻像素发出的具有高对比度的颜色的光线数量，光线跟踪图像处理系统可以呈现抗锯齿图像，同时最小化图像处理系统经历的工作量的增加。此外，根据本发明的另一实施例，通过保持通过具有低对比度的颜色的相邻像素发出的光线的数量，同时增加通过不具有低对比度的颜色的相邻像素发出的光线的数量，图像处理系统减少在执行光线跟踪同时保持渲染图像的质量时遇到的工作量。

3. 发明授权

US08217953B2 Anisotropic texture filtering with texture data prefetching 有权
标题翻译：具有纹理数据预取的各向异性纹理过滤
公开(公告)号：US08217953B2
公开(公告)日：2012-07-10
申请号：US12110045
申请日：2008-04-25
申请人： Miguel Comparan , Eric Oliver Mejdrich , Adam James Muff , Matthew Ray Tubbs
发明人： Miguel Comparan , Eric Oliver Mejdrich , Adam James Muff , Matthew Ray Tubbs
IPC分类号： G09G5/00
CPC分类号： G06T15/04 , G06T2200/12
摘要： A circuit arrangement and method utilize texture data prefetching to prefetch texture data used by an anisotropic filtering algorithm. In particular, stride-based prefetching may be used to prefetch texture data for use in anisotropic filtering, where the value of the stride, or difference between successive accesses, is based upon a distance in a memory address space between sample points taken along the line of anisotropy used in an anisotropic filtering algorithm.
摘要翻译：电路布置和方法利用纹理数据预取来预取由各向异性滤波算法使用的纹理数据。特别地，可以使用基于步幅的预取来预取用于各向异性过滤中的纹理数据，其中步幅的值或连续访问之间的差是基于沿着线所取的采样点之间的存储器地址空间中的距离在各向异性过滤算法中使用各向异性。

4. 发明授权

US08169439B2 Scalar precision float implementation on the “W” lane of vector unit 失效
标题翻译：向量单位“W”通道上的标量精度浮点执行
公开(公告)号：US08169439B2
公开(公告)日：2012-05-01
申请号：US11877205
申请日：2007-10-23
申请人： David Arnold Luick , Eric Oliver Mejdrich , Adam James Muff
发明人： David Arnold Luick , Eric Oliver Mejdrich , Adam James Muff
IPC分类号： G06T15/20
CPC分类号： G06F9/3885 , G06F9/30032 , G06F9/30036 , G06F9/30109 , G06F9/3887 , G06T1/20
摘要： Embodiments of the invention are generally related to image processing, and more specifically to vector units for supporting image processing. A combined vector/scalar unit is provided wherein one or more processing lanes of the vector unit are used for performing scalar operations. An integrated register file is also provided for storing vector and scalar data. Therefore, the transfer of data to memory to exchange data between independent vector and scalar units is obviated and a significant amount of chip area is saved.
摘要翻译：本发明的实施例通常涉及图像处理，更具体地涉及用于支持图像处理的矢量单元。提供了组合矢量/标量单元，其中矢量单元的一个或多个处理通道用于执行标量运算。还提供了用于存储向量和标量数据的集成寄存器文件。因此，消除了将数据传输到存储器以在独立矢量和标量单位之间交换数据，并且节省了大量的芯片面积。

5. 发明授权

US08161271B2 Store misaligned vector with permute 失效
标题翻译：存储未对齐的向量与置换
公开(公告)号：US08161271B2
公开(公告)日：2012-04-17
申请号：US11775999
申请日：2007-07-11
申请人： David Arnold Luick , Eric Oliver Mejdrich , Adam James Muff
发明人： David Arnold Luick , Eric Oliver Mejdrich , Adam James Muff
IPC分类号： G06F15/00 , G06F15/76 , G06F9/30 , G06F9/40 , G06F7/38 , G06F9/00 , G06F9/44 , G06F9/26 , G06F9/34
CPC分类号： G06T15/06
摘要： Embodiments of the invention provide logic within the store data path between a processor and a memory array. The logic may be configured to misalign vector data as it is stored to memory. By misaligning vector data as it is stored to memory, memory bandwidth may be maximized while processing bandwidth required to store vector data misaligned is minimized. Furthermore, embodiments of the invention provide logic within the load data path which allows vector data which is stored misaligned to be aligned as it is loaded into a vector register. By aligning misaligned vector data as it is loaded into a vector register, memory bandwidth may be maximized while processing bandwidth required to align misaligned vector data may be minimized.
摘要翻译：本发明的实施例提供处理器和存储器阵列之间的存储数据路径内的逻辑。逻辑可以被配置为在向量数据存储到存储器时将其对准。通过在将矢量数据存储到存储器时将其对准，存储器带宽可以最大化，而存储向量数据不对齐所需的处理带宽最小化。此外，本发明的实施例提供了负载数据路径内的逻辑，其允许存储的未对准的矢量数据在被加载到向量寄存器中时被对准。通过在将其加载到向量寄存器中时对准未对齐的矢量数据，可以最大化存储器带宽，同时可以最小化对准未对齐矢量数据所需的处理带宽。

6. 发明授权

US08139060B2 Ray tracing image processing system 有权
标题翻译：光线跟踪图像处理系统
公开(公告)号：US08139060B2
公开(公告)日：2012-03-20
申请号：US11563978
申请日：2006-11-28
申请人： Jeffrey Douglas Brown , Russell Dean Hoover , Eric Oliver Mejdrich
发明人： Jeffrey Douglas Brown , Russell Dean Hoover , Eric Oliver Mejdrich
IPC分类号： G06T15/10 , G06T15/20 , G06T15/50 , G06T15/60
CPC分类号： G06T15/40 , G06T15/06
摘要： According to embodiments of the invention, a normally recursive ray tracing algorithm may be partitioned to form an iterative ray tracing algorithm. The resulting portions of the iterative ray tracing algorithm may be executed by a plurality of processing elements. Furthermore, according to embodiments of the invention, a network of inboxes may be used to transfer information which defines original rays and secondary rays (information unlikely to be reused for subsequently issued rays and subsequently rendered frames) between processing elements, and a shared memory cache may store information relating to a three dimensional scene (information likely to be reused for subsequently issued rays and subsequently rendered frames). Using a plurality of processing elements to perform ray tracing and storing information in the shared memory cache which is likely to be reused for subsequent rays and subsequent frames, the performance of a ray tracing image processing system may be improved.
摘要翻译：根据本发明的实施例，正常递归光线跟踪算法可以被分割以形成迭代光线跟踪算法。迭代光线跟踪算法的结果部分可以由多个处理元件执行。此外，根据本发明的实施例，可以使用收件箱网络来传送定义在处理元件之间的原始光线和次级光线（不太可能再次用于随后发出的光线和随后渲染的帧的信息）的信息，以及共享存储器高速缓存可以存储与三维场景有关的信息（可能再次用于随后发出的光线和随后渲染的帧的信息）。使用多个处理元件来执行光线跟踪并且将信息存储在共享存储器高速缓存中，这可能被重用于后续的光线和后续的帧，可以提高光线跟踪图像处理系统的性能。

7. 发明申请

US20110283086A1 STREAMING PHYSICS COLLISION DETECTION IN MULTITHREADED RENDERING SOFTWARE PIPELINE 有权
标题翻译：多媒体渲染软件流水线物理碰撞检测
公开(公告)号：US20110283086A1
公开(公告)日：2011-11-17
申请号：US12778390
申请日：2010-05-12
申请人： Eric Oliver Mejdrich , Paul Emery Schardt , Robert Allen Shearer
发明人： Eric Oliver Mejdrich , Paul Emery Schardt , Robert Allen Shearer
IPC分类号： G06F15/76 , G06F9/02
CPC分类号： G06F9/3851 , G06F9/3802 , G06F9/3838 , G06F9/3842 , G06F9/3877 , G06F15/7825 , G06T17/00 , G06T2210/21
摘要： A circuit arrangement, program product and method stream level of detail components between hardware threads in a multithreaded circuit arrangement to perform physics collision detection. Typically, a master hardware thread, e.g., a component loader hardware thread, is used to retrieve level of detail data for an object from a memory and stream the data to one or more slave hardware threads, e.g., collision detection hardware threads, to perform the actual collision detection. Because the slave hardware threads receive the level of detail data from the master thread, typically the slave hardware threads are not required to load the data from the memory, thereby reducing memory bandwidth requirements and accelerating performance.
摘要翻译：在多线程电路布置中的硬件线程之间的电路布置，程序产品和方法流级别的细节组件来执行物理冲突检测。通常，主硬件线程（例如，组件加载器硬件线程）用于从存储器检索对象的细节数据级别，并将数据流传送到一个或多个从属硬件线程，例如冲突检测硬件线程，以执行实际碰撞检测。由于从属硬件线程接收到主线程的详细数据级别，通常从硬件线程不需要从存储器加载数据，从而减少内存带宽需求并加速性能。

8. 发明授权

US07945764B2 Processing unit incorporating multirate execution unit 失效
标题翻译：包含多速率执行单元的处理单元
公开(公告)号：US07945764B2
公开(公告)日：2011-05-17
申请号：US11972746
申请日：2008-01-11
申请人： Eric Oliver Mejdrich , Adam James Muff , Matthew Ray Tubbs
发明人： Eric Oliver Mejdrich , Adam James Muff , Matthew Ray Tubbs
IPC分类号： G06F9/30
CPC分类号： G06F9/3869 , G06F1/3203 , G06F1/324 , G06F9/3836 , G06F9/3838 , G06F9/3851 , G06F9/3885 , Y02D10/126
摘要： A multirate execution unit is capable of being operated in a plurality of modes, with the execution unit being capable of clocked at multiple different rates relative to a multithreaded issue unit such that, in applications where maximum performance is desired, the execution unit can be clocked at a rate that is faster than the clock rate for the multithreaded issue unit, and in applications where a lower power profile is desired, the execution unit can be throttled back to a slower rate to reduce the power consumption of the execution unit. When the execution unit is clocked at a faster rate than the multithreaded issue unit, the issue unit is permitted to issue more instructions per cycle than when the execution unit is throttled to the slower rate to increase overall instruction throughput.
摘要翻译：多速率执行单元能够以多种模式操作，其中执行单元能够以相对于多线程发布单元的多个不同速率进行计时，使得在需要最大性能的应用中，执行单元可被计时以比多线程发布单元的时钟速率快的速率，以及在需要较低功率配置的应用中，执行单元可以被限制回到较慢的速率以降低执行单元的功耗。当执行单元以比多线程发布单元更快的速度进行计时时，允许发布单元每循环发出更多指令，而不是执行单元被限制到较慢的速率以增加总体指令吞吐量。

9. 发明授权

US07926009B2 Dual independent and shared resource vector execution units with shared register file 有权
标题翻译：具有共享寄存器文件的双独立和共享资源向量执行单元
公开(公告)号：US07926009B2
公开(公告)日：2011-04-12
申请号：US11924980
申请日：2007-10-26
申请人： Eric Oliver Mejdrich , Adam James Muff , Matthew Ray Tubbs
发明人： Eric Oliver Mejdrich , Adam James Muff , Matthew Ray Tubbs
IPC分类号： G06F17/50
CPC分类号： G06T1/20 , G06F15/8092 , G06T15/005
摘要： The present invention is generally related to integrated circuit devices, and more particularly, to methods, systems and design structures for the field of image processing, and more specifically to vector units for supporting image processing. A dual vector unit implementation is described wherein two vector units are configured receive data from a common register file. The vector units may independently and simultaneously process instructions. Furthermore, the vector units may be adapted to perform scalar operations thereby integrating the vector and scalar processing. The vector units may also be configured to share resources to perform an operation, for example, a cross product operation.
摘要翻译：本发明通常涉及集成电路装置，更具体地涉及图像处理领域的方法，系统和设计结构，更具体地涉及用于支持图像处理的矢量单元。描述了双向量单元实现，其中配置了两个向量单元从公共寄存器文件接收数据。向量单元可以独立地并且同时处理指令。此外，矢量单元可以适于执行标量运算，从而整合向量和标量处理。矢量单元还可以被配置为共享资源以执行操作，例如交叉产品操作。

10. 发明申请

US20100188403A1 Tree Insertion Depth Adjustment Based on View Frustrum and Distance Culling 有权
标题翻译：基于视图和距离剔除的树插入深度调整
公开(公告)号：US20100188403A1
公开(公告)日：2010-07-29
申请号：US12361006
申请日：2009-01-28
申请人： Eric Oliver Mejdrich , Paul Emery Schardt , Robert Allen Shearer , Matthew Ray Tubbs
发明人： Eric Oliver Mejdrich , Paul Emery Schardt , Robert Allen Shearer , Matthew Ray Tubbs
IPC分类号： G06T15/50 , G06T15/00
CPC分类号： G06T15/06 , G06T17/005
摘要： A method, program product and system for conducting a ray tracing operation where the rendering compute requirement is reduced by varying the size of bounding volumes into which image data is divided and/or by varying a number of primitives included within nodes of an acceleration data structure that correspond to the bounding volumes.
摘要翻译：一种用于进行光线跟踪操作的方法，程序产品和系统，其中通过改变分割图像数据的边界体积的大小和/或通过改变包括在加速度数据结构的节点内的原始数量来减少渲染计算要求对应于边界体积。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式