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1. 发明授权

US09009369B2 Lookahead scheme for prioritized reads 有权
标题翻译：优先阅读的前瞻方案
公开(公告)号：US09009369B2
公开(公告)日：2015-04-14
申请号：US13282873
申请日：2011-10-27
申请人： Rajat Goel , Hari S. Kannan , Khurram Z. Malik
发明人： Rajat Goel , Hari S. Kannan , Khurram Z. Malik
IPC分类号： G06F3/06 , G11C8/06 , G11C8/16 , G06F13/00
CPC分类号： G06F12/0215 , G06F5/16 , G06F13/1673 , G06F2212/301 , G11C8/06 , G11C8/16
摘要： A circular queue implementing a scheme for prioritized reads is disclosed. In one embodiment, a circular queue (or buffer) includes a number of storage locations each configured to store a data value. A multiplexer tree is coupled between the storage locations and a read port. A priority circuit is configured to generate and provide selection signals to each multiplexer of the multiplexer tree, based on a priority scheme. Based on the states of the selection signals, one of the storage locations is coupled to the read port via the multiplexers of the multiplexer tree.
摘要翻译：公开了实现优先读取方案的循环队列。在一个实施例中，循环队列（或缓冲器）包括多个存储位置，每个存储位置被配置为存储数据值。复用器树耦合在存储位置和读端口之间。优先级电路被配置为基于优先级方案来生成并提供对多路复用器树的每个多路复用器的选择信号。基于选择信号的状态，其中一个存储位置经由复用器树的多路复用器耦合到读端口。

2. 发明授权

US08169246B2 Dynamic-to-static converter latch with glitch suppression 有权
标题翻译：具有毛刺抑制的动态到静态转换器锁存器
公开(公告)号：US08169246B2
公开(公告)日：2012-05-01
申请号：US12713904
申请日：2010-02-26
申请人： Khurram Z. Malik , Andrew L. Arengo
发明人： Khurram Z. Malik , Andrew L. Arengo
IPC分类号： H03K3/356
CPC分类号： H03K3/356191
摘要： A latch circuit. The latch circuit may include an input circuit, a precharge circuit, and a transfer circuit. The precharge circuit may precharge a first node during a first phase of a clock signal. Based on an input signal received at a first logic value, the input signal may drive the first node to a second logic value during the second clock phase. The transfer circuit may include a discharge circuit that is active during an evaluation phase beginning at a delay time subsequent to the clock signal entering the second phase and ending when the clock signal re-enters the first phase. The transfer circuit may also include pull-up and pull-down transistors, one of which may drive a logic value to a second node during the evaluation phase.
摘要翻译：锁存电路。锁存电路可以包括输入电路，预充电电路和传输电路。预充电电路可以在时钟信号的第一阶段期间对第一节点进行预充电。基于在第一逻辑值接收的输入信号，输入信号可以在第二时钟相位期间将第一节点驱动到第二逻辑值。传输电路可以包括在时钟信号进入第二阶段之后的延迟时间开始的评估阶段期间有效的放电电路，并且当时钟信号重新进入第一阶段时结束。传输电路还可以包括上拉和下拉晶体管，其中一个可以在评估阶段期间将逻辑值驱动到第二个节点。

3. 发明申请

US20110210775A1 DYNAMIC-TO-STATIC CONVERTER LATCH WITH GLITCH SUPPRESSION 有权
标题翻译：具有滑动抑制功能的动态至静态转换器锁扣
公开(公告)号：US20110210775A1
公开(公告)日：2011-09-01
申请号：US12713904
申请日：2010-02-26
申请人： Khurram Z. Malik , Andrew L. Arengo
发明人： Khurram Z. Malik , Andrew L. Arengo
IPC分类号： H03K3/00
CPC分类号： H03K3/356191
摘要： A latch circuit. The latch circuit may include an input circuit, a precharge circuit, and a transfer circuit. The precharge circuit may precharge a first node during a first phase of a clock signal. Based on an input signal received at a first logic value, the input signal may drive the first node to a second logic value during the second clock phase. The transfer circuit may include a discharge circuit that is active during an evaluation phase beginning at a delay time subsequent to the clock signal entering the second phase and ending when the clock signal re-enters the first phase. The transfer circuit may also include pull-up and pull-down transistors, one of which may drive a logic value to a second node during the evaluation phase.
摘要翻译：锁存电路。锁存电路可以包括输入电路，预充电电路和传输电路。预充电电路可以在时钟信号的第一阶段期间对第一节点进行预充电。基于在第一逻辑值接收的输入信号，输入信号可以在第二时钟相位期间将第一节点驱动到第二逻辑值。传输电路可以包括在时钟信号进入第二阶段之后的延迟时间开始的评估阶段期间有效的放电电路，并且当时钟信号重新进入第一阶段时结束。传输电路还可以包括上拉和下拉晶体管，其中一个可以在评估阶段期间将逻辑值驱动到第二个节点。

4. 发明申请

US20130107655A1 Lookahead Scheme for Prioritized Reads 有权
公开(公告)号：US20130107655A1
公开(公告)日：2013-05-02
申请号：US13282873
申请日：2011-10-27
申请人： Rajat Goel , Hari S. Kannan , Khurram Z. Malik
发明人： Rajat Goel , Hari S. Kannan , Khurram Z. Malik
IPC分类号： G11C8/06 , G11C8/00
CPC分类号： G06F12/0215 , G06F5/16 , G06F13/1673 , G06F2212/301 , G11C8/06 , G11C8/16
摘要： A circular queue implementing a scheme for prioritized reads is disclosed. In one embodiment, a circular queue (or buffer) includes a number of storage locations each configured to store a data value. A multiplexer tree is coupled between the storage locations and a read port. A priority circuit is configured to generate and provide selection signals to each multiplexer of the multiplexer tree, based on a priority scheme. Based on the states of the selection signals, one of the storage locations is coupled to the read port via the multiplexers of the multiplexer tree.

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