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1. 发明申请

US20130138924A1 EFFICIENT MICROCODE INSTRUCTION DISPATCH 有权
标题翻译：高效的麦克风指令分配
公开(公告)号：US20130138924A1
公开(公告)日：2013-05-30
申请号：US13307969
申请日：2011-11-30
申请人： Ramesh B. Gunna , Peter J. Bannon , Rajat Goel
发明人： Ramesh B. Gunna , Peter J. Bannon , Rajat Goel
IPC分类号： G06F9/22
CPC分类号： G06F9/3836 , G06F9/22 , G06F9/28 , G06F9/30145 , G06F9/3017 , G06F9/3814
摘要： An apparatus and method for avoiding bubbles and maintaining a maximum instruction throughput rate when cracking microcode instructions. A lookahead pointer scans the newest entries of a dispatch queue for microcode instructions. A detected microcode instruction is conveyed to a microcode engine to be cracked into a sequence of micro-ops. Then, the sequence of micro-ops is placed in a queue, and when the original microcode instruction entry in the dispatch queue is selected for dispatch, the sequence of micro-ops is dispatched to the next stage of the processor pipeline.
摘要翻译：一种用于在破解微代码指令时避免气泡并保持最大指令吞吐率的装置和方法。先行指针扫描调度队列的最新条目以获取微代码指令。检测到的微代码指令被传送到微代码引擎以被破解成微操作序列。然后，将微操作序列放置在队列中，并且当调度队列中的原始微代码指令条目被选择用于分派时，微操作序列被分派到处理器管线的下一个阶段。

2. 发明申请

US20130107655A1 Lookahead Scheme for Prioritized Reads 有权
公开(公告)号：US20130107655A1
公开(公告)日：2013-05-02
申请号：US13282873
申请日：2011-10-27
申请人： Rajat Goel , Hari S. Kannan , Khurram Z. Malik
发明人： Rajat Goel , Hari S. Kannan , Khurram Z. Malik
IPC分类号： G11C8/06 , G11C8/00
CPC分类号： G06F12/0215 , G06F5/16 , G06F13/1673 , G06F2212/301 , G11C8/06 , G11C8/16
摘要： A circular queue implementing a scheme for prioritized reads is disclosed. In one embodiment, a circular queue (or buffer) includes a number of storage locations each configured to store a data value. A multiplexer tree is coupled between the storage locations and a read port. A priority circuit is configured to generate and provide selection signals to each multiplexer of the multiplexer tree, based on a priority scheme. Based on the states of the selection signals, one of the storage locations is coupled to the read port via the multiplexers of the multiplexer tree.

3. 发明申请

US20110022824A1 Address Generation Unit with Pseudo Sum to Accelerate Load/Store Operations 有权
标题翻译：地址生成单位，具有伪和，加速加载/存储操作
公开(公告)号：US20110022824A1
公开(公告)日：2011-01-27
申请号：US12506311
申请日：2009-07-21
申请人： Rajat Goel , Chen-Ju Hsieh
发明人： Rajat Goel , Chen-Ju Hsieh
IPC分类号： G06F9/30
CPC分类号： G06F9/3017 , G06F7/506 , G06F7/60 , G06F9/355 , G06F9/3824
摘要： In an embodiment, an address generation unit (AGU) is configured to generate a pseudo sum from an index portion of two or more operands. The pseudo sum may equal the index if the carry-in of the actual sum to the least significant bit of the index is a selected value (e.g. zero). The AGU may also include circuitry coupled to receive the operands and to generate the actual carry-in to the least significant bit of the index. The AGU may transmit the pseudo sum and the carry-in to a decode block for a memory array. The decode block may decode the pseudo sum into one or more one-hot vectors. The one-hot vectors may be input to muxes, and the one-hot vectors rotated by one position may be the other input. The actual carry-in may be the selection control of the mux.
摘要翻译：在一个实施例中，地址生成单元（AGU）被配置为从两个或更多个操作数的索引部分生成伪和。如果实际和到索引的最低有效位的进位是一个选定的值（例如零），那么伪和可以等于索引。 AGU还可以包括耦合以接收操作数并且生成索引的最低有效位的实际载入的电路。 AGU可以将伪和和携带发送到用于存储器阵列的解码块。解码块可以将伪和解码成一个或多个单向量向量。单热矢量可以被输入到多路复用器，并且旋转一个位置的一个热向量可以是另一个输入。实际的进位可能是多路复用器的选择控制。

4. 发明授权

US07373486B2 Partially decoded register renamer 有权
标题翻译：部分解码寄存器重命名
公开(公告)号：US07373486B2
公开(公告)日：2008-05-13
申请号：US11214193
申请日：2005-08-29
申请人： Wei-Han Lien , John K Yong , Shyam Sundar , Rajat Goel
发明人： Wei-Han Lien , John K Yong , Shyam Sundar , Rajat Goel
IPC分类号： G06F9/30 , G06F9/40 , G06F15/00
CPC分类号： G06F9/3836 , G06F9/384 , G06F9/3857 , G06F9/3861
摘要： In one embodiment, a renamer comprises a plurality of storage locations and compare circuitry. Each storage location is assigned to a respective renameable resource and is configured to store an identifier corresponding to a youngest instruction operation that writes the respective renameable resource. Coupled to receive an input representing one or more retiring instruction identifiers corresponding to instruction operations that are being retired, the compare circuitry is configured to detect a match between at least a first identifier in a first storage location and one of the retiring identifiers. An encoded form of the identifiers is logically divided into a plurality of fields, and the input comprises a first plurality of bit vectors. Each of the first plurality of bit vectors corresponds to a respective field and includes a bit position for each possible value of the respective field.
摘要翻译：在一个实施例中，重新映射器包括多个存储位置和比较电路。每个存储位置被分配给相应的可重命名资源，并且被配置为存储对应于写入相应可重命名资源的最小指令操作的标识符。耦合以接收表示与正在退休的指令操作相对应的一个或多个退休指令标识符的输入，所述比较电路被配置为检测第一存储位置中的至少第一标识符与退出标识符之一的匹配。标识符的编码形式在逻辑上被划分为多个字段，并且输入包括第一多个比特向量。第一多个位向量中的每一个对应于相应的场，并且包括相应场的每个可能值的比特位置。

5. 发明授权

US07187606B1 Read port circuit for register file 有权
标题翻译：读取寄存器文件的端口电路
公开(公告)号：US07187606B1
公开(公告)日：2007-03-06
申请号：US11208911
申请日：2005-08-22
申请人： Rajat Goel
发明人： Rajat Goel
IPC分类号： G11C7/00
CPC分类号： G11C7/12 , G11C2207/007
摘要： In one embodiment, a read port circuit includes a precharge circuit configured to precharge a first node in the read port circuit and a pulldown circuit coupled to the first node. The pulldown circuit is configured to conditionally discharge the first node responsive to a first plurality of wordline signals and a first plurality of data signals. Each of the wordline signals corresponds to a respective memory cell of a first plurality of memory cells, and each of the data signals corresponds to a respective memory cell and represents data stored in the respective memory cell. In some embodiments, the read port circuit may be included in a register file in an integrated circuit that also includes logic circuitry configured to generate an address for a read port.
摘要翻译：在一个实施例中，读端口电路包括预充电电路，其被配置为对读端口电路中的第一节点进行预充电，以及耦合到第一节点的下拉电路。下拉电路被配置为响应于第一多个字线信号和第一多个数据信号有条件地对第一节点放电。每个字线信号对应于第一多个存储单元的相应存储单元，并且每个数据信号对应于相应的存储单元，并且表示存储在相应存储单元中的数据。在一些实施例中，读端口电路可以被包括在集成电路中的寄存器文件中，该集成电路还包括被配置为生成读端口的地址的逻辑电路。

6. 发明申请

US20070041262A1 Register file 有权
公开(公告)号：US20070041262A1
公开(公告)日：2007-02-22
申请号：US11208912
申请日：2005-08-22
申请人： Rajat Goel
发明人： Rajat Goel
IPC分类号： G11C8/00
CPC分类号： G11C11/412 , G11C7/10 , G11C8/16 , G11C2207/108
摘要： In one embodiment, a memory circuit comprises one or more first memory cells, each of the one or more first memory cells configured to store at least one bit; one or more second memory cells, each of the one or more second memory cells configured to store at least one bit; and one or more read port circuits physically located between the first memory cells and the second memory cells. Each of the read port circuits is coupled to receive the at least one bit from each of the first memory cells and each of the second memory cells, and each of the read port circuits is configured to output the at least one bit from a selected memory cell of the first memory cells and the second memory cells responsive to a plurality of wordline signals coupled to the read port circuit.

7. 发明申请

US20070041250A1 READ PORT CIRCUIT FOR REGISTER FILE 有权
标题翻译：读端口电路用于寄存器文件
公开(公告)号：US20070041250A1
公开(公告)日：2007-02-22
申请号：US11208911
申请日：2005-08-22
申请人： Rajat Goel
发明人： Rajat Goel
IPC分类号： G11C7/10
CPC分类号： G11C7/12 , G11C2207/007
摘要： In one embodiment, a read port circuit comprises a precharge circuit configured to precharge a first node in the read port circuit and a pulldown circuit coupled to the first node. The pulldown circuit is configured to conditionally discharge the first node responsive to a first plurality of wordline signals and a first plurality of data signals. Each of the wordline signals corresponds to a respective memory cell of a first plurality of memory cells, and each of the data signals corresponds to a respective memory cell and represents data stored in the respective memory cell. In some embodiments, the read port circuit may be included in a register file in an integrated circuit that also comprises logic circuitry configured to generate an address for a read port.
摘要翻译：在一个实施例中，读端口电路包括预充电电路，其被配置为对读端口电路中的第一节点进行预充电，以及耦合到第一节点的下拉电路。下拉电路被配置为响应于第一多个字线信号和第一多个数据信号有条件地对第一节点放电。每个字线信号对应于第一多个存储单元的相应存储单元，并且每个数据信号对应于相应的存储单元，并且表示存储在相应存储单元中的数据。在一些实施例中，读端口电路可以包括在集成电路中的寄存器文件中，该集成电路还包括被配置为生成读端口的地址的逻辑电路。

8. 发明申请

US20060184783A1 System and method for providing an extensible codec architecture for digital images 有权
公开(公告)号：US20060184783A1
公开(公告)日：2006-08-17
申请号：US11062301
申请日：2005-02-17
申请人： David Albert , Frank Krueger , Rajat Goel , Peter Gurevich , Anthony Hodsdon , Radu Magarint , Thomas Olsen , Rahul Patil , Cyra Richardson , Robert Sinclair , Richard Turner , Eric Vandenberg , Robert Wlodarczyk
发明人： David Albert , Frank Krueger , Rajat Goel , Peter Gurevich , Anthony Hodsdon , Radu Magarint , Thomas Olsen , Rahul Patil , Cyra Richardson , Robert Sinclair , Richard Turner , Eric Vandenberg , Robert Wlodarczyk
IPC分类号： G06F1/24 , G06F15/177
CPC分类号： H04N19/162 , H04N19/12 , H04N19/157 , H04N19/172
摘要： An improved system and method for an extensible codec architecture for digital images is provided. Executable software code may be operably coupled to a codec manager for requesting imaging operations to be performed on a digital image. The codec manager may receive the request to perform an imaging operation on the digital image and may select an imaging component, such as a codec, from one or more imaging components registered in the computer system for performing an imaging operation on the digital image. An arbitration manager may include functionality for requesting enumeration of the operations an imaging component may perform on a particular digital image. One or more pixel format converters may then convert the pixel format in the digital image to a pixel format supported by an imaging component installed on the system.

9. 发明申请

US20060184576A1 System and method for extensible metadata architecture for digital images 审中-公开
标题翻译：用于数字图像的可扩展元数据结构的系统和方法
公开(公告)号：US20060184576A1
公开(公告)日：2006-08-17
申请号：US11062267
申请日：2005-02-17
申请人： David Albert , Frank Krueger , Rajat Goel , Peter Gurevich , Anthony Hodsdon , Radu Magarint , Thomas Olsen , Rahul Patil , Cyra Richardson , Robert Sinclair , Richard Turner , Eric Vandenberg , Robert Wlodarczyk
发明人： David Albert , Frank Krueger , Rajat Goel , Peter Gurevich , Anthony Hodsdon , Radu Magarint , Thomas Olsen , Rahul Patil , Cyra Richardson , Robert Sinclair , Richard Turner , Eric Vandenberg , Robert Wlodarczyk
IPC分类号： G06F17/00
CPC分类号： G06F16/58 , G06F16/48
摘要： An improved system and method for an extensible metadata architecture for digital images is provided. Executable software code may be operably coupled to a metadata query reader and a metadata query writer for requesting operations for manipulating metadata in an image file. The metadata query reader may be operably coupled to a decoder having a block reader for identifying metadata blocks in an image file and associating a metadata reader with each metadata block. Each metadata reader may then enumerate the metadata in the metadata block associated with that metadata reader. The metadata query writer may be operably coupled to an encoder having a block writer for associating a metadata writer with each metadata block to be written to an image file. Each metadata writer may then write metadata in the metadata block associated with that metadata writer.
摘要翻译：提供了一种用于数字图像的可扩展元数据结构的改进的系统和方法。可执行软件代码可以可操作地耦合到元数据查询阅读器和元数据查询写入器，用于请求操作以操纵图像文件中的元数据。元数据查询读取器可以可操作地耦合到具有用于识别图像文件中的元数据块并将元数据读取器与每个元数据块相关联的块读取器的解码器。然后，每个元数据读取器可以枚举与该元数据读取器相关联的元数据块中的元数据。元数据查询写入器可以可操作地耦合到具有块写入器的编码器，用于将元数据写入器与要写入图像文件的每个元数据块相关联。然后，每个元数据写入器可以在与该元数据写入器相关联的元数据块中写入元数据。

10. 发明授权

US08914580B2 Reducing cache power consumption for sequential accesses 有权
标题翻译：减少顺序访问的高速缓存功耗
公开(公告)号：US08914580B2
公开(公告)日：2014-12-16
申请号：US12861091
申请日：2010-08-23
申请人： Rajat Goel , Ian D. Kountanis
发明人： Rajat Goel , Ian D. Kountanis
IPC分类号： G06F12/08
CPC分类号： G06F12/0882 , G06F12/0888 , G06F2212/1028 , Y02D10/13
摘要： In some embodiments, a cache may include a tag array and a data array, as well as circuitry that detects whether accesses to the cache are sequential (e.g., occupying the same cache line). For example, a cache may include a tag array and a data array that stores data, such as multiple bundles of instructions per cache line. During operation, it may be determined that successive cache requests are sequential and do not cross a cache line boundary. Responsively, various cache operations may be inhibited to conserve power. For example, access to the tag array and/or data array, or portions thereof, may be inhibited.
摘要翻译：在一些实施例中，高速缓存可以包括标签阵列和数据阵列，以及检测对高速缓存的访问是否是顺序的（例如，占用相同的高速缓存行）的电路。例如，高速缓存可以包括标签阵列和存储数据的数据阵列，例如每个高速缓存线的多条指令束。在操作期间，可以确定连续的缓存请求是顺序的，并且不跨越高速缓存行边界。响应地，可以抑制各种高速缓存操作以节省功率。例如，可以禁止对标签阵列和/或数据阵列或其部分的访问。

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