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1. 发明申请

US20140103392A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20140103392A1
公开(公告)日：2014-04-17
申请号：US14106942
申请日：2013-12-16
申请人： Kiminori HAYANO
发明人： Kiminori HAYANO
IPC分类号： H01L27/06 , H01L27/092
CPC分类号： H01L27/0623 , H01L21/2815 , H01L21/823885 , H01L27/0251 , H01L27/0617 , H01L27/092 , H01L29/0692 , H01L29/42356 , H01L29/42376 , H01L29/66666 , H01L29/735 , H01L29/7436 , H01L29/7827
摘要： A semiconductor device comprises a vertical MOS transistor including a semiconductor substrate having a silicon pillar, a gate electrode formed along a sidewall of the silicon pillar, a gate insulating film formed between the gate electrode and the silicon pillar, an upper diffusion layer formed on the top of the silicon pillar, and a lower diffusion layer formed lower than the upper diffusion layer in the semiconductor substrate; and a pad electrically connected to the lower diffusion layer. Breakdown occurs between the lower diffusion layer and the semiconductor substrate when a surge voltage is applied.
摘要翻译：半导体器件包括垂直MOS晶体管，其包括具有硅柱的半导体衬底，沿着硅柱的侧壁形成的栅电极，形成在栅电极和硅柱之间的栅极绝缘膜，形成在硅柱上的上扩散层所述硅柱的顶部以及在所述半导体衬底中形成为低于所述上扩散层的下扩散层; 以及电连接到下扩散层的焊盘。当施加浪涌电压时，在下扩散层和半导体衬底之间发生击穿。

2. 发明申请

US20130027824A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20130027824A1
公开(公告)日：2013-01-31
申请号：US13553746
申请日：2012-07-19
申请人： Kiminori Hayano
发明人： Kiminori Hayano
IPC分类号： H02H9/04
CPC分类号： H01L27/0292 , H03K19/00315
摘要： A semiconductor device comprises a first power supply system, a second power supply system, an output circuit, a first driving circuit and a first protection. The first power supply system is configured with a first power supply voltage and a first ground voltage. The second power supply system is configured with a second power supply voltage and a second ground voltage. The output circuit receives a power supply from the second power supply system. The first driving circuit receives a power supply from the first power supply system and outputs a signal for driving the output circuit. One end of the first protection element is connected to an output node of the output circuit and the other end is connected to the first ground voltage.
摘要翻译：半导体器件包括第一电源系统，第二电源系统，输出电路，第一驱动电路和第一保护。第一电源系统配置有第一电源电压和第一接地电压。第二电源系统配置有第二电源电压和第二接地电压。输出电路从第二电源系统接收电源。第一驱动电路从第一电源系统接收电源并输出用于驱动输出电路的信号。第一保护元件的一端连接到输出电路的输出节点，另一端连接到第一接地电压。

3. 发明申请

US20070235809A1 Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：US20070235809A1
公开(公告)日：2007-10-11
申请号：US11783095
申请日：2007-04-05
申请人： Kiminori Hayano
发明人： Kiminori Hayano
IPC分类号： H01L23/62
CPC分类号： H01L27/0811 , H01L27/0266
摘要： A semiconductor device includes electrostatic protection circuit Q formed by connecting first NMOS transistor Q1 having first threshold voltage and second NMOS transistor Q2 having second threshold voltage lower than the first threshold voltage in parallel between power supply terminal N1 and ground terminal N2. Film thickness of gate insulating film 4 of the second NMOS transistor Q2 is formed to be thinner than that of gate insulating film 5 of the first NMOS transistor Q1. A source/drain region 7b of the transistor Q1 and a source/drain region 7d of the transistor Q2 are connected to power supply terminal N1. Source/drain region 7a of transistor Q1, gate electrode 5a of transistor Q1, source/drain region 7c of transistor Q2, gate electrode 5b of transistor Q2, and substrate 1 are connected to ground terminal N2. Leak current and operation start voltage are reduced.
摘要翻译：半导体器件包括通过在电源端子N 1和接地端子N 2之间并联连接第一阈值电压的第一NMOS晶体管Q 1和具有低于第一阈值电压的第二阈值电压的第二NMOS晶体管Q 2形成的静电保护电路Q。第二NMOS晶体管Q 2的栅极绝缘膜4的膜厚形成为比第一NMOS晶体管Q1的栅极绝缘膜5薄。膜晶体管Q 1的源极/漏极区域7b和源极/ 晶体管Q 2的漏极区域7d连接到电源端子N 1.晶体管Q1的源极/漏极区域7a，晶体管Q 1的栅极电极5a，晶体管Q2的源极/漏极区域7c，栅极晶体管Q 2的电极5b和基板1连接到接地端子N 2。漏电流和操作开始电压降低。

4. 发明授权

US08937793B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08937793B2
公开(公告)日：2015-01-20
申请号：US13553746
申请日：2012-07-19
申请人： Kiminori Hayano
发明人： Kiminori Hayano
IPC分类号： H02H3/22 , H01L27/02 , H03K19/003
CPC分类号： H01L27/0292 , H03K19/00315
摘要： A semiconductor device comprises a first power supply system, a second power supply system, an output circuit, a first driving circuit and a first protection. The first power supply system is configured with a first power supply voltage and a first ground voltage. The second power supply system is configured with a second power supply voltage and a second ground voltage. The output circuit receives a power supply from the second power supply system. The first driving circuit receives a power supply from the first power supply system and outputs a signal for driving the output circuit. One end of the first protection element is connected to an output node of the output circuit and the other end is connected to the first ground voltage.
摘要翻译：半导体器件包括第一电源系统，第二电源系统，输出电路，第一驱动电路和第一保护。第一电源系统配置有第一电源电压和第一接地电压。第二电源系统配置有第二电源电压和第二接地电压。输出电路从第二电源系统接收电源。第一驱动电路从第一电源系统接收电源并输出用于驱动输出电路的信号。第一保护元件的一端连接到输出电路的输出节点，另一端连接到第一接地电压。

5. 发明授权

US5751051A Semiconductor device equipped with electrostatic breakdown protection circuit 失效
标题翻译：半导体装置配有静电击穿保护电路
公开(公告)号：US5751051A
公开(公告)日：1998-05-12
申请号：US951412
申请日：1997-10-16
申请人： Kiminori Hayano
发明人： Kiminori Hayano
IPC分类号： H01L27/04 , H01L21/822 , H01L23/58 , H01L27/02 , H01L29/00 , H02H9/00
CPC分类号： H01L24/06 , H01L27/0251 , H01L2224/04042 , H01L2224/05554 , H01L2224/05599 , H01L2224/06136 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01082 , H01L2924/1305 , H01L2924/13091 , H01L2924/3011
摘要： A semiconductor device has a semiconductor chip which is divided into a plurality of separate regions. In each of these regions, there are provided a plurality of common discharge lines which are independent from one another, a plurality of first bonding pads which are connected directly to the respective common discharge lines, a plurality of second bonding pads which are not connected directly to the common discharge lines, a plurality of protective elements which are connected between the second bonding pads and the common discharge lines, and an inner lead for discharging which is directly connected to the first bonding pads and is bonded to a surface of the semiconductor chip. In all embodiments of the invention. More than one common discharge line is provided. This arrangement permits the reduction of the chip area thus enhancing design freedom and improving electrostatic breakdown characteristics.
摘要翻译：半导体器件具有被分成多个分离区域的半导体芯片。在这些区域的每一个中，设置有彼此独立的多个公共放电线，多个直接连接到各个公共放电线的第一接合焊盘，不直接连接的多个第二接合焊盘公共放电线，连接在第二接合焊盘和公共放电线之间的多个保护元件和直接连接到第一接合焊盘的用于放电的内部引线，并且接合到半导体芯片的表面。在本发明的所有实施例中。提供多于一个公共放电线。这种布置允许减小芯片面积，从而提高设计自由度并改善静电击穿特性。

6. 发明授权

US5361231A Dynamic random access memory device with redundant word lines shared between memory cell arrays 失效
标题翻译：具有在存储单元阵列之间共享的冗余字线的动态随机存取存储器件
公开(公告)号：US5361231A
公开(公告)日：1994-11-01
申请号：US157439
申请日：1993-11-26
申请人： Kiminori Hayano
发明人： Kiminori Hayano
IPC分类号： G11C11/401 , G11C29/00 , G11C29/04 , G11C7/00 , G11C13/00
CPC分类号： G11C29/808
摘要： A dynamic random access memory device has a plurality of sense amplifier circuits shared between two regular memory cell arrays respectively associated with redundant memory cell arrays, and two transfer gate arrays are coupled between one of the regular memory cell arrays and one of the redundant memory cell arrays as well as between the other regular memory cell array and the other redundant memory cell array so that a large number of defective memory cells are replaceable with both of the redundant memory cell arrays, thereby improving production yield.
摘要翻译：动态随机存取存储器件具有分别与冗余存储单元阵列相关联的两个常规存储单元阵列之间共享的多个读出放大器电路，并且两个传输门阵列耦合在常规存储单元阵列之一和冗余存储单元之一阵列以及另一个常规存储单元阵列和另一个冗余存储单元阵列之间，使得大量的有缺陷的存储单元可以与两个冗余存储单元阵列替换，从而提高了生产成本。

7. 发明授权

US5195053A Semiconductor memory device wired to accommodate increased capacity without increasing the size of the semiconductor memory device 失效
标题翻译：有线以适应增加的容量而不增加半导体存储器件的尺寸的半导体存储器件
公开(公告)号：US5195053A
公开(公告)日：1993-03-16
申请号：US704916
申请日：1991-05-22
申请人： Kiminori Hayano
发明人： Kiminori Hayano
IPC分类号： G11C5/02 , G11C5/06
CPC分类号： G11C5/025 , G11C5/06
摘要： A boundary region for wiring is provided by expanding one of a plurality of boundary regions boundary regions each being between adjacent ones of a plurality of decoder circuits included in a decoder circuit block corresponding to a memory cell array by shifting a desired portion of at least one of the decoder circuits by a desired distance and a wiring connecting wirings in the decoder circuit to a circuit provided outside the decoder circuit block is arranged in the boundary region for wiring, so that a circuit arrangement in a second region outside the decoder circuits can be made freely.
摘要翻译：通过将包含在与存储单元阵列相对应的解码器电路块中的多个解码器电路中的相邻的解码器电路之间的多个边界区域边界区域中的一个扩展至少一个所需的部分来提供布线的边界区域的解码器电路的布线布置在解码器电路的外部设置在解码器电路块外部的电路，布线在解码器电路的外部的第二区域中，自由做

8. 发明授权

US08633538B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US08633538B2
公开(公告)日：2014-01-21
申请号：US13207947
申请日：2011-08-11
申请人： Kiminori Hayano
发明人： Kiminori Hayano
IPC分类号： H01L29/66
CPC分类号： H01L27/0623 , H01L21/2815 , H01L21/823885 , H01L27/0251 , H01L27/0617 , H01L27/092 , H01L29/0692 , H01L29/42356 , H01L29/42376 , H01L29/66666 , H01L29/735 , H01L29/7436 , H01L29/7827
摘要： A semiconductor device comprises a vertical MOS transistor including a semiconductor substrate having a silicon pillar, a gate electrode formed along a sidewall of the silicon pillar, a gate insulating film formed between the gate electrode and the silicon pillar, an upper diffusion layer formed on the top of the silicon pillar, and a lower diffusion layer formed lower than the upper diffusion layer in the semiconductor substrate; and a pad electrically connected to the lower diffusion layer. Breakdown occurs between the lower diffusion layer and the semiconductor substrate when a surge voltage is applied.
摘要翻译：半导体器件包括垂直MOS晶体管，其包括具有硅柱的半导体衬底，沿着硅柱的侧壁形成的栅电极，形成在栅电极和硅柱之间的栅极绝缘膜，形成在硅柱上的上扩散层所述硅柱的顶部以及在所述半导体衬底中形成为低于所述上扩散层的下扩散层; 以及电连接到下扩散层的焊盘。当施加浪涌电压时，在下扩散层和半导体衬底之间发生击穿。

9. 发明申请

US20120037953A1 SEMICONDUCTOR DEVICE 失效
标题翻译：半导体器件
公开(公告)号：US20120037953A1
公开(公告)日：2012-02-16
申请号：US13207947
申请日：2011-08-11
申请人： Kiminori HAYANO
发明人： Kiminori HAYANO
IPC分类号： H01L27/092 , H01L27/06
CPC分类号： H01L27/0623 , H01L21/2815 , H01L21/823885 , H01L27/0251 , H01L27/0617 , H01L27/092 , H01L29/0692 , H01L29/42356 , H01L29/42376 , H01L29/66666 , H01L29/735 , H01L29/7436 , H01L29/7827
摘要： A semiconductor device comprises a vertical MOS transistor including a semiconductor substrate having a silicon pillar, a gate electrode formed along a sidewall of the silicon pillar, a gate insulating film formed between the gate electrode and the silicon pillar, an upper diffusion layer formed on the top of the silicon pillar, and a lower diffusion layer formed lower than the upper diffusion layer in the semiconductor substrate; and a pad electrically connected to the lower diffusion layer. Breakdown occurs between the lower diffusion layer and the semiconductor substrate when a surge voltage is applied.
摘要翻译：半导体器件包括垂直MOS晶体管，其包括具有硅柱的半导体衬底，沿着硅柱的侧壁形成的栅电极，形成在栅电极和硅柱之间的栅极绝缘膜，形成在硅柱上的上扩散层所述硅柱的顶部以及在所述半导体衬底中形成为低于所述上扩散层的下扩散层; 以及电连接到下扩散层的焊盘。当施加浪涌电压时，在下扩散层和半导体衬底之间发生击穿。

10. 发明授权

US06760204B2 Semiconductor integrated circuit device and method for designing the same 有权
标题翻译：半导体集成电路器件及其设计方法
公开(公告)号：US06760204B2
公开(公告)日：2004-07-06
申请号：US09939870
申请日：2001-08-27
申请人： Yoko Hayashida , Kiminori Hayano , Hiroshi Furuta
发明人： Yoko Hayashida , Kiminori Hayano , Hiroshi Furuta
IPC分类号： H02H900
CPC分类号： H01L27/0288 , H01L27/0266 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor integrated circuit device is disclosed that can provide greater flexibility of layout while essentially ensuring circuit characteristics, and at the same time providing an minimum electrostatic discharge breakdown withstand value according to Charged Device Model (CDM) at all input/output (I/O) terminals. For each I/O terminal a size of a CDM protective device can be optimized in response to reference electric potential wiring resistance between an input protective device, a MOSFETs that can constitute an internal circuit, and an input resistance.
摘要翻译：公开了一种半导体集成电路器件，其可以提供更大的布局灵活性，同时基本上确保电路特性，同时根据所有输入/输出（I / O）处的充电器件模型（CDM）提供最小的静电放电击穿耐受值）终端。对于每个I / O端子，可以响应于输入保护器件，可构成内部电路的MOSFET和输入电阻之间的参考电位布线电阻来优化CDM保护器件的尺寸。

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