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1. 发明申请

US20130320359A1 HETEROGENEOUS STACK STRUCTURES WITH OPTICAL TO ELECTRICAL TIMING REFERENCE DISTRIBUTION 审中-公开
标题翻译：具有光电时间参考分布的异质堆叠结构
公开(公告)号：US20130320359A1
公开(公告)日：2013-12-05
申请号：US13487694
申请日：2012-06-04
申请人： Klaus HUMMLER
发明人： Klaus HUMMLER
IPC分类号： H01L23/48 , H01L31/12 , H01L31/02 , H01L27/144
CPC分类号： G02B6/43 , H01L24/16 , H01L25/0657 , H01L27/1443 , H01L2224/13099 , H01L2224/16146 , H01L2224/16225 , H01L2224/16227 , H01L2225/06513 , H01L2225/06517 , H01L2225/06534 , H01L2924/12042 , H01L2924/15311 , H01L2924/00014 , H01L2924/00
摘要： A heterogeneous stack structure is provided which includes one or more optical signal-based chips and multiple electrical signal-based chips. The optical chip(s) and the electrical chip(s) are different layers of the stack structure, and the optical chip(s) includes optical signal paths extending at least partially laterally within the optical chip(s). Electrical signal paths are provided extending between and coupling the optical chip(s) and the electrical chips. The electrical signal paths include one or more through substrate vias (TSVs) through one or more electrical chips of the multiple electrical chips in the stack structure. In one embodiment, the optical chip(s) is configured laterally to locally distribute, via one or more paths of the electrical signal paths, a timing reference signal for one or more electrical chips in the stack. Conversion between optical and electrical signals within the stack structure occurs within the optical chip(s).
摘要翻译：提供了包括一个或多个基于光信号的芯片和多个基于电信号的芯片的异构堆栈结构。光学芯片和电气芯片是堆叠结构的不同层，并且光学芯片包括在光学芯片内部至少部分地横向延伸的光学信号路径。提供的电信号通路在光学芯片和电气芯片之间延伸并耦合。电信号路径包括通过堆叠结构中的多个电子芯片的一个或多个电气芯片的一个或多个通过衬底通孔（TSV）。在一个实施例中，光学芯片被侧向配置以经由电信号路径的一个或多个路径局部地分配用于堆叠中的一个或多个电气芯片的定时参考信号。堆叠结构内的光和电信号之间的转换发生在光学芯片内。

2. 发明申请

US20080313494A1 MEMORY REFRESH SYSTEM AND METHOD 有权
标题翻译：存储器刷新系统和方法
公开(公告)号：US20080313494A1
公开(公告)日：2008-12-18
申请号：US11763593
申请日：2007-06-15
申请人： Klaus Hummler , Jong Hoon Oh , Wayne Frederick Ellis , Jung Pill Kim , Oliver Kiehl , Josef Schnell , Octavian Beldiman , Lee Ward Collins
发明人： Klaus Hummler , Jong Hoon Oh , Wayne Frederick Ellis , Jung Pill Kim , Oliver Kiehl , Josef Schnell , Octavian Beldiman , Lee Ward Collins
IPC分类号： G06F11/16
CPC分类号： G11C29/02 , G11C7/1039 , G11C11/401 , G11C11/406 , G11C29/028 , G11C29/50016 , G11C2211/4062 , G11C2211/4065
摘要： A refresh scheduler is configured to refresh memory cells of a memory device according to a plurality of refresh intervals. The various refresh intervals are determined in response to refresh errors.
摘要翻译：刷新调度器被配置为根据多个刷新间隔刷新存储器设备的存储单元。响应于刷新错误确定各种刷新间隔。

3. 发明申请

US20080189480A1 Memory configured on a common substrate 有权
标题翻译：存储器配置在公共基板上
公开(公告)号：US20080189480A1
公开(公告)日：2008-08-07
申请号：US11701006
申请日：2007-02-01
申请人： Jung Pill Kim , Jong-Hoon Oh , Oliver Kiehl , Josef Schnell , Klaus Hummler , Wayne Ellis , Octavian Beldiman , Lee Collins
发明人： Jung Pill Kim , Jong-Hoon Oh , Oliver Kiehl , Josef Schnell , Klaus Hummler , Wayne Ellis , Octavian Beldiman , Lee Collins
IPC分类号： G06F12/00
CPC分类号： G11C5/04 , G11C5/063 , H01L2224/16225 , H01L2924/00011 , H01L2924/00014 , H01L2924/15192 , H01L2924/15311 , H05K1/181 , H01L2224/0401
摘要： A memory includes a first macro chip, a spine chip, and a common substrate. The common substrate is configured to pass signals between the first macro chip and the spine chip. The first macro chip, the spine chip, and the common substrate provide a memory.
摘要翻译：存储器包括第一宏芯片，脊芯片和公共基板。公共基板被配置为在第一宏芯片和脊芯片之间传递信号。第一个宏芯片，脊椎芯片和公共基板提供了一个记忆。

4. 发明申请

US20060285412A1 Memory having parity error correction 失效
标题翻译：具有奇偶校验纠错的存储器
公开(公告)号：US20060285412A1
公开(公告)日：2006-12-21
申请号：US11259318
申请日：2005-10-26
申请人： Klaus Hummler
发明人： Klaus Hummler
IPC分类号： G11C7/00
CPC分类号： G11C7/1006 , G06F11/106 , G11C11/406 , G11C11/40615 , G11C11/4078 , G11C2211/4062
摘要： A memory includes a sense amplifier segment and a plurality of word lines including a first transfer word line and a second transfer word line complementary to the first transfer word line. The memory includes a plurality of bit lines coupled to the sense amplifier segment and a memory cell located at each cross point of each word line and each bit line. The first transfer word line and the second transfer word line are adapted for simultaneously inverting data bit values stored in memory cells along a failed word line to correct a parity error during self refresh.
摘要翻译：存储器包括读出放大器段和包括与第一传送字线互补的第一传送字线和第二传送字线的多个字线。存储器包括耦合到读出放大器段的多个位线和位于每个字线和每个位线的每个交叉点处的存储器单元。第一传送字线和第二传输字线适于同时反转沿着故障字线存储在存储器单元中的数据位值，以在自刷新期间校正奇偶校验错误。

5. 发明申请

US20060133186A1 Memory access using multiple activated memory cell rows 有权
标题翻译：使用多个激活的内存单元行进行内存访问
公开(公告)号：US20060133186A1
公开(公告)日：2006-06-22
申请号：US11018313
申请日：2004-12-21
申请人： Klaus Hummler
发明人： Klaus Hummler
IPC分类号： G11C8/00
CPC分类号： G11C7/1018
摘要： For one or more disclosed embodiments, a plurality of rows of memory cells in a memory bank are activated, and a column of memory cells in the memory bank is selected to select memory cells common to activated rows and the selected column. At least one of the selected memory cells common to activated rows and the selected column is selectively accessed. The selecting and the selectively accessing are repeated to access memory cells common to activated rows and a plurality of selected columns.
摘要翻译：对于一个或多个公开的实施例，存储器组中的多行存储器单元被激活，并且存储器组中的一列存储器单元被选择为选择激活行和所选列的公用存储单元。选择性地访问激活行和所选列共用的所选存储单元中的至少一个。重复选择和选择性访问以访问激活行和多个选定列共同的存储单元。

6. 发明授权

US5747802A Automated non-visual method of locating periodically arranged sub-micron objects 失效
标题翻译：定期定位的亚微米物体的自动非视觉方法
公开(公告)号：US5747802A
公开(公告)日：1998-05-05
申请号：US626192
申请日：1996-03-29
申请人： Norbert Arnold , Klaus Hummler , Ernest Levine , Rainer Weiland
发明人： Norbert Arnold , Klaus Hummler , Ernest Levine , Rainer Weiland
IPC分类号： G01B11/00 , G01B15/00 , G01Q20/02 , G01Q30/02 , H01L21/66 , G01N23/00 , H01J37/00
CPC分类号： H01L22/12
摘要： A method is disclosed for locating a particular small objects (down to submicron) within an array of periodically arranged like objects utilizing a scanning tool. The method includes scanning the array for generating a plurality of pulses, which correspond to these objects contained within the array. Counting the plurality of pulses in order to locate the particular object within the array.
摘要翻译：公开了一种用于利用扫描工具定位周期性排列的相似物体的阵列内的特定小物体（至亚微米级）的方法。该方法包括扫描阵列以产生与包含在阵列内的这些对象对应的多个脉冲。计数多个脉冲以便将阵列内的特定对象定位。

7. 发明申请

US20130299950A1 SEMICONDUCTOR STRUCTURE WITH BURIED THROUGH SUBSTRATE VIAS 审中-公开
标题翻译：通过基板VIAS穿过的半导体结构
公开(公告)号：US20130299950A1
公开(公告)日：2013-11-14
申请号：US13469494
申请日：2012-05-11
申请人： Klaus HUMMLER
发明人： Klaus HUMMLER
IPC分类号： H01L23/34 , H01L21/30 , H01L21/20
CPC分类号： H01L23/481 , H01L21/3081 , H01L21/76898 , H01L23/3677 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor structures and methods of fabrication are provided. One semiconductor structure includes a substrate, a semiconductor device layer supported by the substrate, and one or more buried through substrate vias (TSVs) disposed at least partially within the substrate. The buried through substrate via(s) is buried within the semiconductor substrate, and terminates below the semiconductor device layer of the semiconductor structure, and the semiconductor device layer extends over the buried through substrate via(s), thereby providing the buried through substrate via(s) without consuming space within the semiconductor device layer. A dielectric layer may be disposed between the substrate and the semiconductor device layer, with the TSV(s) terminating at a first end within the dielectric layer. Alternatively, the semiconductor device layer may be an epitaxially-grown layer extending over the TSV(s). Where a plurality of buried TSV(s) are employed, the vias may be disposed in a repeating pattern across the semiconductor structure.
摘要翻译：提供半导体结构和制造方法。一个半导体结构包括衬底，由衬底支撑的半导体器件层以及至少部分地设置在衬底内的一个或多个掩埋通孔衬底通孔（TSV）。埋入基板通孔（s）被埋在半导体衬底内，并且终止在半导体结构的半导体器件层的下面，并且半导体器件层在掩埋的衬底上延伸穿过（s），从而提供掩埋的衬底通孔而不消耗半导体器件层内的空间。电介质层可以设置在衬底和半导体器件层之间，其中TSV终止在电介质层内的第一端。或者，半导体器件层可以是在TSV上延伸的外延生长层。在采用多个掩埋TSV的情况下，通孔可以跨越半导体结构以重复图案设置。

8. 发明授权

US07944047B2 Method and structure of expanding, upgrading, or fixing multi-chip package 有权
标题翻译：扩展，升级或固定多芯片封装的方法和结构
公开(公告)号：US07944047B2
公开(公告)日：2011-05-17
申请号：US11860985
申请日：2007-09-25
申请人： Jong Hoon Oh , Klaus Hummler , Oliver Kiehl , Josef Schnell , Wayne Frederick Ellis , Jung Pill Kim , Lee Ward Collins , Octavian Beldiman
发明人： Jong Hoon Oh , Klaus Hummler , Oliver Kiehl , Josef Schnell , Wayne Frederick Ellis , Jung Pill Kim , Lee Ward Collins , Octavian Beldiman
IPC分类号： H01L21/00 , H01L23/34
CPC分类号： H01L25/105 , H01L23/50 , H01L25/0657 , H01L25/18 , H01L2224/16225 , H01L2225/1023 , H01L2225/1058 , H01L2924/15311
摘要： Embodiments of the present invention generally provide techniques and apparatus for altering the functionality of a multi-chip package (MCP) without requiring entire replacement of the MCP. The MCP may be designed with a top package substrate designed to interface with an add-on package that, when sensed by the MCP, alters the functionality of the MCP.
摘要翻译：本发明的实施例通常提供用于改变多芯片封装（MCP）的功能而不需要完全替换MCP的技术和装置。 MCP可以被设计成具有顶部封装衬底，其被设计为与由MCP接收的附加封装相连接，改变MCP的功能。

9. 发明授权

US07882324B2 Method and apparatus for synchronizing memory enabled systems with master-slave architecture 有权
标题翻译：用于使具有主从结构的存储器启用系统同步的方法和装置
公开(公告)号：US07882324B2
公开(公告)日：2011-02-01
申请号：US11928633
申请日：2007-10-30
申请人： Josef Schnell , Klaus Hummler , Jong Hoon Oh , Wayne Frederick Ellis , Jung Pill Kim , Oliver Kiehl , Octavian Beldiman , Lee Ward Collins
发明人： Josef Schnell , Klaus Hummler , Jong Hoon Oh , Wayne Frederick Ellis , Jung Pill Kim , Oliver Kiehl , Octavian Beldiman , Lee Ward Collins
IPC分类号： G06F12/00
CPC分类号： G06F13/1689 , G06F1/10 , G11C7/22 , G11C2207/2254
摘要： Embodiments of the invention generally provide a system, method and memory device for accessing memory. One embodiment includes synchronization circuitry configured to determine timing skew between a first memory device and a second memory device, and introduce a delta delay to at least one of the first memory device and the second memory device to adjust the timing skew.
摘要翻译：本发明的实施例通常提供用于访问存储器的系统，方法和存储器件。一个实施例包括被配置为确定第一存储器设备和第二存储器设备之间的定时偏差的同步电路，并且向第一存储器设备和第二存储器设备中的至少一个引入增量延迟以调整定时偏差。

10. 发明授权

US07688665B2 Structure to share internally generated voltages between chips in MCP 有权
标题翻译：结构可共享MCP内芯片之间内部产生的电压
公开(公告)号：US07688665B2
公开(公告)日：2010-03-30
申请号：US11860977
申请日：2007-09-25
申请人： Jung Pill Kim , Jong Hoon Oh , Oliver Kiehl , Josef Schnell , Klaus Hummler , Wayne Frederick Ellis , Octavian Beldiman , Lee Ward Collins
发明人： Jung Pill Kim , Jong Hoon Oh , Oliver Kiehl , Josef Schnell , Klaus Hummler , Wayne Frederick Ellis , Octavian Beldiman , Lee Ward Collins
IPC分类号： G11C5/14
CPC分类号： H01L23/5286 , H01L23/3128 , H01L23/50 , H01L25/0657 , H01L2924/0002 , H01L2924/15311 , H01L2924/00
摘要： Embodiments of the invention generally provide an apparatus and technique for sharing an internally generated voltage between devices of a multi-chip package (MCP). The internally generated voltage may be shared via a conductive structure that electrically couples the devices and carries the internally generated voltage.
摘要翻译：本发明的实施例通常提供用于在多芯片封装（MCP）的器件之间共享内部产生的电压的装置和技术。内部产生的电压可以通过电耦合器件并承载内部产生的电压的导电结构来共享。

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