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1. 发明授权

US07975170B2 Memory refresh system and method 有权
标题翻译：内存刷新系统和方法
公开(公告)号：US07975170B2
公开(公告)日：2011-07-05
申请号：US11763593
申请日：2007-06-15
申请人： Klaus Hummler , Jong Hoon Oh , Wayne Frederick Ellis , Jung Pill Kim , Oliver Kiehl , Josef Schnell , Octavian Beldiman , Lee Ward Collins
发明人： Klaus Hummler , Jong Hoon Oh , Wayne Frederick Ellis , Jung Pill Kim , Oliver Kiehl , Josef Schnell , Octavian Beldiman , Lee Ward Collins
IPC分类号： G06F11/00
CPC分类号： G11C29/02 , G11C7/1039 , G11C11/401 , G11C11/406 , G11C29/028 , G11C29/50016 , G11C2211/4062 , G11C2211/4065
摘要： A refresh scheduler is configured to refresh memory cells of a memory device according to a plurality of refresh intervals. The various refresh intervals are determined in response to refresh errors.
摘要翻译：刷新调度器被配置为根据多个刷新间隔刷新存储器设备的存储单元。响应于刷新错误确定各种刷新间隔。

2. 发明授权

US07721010B2 Method and apparatus for implementing memory enabled systems using master-slave architecture 有权
标题翻译：使用主 - 从体系结构实现启用内存的系统的方法和装置
公开(公告)号：US07721010B2
公开(公告)日：2010-05-18
申请号：US11930450
申请日：2007-10-31
申请人： Josef Schnell , Klaus Hummler , Jong Hoon Oh , Wayne Frederick Ellis , Jung Pill Kim , Oliver Kiehl , Octavian Beldiman , Lee Ward Collins
发明人： Josef Schnell , Klaus Hummler , Jong Hoon Oh , Wayne Frederick Ellis , Jung Pill Kim , Oliver Kiehl , Octavian Beldiman , Lee Ward Collins
IPC分类号： G06F12/00
CPC分类号： G11C7/10 , G11C7/1051 , G11C7/1063 , G11C7/1078 , G11C7/109
摘要： Embodiments of the invention generally provide a system, method, and memory device for accessing memory. In one embodiment, a first memory device includes command decoding logic configured to decode commands issued to the first memory device and a second memory device, while command decoding logic of the second memory device is bypassed.
摘要翻译：本发明的实施例通常提供用于访问存储器的系统，方法和存储器装置。在一个实施例中，第一存储器设备包括命令解码逻辑，其被配置为解码发出到第一存储器设备的命令和第二存储器设备，同时绕过第二存储器设备的命令解码逻辑。

3. 发明授权

US07694196B2 Self-diagnostic scheme for detecting errors 失效
标题翻译：用于检测错误的自诊断方案
公开(公告)号：US07694196B2
公开(公告)日：2010-04-06
申请号：US11943428
申请日：2007-11-20
申请人： Josef Schnell , Klaus Hummler , Jong Hoon Oh , Wayne Frederick Ellis , Jung Pill Kim , Oliver Kiehl , Octavian Beldiman , Lee Ward Collins
发明人： Josef Schnell , Klaus Hummler , Jong Hoon Oh , Wayne Frederick Ellis , Jung Pill Kim , Oliver Kiehl , Octavian Beldiman , Lee Ward Collins
IPC分类号： G11C29/00
CPC分类号： G11C5/04 , G11C29/44 , G11C29/789 , G11C2029/0401 , G11C2029/1208 , G11C2229/726 , G11C2229/743 , H01L25/0657 , H01L25/18 , H01L2924/0002 , H01L2924/15311 , H01L2924/00
摘要： The present invention is generally related to integrated circuit devices, and more particularly, to methods and systems of a multi-chip package (MCP) containing a self-diagnostic scheme for detecting errors in the MCP. The MCP generally comprises a controller, at least one volatile memory chip having error detection logic, at least one non-volatile memory chip, and at least one fail signature register for storing fail signature data related to memory errors detected in the MCP. The controller can poll the fail signature register for fail signature data related to memory errors stored therein. Upon detection of fail signature data, the controller can store the fail signature data on a fail signature register located on a non-volatile memory.
摘要翻译：本发明通常涉及集成电路器件，更具体地说，涉及包含用于检测MCP中的错误的自诊断方案的多芯片封装（MCP）的方法和系统。 MCP通常包括控制器，具有错误检测逻辑的至少一个易失性存储器芯片，至少一个非易失性存储器芯片以及用于存储与在MCP中检测到的存储器错误相关的失败签名数据的至少一个故障签名寄存器。控制器可以轮询失败签名寄存器以获取与其中存储的存储器错误有关的失败签名数据。在检测到失败签名数据时，控制器可以将故障签名数据存储在位于非易失性存储器上的故障签名寄存器上。

4. 发明申请

US20080313494A1 MEMORY REFRESH SYSTEM AND METHOD 有权
标题翻译：存储器刷新系统和方法
公开(公告)号：US20080313494A1
公开(公告)日：2008-12-18
申请号：US11763593
申请日：2007-06-15
申请人： Klaus Hummler , Jong Hoon Oh , Wayne Frederick Ellis , Jung Pill Kim , Oliver Kiehl , Josef Schnell , Octavian Beldiman , Lee Ward Collins
发明人： Klaus Hummler , Jong Hoon Oh , Wayne Frederick Ellis , Jung Pill Kim , Oliver Kiehl , Josef Schnell , Octavian Beldiman , Lee Ward Collins
IPC分类号： G06F11/16
CPC分类号： G11C29/02 , G11C7/1039 , G11C11/401 , G11C11/406 , G11C29/028 , G11C29/50016 , G11C2211/4062 , G11C2211/4065
摘要： A refresh scheduler is configured to refresh memory cells of a memory device according to a plurality of refresh intervals. The various refresh intervals are determined in response to refresh errors.
摘要翻译：刷新调度器被配置为根据多个刷新间隔刷新存储器设备的存储单元。响应于刷新错误确定各种刷新间隔。

5. 发明申请

US20080189480A1 Memory configured on a common substrate 有权
标题翻译：存储器配置在公共基板上
公开(公告)号：US20080189480A1
公开(公告)日：2008-08-07
申请号：US11701006
申请日：2007-02-01
申请人： Jung Pill Kim , Jong-Hoon Oh , Oliver Kiehl , Josef Schnell , Klaus Hummler , Wayne Ellis , Octavian Beldiman , Lee Collins
发明人： Jung Pill Kim , Jong-Hoon Oh , Oliver Kiehl , Josef Schnell , Klaus Hummler , Wayne Ellis , Octavian Beldiman , Lee Collins
IPC分类号： G06F12/00
CPC分类号： G11C5/04 , G11C5/063 , H01L2224/16225 , H01L2924/00011 , H01L2924/00014 , H01L2924/15192 , H01L2924/15311 , H05K1/181 , H01L2224/0401
摘要： A memory includes a first macro chip, a spine chip, and a common substrate. The common substrate is configured to pass signals between the first macro chip and the spine chip. The first macro chip, the spine chip, and the common substrate provide a memory.
摘要翻译：存储器包括第一宏芯片，脊芯片和公共基板。公共基板被配置为在第一宏芯片和脊芯片之间传递信号。第一个宏芯片，脊椎芯片和公共基板提供了一个记忆。

6. 发明授权

US06795010B1 Techniques for pausing and resuming analog-to-digital signal conversion 失效
标题翻译：暂停和恢复模数转换信号的技术
公开(公告)号：US06795010B1
公开(公告)日：2004-09-21
申请号：US10629390
申请日：2003-07-29
申请人： Yasho Potlapalli , Octavian Beldiman , Takashi Fujita
发明人： Yasho Potlapalli , Octavian Beldiman , Takashi Fujita
IPC分类号： H03M112
CPC分类号： H03M1/1225 , G06F3/05
摘要： Techniques are described for analog-to-digital signal conversion. According to exemplary embodiments, a first request is associated with a plurality of input terminals and a second request is associated with one of the input terminals. An analog signal presented at each of a portion of the input terminals associated with the first request is converted in succession into a digital value until the one of the input terminals associated with the second request is reached. A predetermined amount of time is waited to receive the second request. An analog signal presented at each of a remaining portion of the input terminals associated with the first request is converted in succession into a digital value when one of an expiration of the predetermined amount of time and a receiving of the second request occurs.
摘要翻译：描述了用于模数转换的技术。根据示例性实施例，第一请求与多个输入终端相关联，并且第二请求与输入终端之一相关联。在与第一请求相关联的输入端的一部分中的每一个处呈现的模拟信号被连续地转换为数字值，直到达到与第二请求相关联的输入端之一。等待预定时间量接收第二请求。当预定时间量的到期和第二个请求的接收发生之一时，呈现在与第一请求相关联的输入终端的剩余部分中的每一个处的模拟信号被连续地转换成数字值。

7. 发明申请

US20090200652A1 METHOD FOR STACKING CHIPS IN A MULTI-CHIP PACKAGE 有权
标题翻译：用于在多芯片封装中堆叠晶片的方法
公开(公告)号：US20090200652A1
公开(公告)日：2009-08-13
申请号：US12028542
申请日：2008-02-08
申请人： Jong Hoon Oh , Klaus Hummler , Oliver Kiehl , Josef Schnell , Wayne Frederick Ellis , Jung Pil Kim , Lee Ward Collins , Octavian Beldiman
发明人： Jong Hoon Oh , Klaus Hummler , Oliver Kiehl , Josef Schnell , Wayne Frederick Ellis , Jung Pil Kim , Lee Ward Collins , Octavian Beldiman
IPC分类号： H01L23/498 , H01L21/58
CPC分类号： H01L25/0657 , H01L25/03 , H01L25/18 , H01L2224/05568 , H01L2224/05573 , H01L2224/16145 , H01L2224/16225 , H01L2224/48091 , H01L2224/48227 , H01L2225/0651 , H01L2225/06513 , H01L2924/00014 , H01L2924/01079 , H01L2224/05599
摘要： A multi-chip package is provided that has at least a first, second and third chip, each comprising a top and bottom surface. The multi-chip package also has a package substrate for interfacing with a printed circuit board (PCB). The chips and the package substrate are housed within an encapsulation material. The bottom surface of the first chip is attached to the package substrate. The top surface of the first chip has a first plurality of landing pads, which serve as a mechanical and electrical interface between the first and second chip. The bottom surface of the second chip has a second plurality of landing pads that serve as a mechanical and electrical interface between the second and first chip. Additionally, the top surface of the second chip has a third plurality of landing pads that serve as a mechanical and electrical interface between the second and third chip.
摘要翻译：提供了具有至少第一，第二和第三芯片的多芯片封装，每个芯片包括顶部和底部表面。多芯片封装还具有用于与印刷电路板（PCB）连接的封装基板。芯片和封装衬底容纳在封装材料内。第一芯片的底表面附接到封装衬底。第一芯片的顶表面具有第一多个着陆焊盘，其用作第一和第二芯片之间的机械和电接口。第二芯片的底表面具有用作第二芯片和第一芯片之间的机械和电接口的第二多个着陆焊盘。此外，第二芯片的顶表面具有用作第二和第三芯片之间的机械和电接口的第三多个着陆焊盘。

8. 发明申请

US20090113158A1 METHOD AND APPARATUS FOR SYNCHRONIZING MEMORY ENABLED SYSTEMS WITH MASTER-SLAVE ARCHITECTURE 有权
标题翻译：用主同步架构同步存储器使能系统的方法和装置
公开(公告)号：US20090113158A1
公开(公告)日：2009-04-30
申请号：US11928633
申请日：2007-10-30
申请人： Josef Schnell , Klaus Hummler , Jong Hoon Oh , Wayne Frederick Ellis , Jung Pill Kim , Oliver Kiehl , Octavian Beldiman , Lee Ward Collins
发明人： Josef Schnell , Klaus Hummler , Jong Hoon Oh , Wayne Frederick Ellis , Jung Pill Kim , Oliver Kiehl , Octavian Beldiman , Lee Ward Collins
IPC分类号： G06F12/00
CPC分类号： G06F13/1689 , G06F1/10 , G11C7/22 , G11C2207/2254
摘要： Embodiments of the invention generally provide a system, method and memory device for accessing memory. One embodiment includes synchronization circuitry configured to determine timing skew between a first memory device and a second memory device, and introduce a delta delay to at least one of the first memory device and the second memory device to adjust the timing skew.
摘要翻译：本发明的实施例通常提供用于访问存储器的系统，方法和存储器件。一个实施例包括被配置为确定第一存储器设备和第二存储器设备之间的定时偏差的同步电路，并且向第一存储器设备和第二存储器设备中的至少一个引入增量延迟以调整定时偏差。

9. 发明申请

US20090080279A1 STRUCTURE TO SHARE INTERNALLY GENERATED VOLTAGES BETWEEN CHIPS IN MCP 有权
标题翻译：在MCP中分配内部电压之间的结构
公开(公告)号：US20090080279A1
公开(公告)日：2009-03-26
申请号：US11860977
申请日：2007-09-25
申请人： JUNG PILL KIM , Jong Hoon Oh , Oliver Kiehl , Josef Schnell , Klaus Hummler , Wayne Frederick Ellis , Octavian Beldiman , Lee Ward Collins
发明人： JUNG PILL KIM , Jong Hoon Oh , Oliver Kiehl , Josef Schnell , Klaus Hummler , Wayne Frederick Ellis , Octavian Beldiman , Lee Ward Collins
IPC分类号： G11C5/14 , H01L23/538
CPC分类号： H01L23/5286 , H01L23/3128 , H01L23/50 , H01L25/0657 , H01L2924/0002 , H01L2924/15311 , H01L2924/00
摘要： Embodiments of the invention generally provide an apparatus and technique for sharing an internally generated voltage between devices of a multi-chip package (MCP). The internally generated voltage may be shared via a conductive structure that electrically couples the devices and carries the internally generated voltage.
摘要翻译：本发明的实施例通常提供用于在多芯片封装（MCP）的器件之间共享内部产生的电压的装置和技术。内部产生的电压可以通过电耦合器件并承载内部产生的电压的导电结构来共享。

10. 发明授权

US07142146B2 Method and system for reducing interference between analog circuits operating from a common power supply 有权
标题翻译：用于减少从公共电源工作的模拟电路之间的干扰的方法和系统
公开(公告)号：US07142146B2
公开(公告)日：2006-11-28
申请号：US11187239
申请日：2005-07-22
申请人： Yashovardhan R. Potlapalli , Octavian Beldiman
发明人： Yashovardhan R. Potlapalli , Octavian Beldiman
IPC分类号： H03M1/12
CPC分类号： H03M1/0845
摘要： In a system having multiple analog circuits that share a common power supply, where a change in the operational state of one circuit can have an effect on the performance of another circuit, a determination is made when any one of the circuits enters a state where its performance could be affected. Under such a condition, the other circuits that share the common power supply are placed in a state where their effect on the operation of the first circuit will be negligible. This state for the other circuits can be one of maximum current draw, so that subsequent operation by the other circuits will not alter the demands on the power supply.
摘要翻译：在具有共享公共电源的多个模拟电路的系统中，其中一个电路的操作状态的改变可以对另一个电路的性能产生影响，当任何一个电路进入其中表现可能会受到影响。在这种情况下，共享公共电源的其他电路被置于其对第一电路的操作的影响可以忽略的状态。其他电路的这种状态可以是最大电流消耗之一，因此其他电路的后续操作不会改变对电源的要求。

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