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1. 发明申请

US20070109721A1 Coin-shaped storage cell 有权
标题翻译：硬币存储单元
公开(公告)号：US20070109721A1
公开(公告)日：2007-05-17
申请号：US10581339
申请日：2004-12-02
申请人： Masayuki Sato , Masashige Ashizaki , Koichi Morikawa , Isamu Nishiyama , Nario Niibo , Masayuki Taniguchi
发明人： Masayuki Sato , Masashige Ashizaki , Koichi Morikawa , Isamu Nishiyama , Nario Niibo , Masayuki Taniguchi
IPC分类号： H01G9/00
CPC分类号： H01G9/10 , H01G9/08 , H01G9/155 , H01M2/0222 , H01M2/0413 , Y02E60/13
摘要： A coin-shaped storage cell (1) has a pair of polarizable electrodes (17, 18), an insulating separator (21) interposed between the polarizable electrodes, an electrolytic solution (22) impregnated in the polarizable electrodes (17, 18) and the separator (21), a metal case (11) for housing the polarizable electrodes (17, 18), an insulating ring packing (15) arranged in the metal case, and a top lid (13) which is caulked integrally with the metal case (11) via the ring packing (15). The inner bottom surface of the metal case (11) is provided with recessed and projected portions.
摘要翻译：硬币形存储单元（1）具有一对可极化电极（17,18），插入在可极化电极之间的绝缘隔板（21），浸渍在可极化电极（17,18）中的电解液（22）和分离器（21），用于容纳可极化电极（17,18）的金属壳体（11），布置在金属壳体中的绝缘环填料（15）和与金属一体地铆接的顶盖（13）（11）通过环形包装（15）。金属壳体（11）的内底表面设有凹入和突出部分。

2. 发明申请

US20050058002A1 Multi-port semiconductor memory 有权
标题翻译：多端口半导体存储器
公开(公告)号：US20050058002A1
公开(公告)日：2005-03-17
申请号：US10779780
申请日：2004-02-18
申请人： Koichi Morikawa
发明人： Koichi Morikawa
IPC分类号： G11C11/41 , G11C7/18 , G11C8/00 , G11C8/16
CPC分类号： G11C8/16 , G11C7/18
摘要： A multi-port semiconductor memory in which wrong read-out due to coupling noise is hardly generated and operation speed is fast is provided. When data are written in memory cells from a pair of bit lines for one port, NMOS transistors become on. Electrical potential only at a low-level side is pulled up between the pair of bit lines, because electrical potential at a high-level side is approximately equivalent to power potential. Accordingly, when one of adjacent bit lines is on high-level and the other is on low-level, potential difference is reduced by the pull-up, resulting in reduction of generating time of the coupling noise. Although read-out of data can not be performed while the coupling noise is being generated, since the concerned generating time is reduced in the invention, the operation speed is substantially fast.
摘要翻译：其中几乎不产生由于耦合噪声而导致读出错误的多端口半导体存储器，并且提供了操作速度快的多端口半导体存储器。当数据从一个端口的一对位线写入存储单元时，NMOS晶体管导通。由于高电平侧的电位大致等于功率电位，所以仅在低电平侧的电位才被提升在一对位线之间。因此，当相邻位线中的一个位于高电平并且另一个位于低电平时，由于上拉而电位差减小，导致耦合噪声的产生时间的减少。虽然在产生耦合噪声的同时读出数据是不可执行的，但由于在本发明中减少了相关的生成时间，因此操作速度基本上是快的。

3. 发明授权

US06836175B2 Semiconductor integrated circuit with sleep memory 失效
公开(公告)号：US06836175B2
公开(公告)日：2004-12-28
申请号：US10638304
申请日：2003-08-12
申请人： Koichi Morikawa
发明人： Koichi Morikawa
IPC分类号： H03K301
CPC分类号： H03K19/0016 , G11C5/063 , H02J9/005
摘要： A semiconductor integrated circuit operating in an active state and a sleep state has a power line that is branched through a first transistor to a first virtual power line and through a second transistor to a second virtual power line. The first transistor is switched on in the active state and off in the sleep state; the second transistor is switched off in the active state and on in the sleep state. The first virtual power line powers logic circuits. The second power line powers a memory circuit that stores necessary logic-circuit signal levels during the sleep state. The memory circuit does not consume power in the active state.

4. 发明授权

US6118328A Semiconductor integrated circuit having virtual power supply line and power control transistor 有权
标题翻译：具有虚拟电源线和功率控制晶体管的半导体集成电路
公开(公告)号：US6118328A
公开(公告)日：2000-09-12
申请号：US144433
申请日：1998-09-01
申请人： Koichi Morikawa
发明人： Koichi Morikawa
IPC分类号： H01L21/8238 , G11C11/407 , H01L27/092 , H03K19/00 , H03K19/096 , H03K3/01
CPC分类号： H03K19/0016
摘要： The invention intends to provide a semiconductor integrated circuit including MOS transistors, which is able to operate at a high-speed with a low power supply voltage in the active mode, and to reduce the power consumption resulting from the leakage current in the standby mode.In view of the foregoing object, the semiconductor integrated circuit of the invention is comprised of a first power supply line to which a first power supply potential is supplied, a virtual power supply line, a logic circuit connected to the virtual power supply line, a power control transistor provided between the first power supply line and the virtual power supply line, having a control electrode to which a first control signal is inputted, a second power supply line to which a second power supply potential is supplied, and a substrate potential control circuit connected to a substrate on which the power control transistor is formed, the first power supply line, and the second power supply line.
摘要翻译：本发明旨在提供一种包括MOS晶体管的半导体集成电路，其能够以活动模式中的低电源电压以高速运行，并且降低由待机模式中的漏电流引起的功耗。鉴于上述目的，本发明的半导体集成电路包括：供给第一电源电位的第一电源线，虚拟电源线，连接到虚拟电源线的逻辑电路，设置在第一电源线和虚拟电源线之间的功率控制晶体管，具有输入第一控制信号的控制电极，提供第二电源电位的第二电源线，以及基板电位控制连接到其上形成有功率控制晶体管的基板，第一电源线和第二电源线。

5. 发明授权

US08420255B2 Storage cell and method of manufacturing same 有权
标题翻译：储存池及其制造方法
公开(公告)号：US08420255B2
公开(公告)日：2013-04-16
申请号：US12373979
申请日：2007-08-03
申请人： Koichi Morikawa , Shinji Nakano , Nario Niibo , Yukio Nishioka , Masayuki Sato , Masashige Ashizaki
发明人： Koichi Morikawa , Shinji Nakano , Nario Niibo , Yukio Nishioka , Masayuki Sato , Masashige Ashizaki
IPC分类号： H01M2/30
CPC分类号： H01M2/021 , H01G9/016 , H01G9/08 , H01G9/155 , H01G11/52 , H01G11/74 , H01G11/80 , H01G11/84 , H01M2/0212 , H01M2/0275 , H01M2/0277 , H01M2/30 , H01M10/0436 , Y02E60/13 , Y10T29/4911
摘要： A storage cell includes a storage element including first and second electrodes which are opposite to each other in a predetermined direction, a first terminal bonded to the first electrode, a second terminal bonded to the second electrode, and an outer resin covering the storage element to expose an outer surface of the first terminal and an outer surface of the second terminal from the outer resin. The storage element has substantially a rectangular shape viewing from the predetermined direction. The outer resin has substantially a rectangular shape viewing from the predetermined direction. The outer resin has first and second surfaces opposite to each other, and has a third surface connected with the first surface and the second surface. The first terminal is exposed on the first surface of the outer resin. The second terminal has a shape extending beyond the storage element along the first and third surfaces, and is exposed on the first surface. This storage cell has a small size, a large capacitance, and high reliability.
摘要翻译：存储单元包括存储元件，其包括在预定方向上彼此相对的第一和第二电极，接合到第一电极的第一端子，接合到第二电极的第二端子和覆盖存储元件的外部树脂，从外树脂露出第一端子的外表面和第二端子的外表面。存储元件具有从预定方向观察的基本上矩形形状。外部树脂具有从预定方向观察的大致矩形形状。外部树脂具有彼此相对的第一和第二表面，并且具有与第一表面和第二表面连接的第三表面。第一端子暴露在外部树脂的第一表面上。第二端子具有沿着第一和第三表面延伸超过存储元件的形状，并且暴露在第一表面上。该存储单元具有体积小，电容大，可靠性高的特点。

6. 发明申请

US20090181297A1 STORAGE CELL 审中-公开
标题翻译：存储单元
公开(公告)号：US20090181297A1
公开(公告)日：2009-07-16
申请号：US12347168
申请日：2008-12-31
申请人： Masashige Ashizaki , Masayuki Sato , Koichi Morikawa , Nario Niibo
发明人： Masashige Ashizaki , Masayuki Sato , Koichi Morikawa , Nario Niibo
IPC分类号： H01M2/26
CPC分类号： H01G9/155 , H01G9/016 , H01G9/10 , H01G11/74 , H01G11/78 , H01G11/80 , H01M2/0207 , H01M2/0267 , H01M2/0275 , H01M2/0285 , H01M2/08 , H01M2/1061 , Y02E60/13
摘要： A storage cell includes a storage element, a first case having a first flat portion contacting an upper surface of the storage element and having a rectangular shape, a second case having a second flat portion contacting a lower surface of the storage element and having a rectangular shape, a gasket allowing the storage element to be accommodated between the first case and the second case, first and second terminal plates joined to the first and second cases, respectively, a first sealing resin for sealing the first case and the gasket, a second sealing resin for sealing the second case and the gasket, and a package resin covering the above components. The gasket has a rectangular frame shape, and has a cross section having substantially an H-shape. Edges of the first and second cases are inserted in recesses in the gasket and sealed with the first and second sealing resins, respectively. This storage cell has a high withstanding temperature and reduces an area having the cell mounted thereto.
摘要翻译：存储单元包括存储元件，第一壳体具有与存储元件的上表面接触并具有矩形形状的第一平坦部分，第二壳体，具有与存储元件的下表面接触的第二平坦部分，并且具有矩形形状，允许存储元件容纳在第一壳体和第二壳体之间的垫圈，分别连接到第一壳体和第二壳体的第一和第二端子板，用于密封第一壳体和垫圈的第一密封树脂，第二壳体用于密封第二壳体和垫圈的密封树脂，以及覆盖上述部件的封装树脂。垫圈具有矩形框架形状，并且具有大致H形的横截面。第一和第二壳体的边缘插入垫圈中的凹槽中并分别用第一和第二密封树脂密封。该存储单元具有高的耐受温度并且减小了安装有单元的区域。

7. 发明授权

US07515395B2 Material of case for storage cell 有权
标题翻译：储存盒的材料
公开(公告)号：US07515395B2
公开(公告)日：2009-04-07
申请号：US10577342
申请日：2004-12-15
申请人： Koichi Morikawa , Masashige Ashizaki , Eri Hirose , Yutaka Kobayashi
发明人： Koichi Morikawa , Masashige Ashizaki , Eri Hirose , Yutaka Kobayashi
IPC分类号： H01G2/10 , H01G9/08
CPC分类号： C22C38/001 , C21D6/001 , C21D6/002 , C21D2211/001 , C22C38/02 , C22C38/04 , C22C38/44 , H01M2/0275 , H01M2/0285
摘要： There is provided a casing material for a storage cell having sufficient corrosion resistance and strength even under a charging environment of a high voltage exceeding 2.8 V. This casing material for the storage cell comprises C: not more than 0.03 mass %, Si: 0.01-0.50 mass %, Mn: not more than 0.20 mass %, P: not more than 0.04 mass %, S: not more than 0.0010 mass %, Ni: 20.0-40.0 mass %, Cr: 20.0-30.0 mass %, Mo: 5.0-10.0 mass %, Al: 0.001-0.10 mass %, N: 0.10-0.50 mass %, Ca: not more than 0.001 mass %, Mg: 0.0001-0.0050 mass %, 0: not more than 0.005 mass %, provided that contents of Cr, Mo and N satisfy Cr+3.3×Mo+20×N≧43, and the balance being substantially Fe and inevitable impurities, in which a content of CaO as an oxide inclusion in steel is not more than 20 mass %.
摘要翻译：即使在超过2.8V的高电压的充电环境下，也提供了具有足够的耐腐蚀性和强度的蓄电池的外壳材料。该蓄电池用外壳材料包括C：0.03质量％以下，Si：0.01〜 0.50质量％，Mn：0.20质量％以下，P：0.04质量％以下S：0.0010质量％以下Ni：20.0〜40.0质量％Cr：20.0〜30.0质量％Mo：5.0 -10.0质量％，Al：0.001-0.10质量％，N：0.10〜0.50质量％，Ca：0.001质量％以下，Mg：0.0001-0.0050质量％，0：0.005质量％以下，的Cr，Mo和N满足Cr + 3.3xMo + 20xN> = 43，余量实质上为Fe和不可避免的杂质，其中钢中作为氧化物夹杂物的CaO含量不超过20质量％。

8. 发明授权

US07170814B2 Multi-port semiconductor memory 有权
公开(公告)号：US07170814B2
公开(公告)日：2007-01-30
申请号：US10779780
申请日：2004-02-18
申请人： Koichi Morikawa
发明人： Koichi Morikawa
IPC分类号： G11C8/00 , G11C11/00 , G11C7/10
CPC分类号： G11C8/16 , G11C7/18
摘要： A multi-port semiconductor memory in which wrong read-out due to coupling noise is hardly generated and operation speed is fast is provided. When data are written in memory cells from a pair of bit lines for one port, NMOS transistors become on. Electrical potential only at a low-level side is pulled up between the pair of bit lines, because electrical potential at a high-level side is approximately equivalent to power potential. Accordingly, when one of adjacent bit lines is on high-level and the other is on low-level, potential difference is reduced by the pull-up, resulting in reduction of generating time of the coupling noise. Although read-out of data can not be performed while the coupling noise is being generated, since the concerned generating time is reduced in the invention, the operation speed is substantially fast.

9. 发明授权

US06747886B1 Content addressable memory with shifted enable signal 失效
标题翻译：内容可寻址存储器，具有移位的使能信号
公开(公告)号：US06747886B1
公开(公告)日：2004-06-08
申请号：US10401743
申请日：2003-03-31
申请人： Koichi Morikawa
发明人： Koichi Morikawa
IPC分类号： G11C1500
CPC分类号： G11C15/04 , G11C15/00
摘要： A content addressable memory includes a seek access circuit with four transistors connected in series between a pair of bit lines. The two inner transistors are driven by a data storage circuit; the outer two transistors function as enable transistors. A level shifting circuit receives an enable signal and shifts one or both of the logic levels of the enable signal so as to widen the potential difference between them. The shifted enable signal drives the enable transistors in the seek access circuit. Shifting the high logic level of the enable signal upward speeds up seek access by reducing the on-resistance of the enable transistors. Shifting the low logic level of the enable signal downward reduces subthreshold leakage through the seek access circuit, thereby reducing current consumption, speeding up read and write access, and preventing access errors.
摘要翻译：内容可寻址存储器包括具有串联连接在一对位线之间的四个晶体管的寻道存取电路。两个内部晶体管由数据存储电路驱动; 外部两个晶体管用作启用晶体管。电平移位电路接收使能信号并移位使能信号的逻辑电平中的一个或两者，以便扩大它们之间的电位差。移位的使能信号驱动寻道存取电路中的使能晶体管。通过降低启用晶体管的导通电阻，使启动信号的高逻辑电平向上移动可以加快寻道访问。向下移动使能信号的低逻辑电平可以降低通过寻道存取电路的次阈值泄漏，从而减少电流消耗，加速读写访问，并防止访问错误。

10. 发明授权

US06570811B1 Writing operation control circuit and semiconductor memory using the same 失效
标题翻译：写操作控制电路和使用其的半导体存储器
公开(公告)号：US06570811B1
公开(公告)日：2003-05-27
申请号：US10115003
申请日：2002-04-04
申请人： Koichi Morikawa
发明人： Koichi Morikawa
IPC分类号： G11C800
CPC分类号： G11C11/419
摘要： A writing operation control circuit for a semiconductor memory includes a driving circuit which operates to perform a writing operation in response to a writing data signal, the driving circuit having a specific threshold voltage; a first voltage control circuit which selectively outputs first and second supply voltages to the driving circuit in response to a logical level of a write controlling signal; and a second voltage control circuit which selectively outputs third and fourth supply voltages to the driving circuit in response to a logical level of the write controlling signal. The second supply voltage is higher than the first supply voltage, the first supply voltage is higher than the fourth supply voltage, and the fourth supply voltage is higher than the third supply voltage.
摘要翻译：一种用于半导体存储器的写入操作控制电路包括驱动电路，其操作以响应写入数据信号执行写入操作，该驱动电路具有特定的阈值电压; 第一电压控制电路，其响应于写入控制信号的逻辑电平选择性地向驱动电路输出第一和第二电源电压; 以及第二电压控制电路，其响应于写入控制信号的逻辑电平选择性地向驱动电路输出第三和第四电源电压。第二电源电压高于第一电源电压，第一电源电压高于第四电源电压，第四电源电压高于第三电源电压。

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