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    • 1. 发明授权
    • Programming memory cells using smaller step voltages for higher program levels
    • 使用更小的步进电压编程存储器单元以实现更高的程序级
    • US08737131B2
    • 2014-05-27
    • US13305795
    • 2011-11-29
    • Koji Sakui
    • Koji Sakui
    • G11C11/34
    • G11C16/10G11C11/5628G11C16/0483G11C16/3427
    • Memory devices and methods are disclosed. An embodiment of one such method includes programming a first memory cell to a first program level by applying a first series of programming pulses to a control gate of the first memory cell, where the programming pulses of the first series have voltages that sequentially increase by a certain first voltage; and programming a second memory cell to a second program level that is higher than the first program level by applying a second series of programming pulses to a control gate of the second memory cell, where the programming pulses of the second series have voltages that sequentially increase by a certain second voltage less than the certain first voltage.
    • 公开了存储器件和方法。 一种这样的方法的实施例包括通过将第一系列编程脉冲施加到第一存储器单元的控制栅极来将第一存储器单元编程为第一程序级,其中第一系列的编程脉冲具有依次增加的电压 一定的第一电压; 以及通过将第二系列编程脉冲施加到所述第二存储器单元的控制栅极来将第二存储器单元编程为高于所述第一编程电平的第二编程电平,其中所述第二系列的编程脉冲具有顺序增加的电压 通过一定的第二电压小于一定的第一电压。
    • 2. 发明申请
    • PARTIAL BLOCK MEMORY OPERATIONS
    • 部分块存储器操作
    • US20140036590A1
    • 2014-02-06
    • US13564458
    • 2012-08-01
    • Peter Sean FeeleyKoji SakuiAkira Goda
    • Peter Sean FeeleyKoji SakuiAkira Goda
    • G11C16/04
    • Methods and apparatuses are disclosed, such as those including a block of memory cells that includes strings of charge storage devices. Each of the strings may comprise a plurality of charge storage devices formed in a plurality of tiers. The apparatus may comprise a plurality of access lines shared by the strings. Each of the plurality of access lines may be coupled to the charge storage devices corresponding to a respective tier of the plurality of tiers. The apparatus may comprise a plurality of sub-sources associated with the strings. Each of the plurality of sub-sources may be coupled to a source select gate of each string of a respective subset of a plurality of subsets of the strings, and each sub-source may be independently selectable from other sub-sources to select the strings of its respective subset independently of other strings corresponding to other subsets.
    • 公开了诸如包括包含电荷存储装置串的存储器单元块的方法和装置。 每个串可以包括以多层形成的多个电荷存储装置。 该装置可以包括由串共享的多个接入线。 多个接入线路中的每一个可以耦合到与多个层级的相应层对应的电荷存储装置。 该装置可以包括与弦相关联的多个子源。 多个子源中的每一个可以耦合到字符串的多个子集的相应子集的每个串的源选择门,并且每个子源可以独立地从其他子源中选择以选择字符串 独立于对应于其他子集的其他字符串。
    • 5. 发明申请
    • PROGRAMMING MEMORY CELLS USING SMALLER STEP VOLTAGES FOR HIGHER PROGRAM LEVELS
    • 使用较小程序级电压编程存储器电池
    • US20130135937A1
    • 2013-05-30
    • US13305795
    • 2011-11-29
    • Koji Sakui
    • Koji Sakui
    • G11C16/10
    • G11C16/10G11C11/5628G11C16/0483G11C16/3427
    • Memory devices and methods are disclosed. An embodiment of one such method includes programming a first memory cell to a first program level by applying a first series of programming pulses to a control gate of the first memory cell, where the programming pulses of the first series have voltages that sequentially increase by a certain first voltage; and programming a second memory cell to a second program level that is higher than the first program level by applying a second series of programming pulses to a control gate of the second memory cell, where the programming pulses of the second series have voltages that sequentially increase by a certain second voltage less than the certain first voltage.
    • 公开了存储装置和方法。 一种这样的方法的实施例包括通过将第一系列编程脉冲施加到第一存储器单元的控制栅极来将第一存储器单元编程为第一程序级,其中第一系列的编程脉冲具有依次增加的电压 一定的第一电压; 以及通过将第二系列编程脉冲施加到所述第二存储器单元的控制栅极来将第二存储器单元编程为高于所述第一编程电平的第二编程电平,其中所述第二系列的编程脉冲具有顺序增加的电压 通过一定的第二电压小于一定的第一电压。
    • 7. 发明申请
    • Nonvolatile Semiconductor Storage Device and Operation Method Thereof
    • 非易失性半导体存储器件及其操作方法
    • US20080192549A1
    • 2008-08-14
    • US11815387
    • 2006-02-03
    • Michio NakagawaKoji Sakui
    • Michio NakagawaKoji Sakui
    • G11C16/12
    • G11C16/12G11C16/3468
    • To provide a nonvolatile semiconductor storage device and a drive method thereof capable of preventing lowering efficiency of write or erase operation and reducing the write time and the erase time. [MEANS FOR SOLVING PROBLEMS] A nonvolatile semiconductor storage device includes an electrically rewritable memory cell formed by a floating gate and a control gate layered on a semiconductor layer. The nonvolatile semiconductor storage device applies a plurality of threshold value fluctuation pulses having a stepwise high potential to the memory cell and then detects a threshold value of the memory cell. When the threshold value of the memory cell is not a predetermined value, a plurality of threshold value fluctuation pulses having stepwise high potential are applied to the memory cell from a potential of the lastly applied threshold value fluctuation pulse, among the plurality of threshold value fluctuation pulses, to which a certain potential is added.
    • 提供一种能够防止写入或擦除操作的降低效率并减少写入时间和擦除时间的非易失性半导体存储器件及其驱动方法。 解决问题的手段非易失性半导体存储装置包括由浮置栅极和层叠在半导体层上的控制栅极形成的电可重写存储单元。 非易失性半导体存储装置向存储单元施加具有逐级高电位的多个阈值波动脉冲,然后检测存储单元的阈值。 当存储单元的阈值不是预定值时,具有逐步高电位的多个阈值波动脉冲从最近施加的阈值波动脉冲的电位在多个阈值波动之中被施加到存储单元 脉冲,添加一定的电位。
    • 8. 发明授权
    • Non-volatile semiconductor storage apparatus
    • 非易失性半导体存储装置
    • US07362614B2
    • 2008-04-22
    • US11529272
    • 2006-09-29
    • Koji SakuiKazuhiro Suzuki
    • Koji SakuiKazuhiro Suzuki
    • G11C11/34
    • G11C16/0483
    • A non-volatile semiconductor storage apparatus includes a memory cell array including at least one memory cell unit in which multiple electrically rewritable non-volatile memory cells are serially connected, multiple control gate lines connecting to a control terminal for the multiple memory cells, a bit line connecting to the memory cell unit, means for selecting the control gate line, means for selecting the bit line, an externally input single power supply terminal, and an externally input ground potential terminal. In this case, the voltage equal to or lower than the voltage of the externally input single power supply is applied to the control gate line in reading out stored data in the memory cells.
    • 非易失性半导体存储装置包括存储单元阵列,其包括至少一个存储单元单元,其中多个电可重写非易失性存储单元串联连接,连接到多个存储器单元的控制端的多个控制栅极线, 连接到存储单元单元的线路,用于选择控制栅极线的装置,用于选择位线的装置,外部输入的单个电源端子和外部输入的接地电位端子。 在这种情况下,等于或低于外部输入单个电源的电压的电压在读出存储单元中存储的数据时被施加到控制栅极线。