专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08503235B2 Nonvolatile memory with faulty cell registration 失效
标题翻译：具有故障单元注册的非易失性存储器
公开(公告)号：US08503235B2
公开(公告)日：2013-08-06
申请号：US13298548
申请日：2011-11-17
申请人： Kunihiro Katayama , Takayuki Tamura , Satoshi Watatani , Kiyoshi Inoue , Shigemasa Shiota , Masashi Naito
发明人： Kunihiro Katayama , Takayuki Tamura , Satoshi Watatani , Kiyoshi Inoue , Shigemasa Shiota , Masashi Naito
IPC分类号： G11C11/34 , G11C11/29
CPC分类号： G11C16/349 , G11C29/76 , G11C29/88
摘要： In response to a read command received by a system interface unit for accessing a plurality of blocks of data stored in said non-volatile semiconductor memory, a controller carries out selective read operations of blocks of data to two memories from the non-volatile semiconductor memory. The controller also carries out parallel operations of data transferring a first block of data, which has already been subjected to error detection and error correction operations by an error correction unit, from one of the two memories to a host system via said system interface unit and of data transferring of a second block of data to be subjected to the error detection and error correction operation, from said non-volatile semiconductor memory to the other of the two memories.
摘要翻译：响应于由用于访问存储在所述非易失性半导体存储器中的多个数据块的系统接口单元接收到的读取命令，控制器对来自非易失性半导体存储器的两个存储器执行数据块的选择性读取操作。所述控制器还执行数据的并行操作，所述数据传输已经经过错误校正单元的错误检测和纠错操作的第一数据块经由所述系统接口单元从所述两个存储器之一传送到主机系统，并且将要进行错误检测和纠错操作的第二数据块的数据传输从所述非易失性半导体存储器传输到两个存储器中的另一个。

2. 发明授权

US08331153B2 Semiconductor memory having electrically erasable and programmable semiconductor memory cells 有权
标题翻译：具有电可擦除和可编程的半导体存储器单元的半导体存储器
公开(公告)号：US08331153B2
公开(公告)日：2012-12-11
申请号：US13363400
申请日：2012-02-01
申请人： Kunihiro Katayama , Takayuki Tamura , Kiyoshi Inoue
发明人： Kunihiro Katayama , Takayuki Tamura , Kiyoshi Inoue
IPC分类号： G11C16/04
CPC分类号： G11C16/28 , G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C16/10 , G11C16/30 , G11C2211/5621 , G11C2211/5632 , G11C2211/5634 , G11C2211/5641 , G11C2211/5642
摘要： In a nonvolatile memory apparatus, a system bus receives address, command, and/or control signals. Memory cells store bits of data by shifting a threshold voltage to one of plural ranges. In writing a first page, the threshold voltage of a first memory cell remains in a first range or shifts into a second range. In writing a second page, the threshold voltage remains in the first or second voltages, or shifts into a third range from the first range or into a fourth range from the second range. Before writing the second page, the memory reads data from the first memory cell for generating the second page writing data. A shifting direction of the threshold voltage from the first to the second range is the same as a shifting direction from the first to the third range.
摘要翻译：在非易失性存储装置中，系统总线接收地址，命令和/或控制信号。存储单元通过将阈值电压移位到多个范围之一来存储数据位。在写入第一页时，第一存储器单元的阈值电压保持在第一范围或者移位到第二范围。在写第二页时，阈值电压保持在第一或第二电压中，或者从第二范围移动到从第一范围到第四范围的第三范围。在写入第二页之前，存储器从第一存储器单元读取用于生成第二页写入数据的数据。从第一到第二范围的阈值电压的移动方向与从第一到第三范围的移动方向相同。

3. 发明申请

US20100177579A1 SEMICONDUCTOR MEMORY DEVICE HAVING FAULTY CELLS 有权
标题翻译：具有故障细胞的半导体存储器件
公开(公告)号：US20100177579A1
公开(公告)日：2010-07-15
申请号：US12615502
申请日：2009-11-10
申请人： Kunihiro Katayama , Takayuki Tamura , Satoshi Watatani , Kiyoshi Inoue , Shigemasa Shiota , Masashi Naito
发明人： Kunihiro Katayama , Takayuki Tamura , Satoshi Watatani , Kiyoshi Inoue , Shigemasa Shiota , Masashi Naito
IPC分类号： G11C29/04
CPC分类号： G11C16/349 , G11C29/76 , G11C29/88
摘要： In response to a read command received by a system interface unit for accessing a plurality of blocks of data stored in said non-volatile semiconductor memory, a controller carries out selective read operations of blocks of data to two memories from the non-volatile semiconductor memory. The controller also carries out parallel operations of data transferring a first block of data, which has already been subjected to error detection and error correction operations by an error correction unit, from one of the two memories to a host system via said system interface unit and of data transferring of a second block of data to be subjected to the error detection and error correction operation, from said non-volatile semiconductor memory to the other of the two memories.
摘要翻译：响应于由用于访问存储在所述非易失性半导体存储器中的多个数据块的系统接口单元接收到的读取命令，控制器对来自非易失性半导体存储器的两个存储器执行数据块的选择性读取操作。所述控制器还执行数据的并行操作，所述数据传输已经经过错误校正单元的错误检测和纠错操作的第一数据块经由所述系统接口单元从所述两个存储器之一传送到主机系统，并且将要进行错误检测和纠错操作的第二数据块的数据传输从所述非易失性半导体存储器传输到两个存储器中的另一个。

4. 发明授权

US07570515B2 Semiconductor memory having electrically erasable and programmable semiconductor memory cells 失效
标题翻译：具有电可擦除和可编程的半导体存储器单元的半导体存储器
公开(公告)号：US07570515B2
公开(公告)日：2009-08-04
申请号：US11870196
申请日：2007-10-10
申请人： Kunihiro Katayama , Takayuki Tamura , Kiyoshi Inoue
发明人： Kunihiro Katayama , Takayuki Tamura , Kiyoshi Inoue
IPC分类号： G11C16/04
CPC分类号： G11C16/28 , G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C16/10 , G11C16/30 , G11C2211/5621 , G11C2211/5632 , G11C2211/5634 , G11C2211/5641 , G11C2211/5642
摘要： An electrically alterable non-volatile multi-level memory device and a method of operating such a device, which includes setting a status of at least one of the memory cells to one state selected from a plurality of states including at least first to fourth level states, in response to information to be stored in the one memory cell, and reading the status of the memory cell to determine whether the read out status corresponds to one of the first to fourth level states by utilizing a first reference level set between the second and third level states, a second reference level set between the first and second level states and a third reference level set between the third and fourth level states.
摘要翻译：一种可电气可变的非易失性多级存储器件和操作这种器件的方法，其包括将至少一个存储器单元的状态设置为从包括至少第一至第四电平状态的多个状态中选择的一种状态响应于要存储在一个存储器单元中的信息，并且通过利用在第二和第二电平状态之间设置的第一参考电平来读取存储单元的状态来确定读出状态是否对应于第一至第四电平状态之一第三电平状态，在第一和第二电平状态之间设置的第二参考电平和在第三和第四电平状态之间设置的第三参考电平。

5. 发明申请

US20090187703A1 MEMORY CARD AND ITS INITIAL SETTING METHOD 有权
标题翻译：记忆卡及其初始设置方法
公开(公告)号：US20090187703A1
公开(公告)日：2009-07-23
申请号：US12412117
申请日：2009-03-26
申请人： HIDEFUMI OODATE , Atsushi Shiraishi , Shigeo Kurakata , Kunihiro Katayama , Motoki Kanamori
发明人： HIDEFUMI OODATE , Atsushi Shiraishi , Shigeo Kurakata , Kunihiro Katayama , Motoki Kanamori
IPC分类号： G06F12/02 , G06F12/00 , G11C5/14
CPC分类号： G11C16/20
摘要： In the initial setting of a memory card 1, the flash check data FD stored in a flash memory 2 is read out, this data FD is compared with the operation check data FD11 stored previously in the ROM, the write check data FD12 stored in the ROM 4a is written, if a fault is not detected, to the flash memory 2, and this data is read again and is compared with the write check data. FD12 of the ROM 4a. When any fault is not detected in comparison of these data, the CPU determines that the flash memory 2 is normal. Moreover, if a fault is detected in the comparison of data, the CPU sets the reset process fault data to a register 5a to set a controller 3 to the sleep mode. When the command CMD is received during this period, data comparison is executed again.
摘要翻译：在存储卡1的初始设置中，读出存储在闪速存储器2中的闪存检查数据FD，将该数据FD与先前存储在ROM中的操作检查数据FD11进行比较，存储在存储卡1中的写入检查数据FD12 如果没有检测到故障，ROM 4a被写入闪速存储器2，并且该数据被再次读取并且与写检查数据进行比较。 ROM 4a的FD12。当比较这些数据时没有检测到任何故障时，CPU确定闪存2正常。此外，如果在比较数据中检测到故障，则CPU将复位处理故障数据设置为寄存器5a，以将控制器3设置为睡眠模式。当在此期间接收到命令CMD时，再次执行数据比较。

6. 发明授权

US07418602B2 Memory card 失效
标题翻译：存储卡
公开(公告)号：US07418602B2
公开(公告)日：2008-08-26
申请号：US10868960
申请日：2004-06-17
申请人： Satoshi Yoshida , Kunihiro Katayama , Akira Kanehira , Masaharu Ukeda
发明人： Satoshi Yoshida , Kunihiro Katayama , Akira Kanehira , Masaharu Ukeda
IPC分类号： G06F21/00
CPC分类号： G06F21/78 , G06F21/31 , G06F2221/2143
摘要： In order to protect the user security data, provided is a memory card capable of preventing the data leakage to a third party not having the access authority by imposing the limitation on the number of password authentications and automatically erasing the data. In a system comprised of a multimedia card and a host machine electrically connected to the multimedia card and controlling the operations of the multimedia card, a retry counter for storing the number of password authentication failures is provided and the upper limit of the number of failures is registered in a register. When passwords are repeatedly entered once, twice, . . . and n times and the retry counter which counts the entries reaches the upper limit of the number of failures, the data is automatically erased so as not to leave the data in the flash memory.
摘要翻译：为了保护用户安全数据，提供了一种能够通过对密码认证数量进行限制并自动擦除数据来防止数据泄漏给不具有访问权限的第三方的存储卡。在由多媒体卡和与多媒体卡电连接并控制多媒体卡的操作的主机构成的系统中，提供用于存储密码认证失败次数的重试计数器，故障次数的上限为注册登记。当密码重复输入一次，两次，。。。并且n次，对条目进行计数的重试计数器达到故障次数的上限，数据被自动擦除，以便不将数据留在闪存中。

7. 发明申请

US20080059852A1 MEMORY CARD AND ITS INITIAL SETTING METHOD 有权
标题翻译：记忆卡及其初始设置方法
公开(公告)号：US20080059852A1
公开(公告)日：2008-03-06
申请号：US11877500
申请日：2007-10-23
申请人： Hidefumi Oodate , Atsushi Shiraishi , Shigeo Kurakata , Kunihiro Katayama , Motoki Kanamori
发明人： Hidefumi Oodate , Atsushi Shiraishi , Shigeo Kurakata , Kunihiro Katayama , Motoki Kanamori
IPC分类号： G11C29/00
CPC分类号： G11C16/20
摘要： In the initial setting of a memory card 1, the flash check data FD stored in a flash memory 2 is read out, this data FD is compared with the operation check data FD11 stored previously in the ROM, the write check data FD12 stored in the ROM 4a is written, if a fault is not detected, to the flash memory 2, and this data is read again and is compared with the write check data. FD12 of the ROM 4a. When any fault is not detected in comparison of these data, the CPU determines that the flash memory 2 is normal. Moreover, if a fault is detected in the comparison of data, the CPU sets the reset process fault data to a register 5a to set a controller 3 to the sleep mode. When the command CMD is received during this period, data comparison is executed again.
摘要翻译：在存储卡1的初始设置中，读出存储在闪速存储器2中的闪存检查数据FD，该数据FD与先前存储在ROM中的操作检查数据FD1＆lt; 1＆gt; 存储在ROM4a中的写入检查数据FD1＆lt; 2＆gt;如果没有检测到故障则被写入闪速存储器2，并且再次读取该数据并与写入检查进行比较数据。 ROM1a的FD1＆lt; 2＆gt ;. 当比较这些数据时没有检测到任何故障时，CPU确定闪存2正常。此外，如果在数据比较中检测到故障，则CPU将复位过程故障数据设置为寄存器5a以将控制器3设置为睡眠模式。当在此期间接收到命令CMD时，再次执行数据比较。

8. 发明授权

US07295467B2 Semiconductor memory having electrically erasable and programmable semiconductor memory cells 有权
标题翻译：具有电可擦除和可编程的半导体存储器单元的半导体存储器
公开(公告)号：US07295467B2
公开(公告)日：2007-11-13
申请号：US11206995
申请日：2005-08-19
申请人： Kunihiro Katayama , Takayuki Tamura , Kiyoshi Inoue
发明人： Kunihiro Katayama , Takayuki Tamura , Kiyoshi Inoue
IPC分类号： G11C16/04
CPC分类号： G11C16/28 , G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C16/10 , G11C16/30 , G11C2211/5621 , G11C2211/5632 , G11C2211/5634 , G11C2211/5641 , G11C2211/5642
摘要： An electrically alterable non-volatile multi-level memory device and a method of operating such a device, which includes setting a status of at least one of the memory cells to one state selected from a plurality of states including at least first to fourth level states, in response to information to be stored in the one memory cell, and reading the status of the memory cell to determine whether the read out status corresponds to one of the first to fourth level states by utilizing a first reference level set between the second and third level states, a second reference level set between the first and second level states and a third reference level set between the third and fourth level states.
摘要翻译：一种可电气可变的非易失性多级存储器件和操作这种器件的方法，其包括将至少一个存储器单元的状态设置为从包括至少第一至第四电平状态的多个状态中选择的一种状态响应于要存储在一个存储器单元中的信息，并且通过利用在第二和第二电平状态之间设置的第一参考电平来读取存储单元的状态来确定读出状态是否对应于第一至第四电平状态之一第三电平状态，在第一和第二电平状态之间设置的第二参考电平和在第三和第四电平状态之间设置的第三参考电平。

9. 发明申请

US20070168782A1 External storage device and memory access control method thereof 有权
标题翻译：外部存储装置及其存储器访问控制方法
公开(公告)号：US20070168782A1
公开(公告)日：2007-07-19
申请号：US11599388
申请日：2006-11-15
申请人： Takayuki Tamura , Shigemasa Shiota , Kunihiro Katayama , Masashi Naito
发明人： Takayuki Tamura , Shigemasa Shiota , Kunihiro Katayama , Masashi Naito
IPC分类号： G11C29/00
CPC分类号： G06F11/1008
摘要： A storage device, including: a non-volatile semiconductor memory which is electrically erasable; a system interface coupled with an external host system; and a controller reading data from the non-volatile semiconductor memory and transmitting data to the host system via the system interface in response to a read command received by the system interface from the host system; and wherein the controller starts reading (N+n)th sector data from the non-volatile semiconductor memory, while the controller transmits Nth sector data that has been read from the non-volatile semiconductor memory to the host system via the system interface, in response to the read command for successive sector data.
摘要翻译：一种存储装置，包括：电可擦除的非易失性半导体存储器; 与外部主机系统耦合的系统接口; 以及控制器，从所述非易失性半导体存储器读取数据，并且响应于所述系统接口从所述主机系统接收到的读取命令，经由所述系统接口向所述主机系统发送数据; 并且其中所述控制器从所述非易失性半导体存储器开始读取第（N + n）个扇区数据，同时所述控制器经由所述系统接口将从所述非易失性半导体存储器读取的第N个扇区数据发送到所述主机系统，对连续扇区数据的读命令作出响应。

10. 发明授权

US07188265B2 Method of recognizing a card using a select signal during a determination mode and switching from low to high resistance after the determination 有权
标题翻译：在确定模式期间使用选择信号识别卡并在确定之后从低电平切换到高电阻的方法
公开(公告)号：US07188265B2
公开(公告)日：2007-03-06
申请号：US10716456
申请日：2003-11-20
申请人： Shigeo Kurakata , Kunihiro Katayama , Motoki Kanamori , Atsushi Shikata , Tetsuya Iida
发明人： Shigeo Kurakata , Kunihiro Katayama , Motoki Kanamori , Atsushi Shikata , Tetsuya Iida
IPC分类号： G06F1/26
CPC分类号： G06K19/0701 , G06K19/07
摘要： A memory card is provided in which power consumption is reduced by the pull-up resistor of an input terminal and a misoperation induced by the pull-down resistor of a host apparatus is prevented. The memory card has a select terminal connected to the pull-up resistor. When the mode of the memory card is determined based on an input from the select terminal, a relatively low resistance value is selected for the pull-up resistor of the select terminal before a determination timing and the pull-up resistor is restored to an initial resistance value after the mode determination. A relatively high resistance value reduces a leakage current consumed by the pull-up resistor of the select terminal. When a pull-down resistor is connected to the terminal of a memory card host to which the memory card is attached, if the resistance value of the pull-up resistor is excessively high, it is influenced by the drawing in of a current by the pull-down resistor. If the resistance value of the pull-up resistor of the select terminal is lowered at the time of mode determination, an adverse effect of the lowering of a potential by the pull-down resistor can be circumvented.
摘要翻译：提供了一种存储卡，其中通过输入端的上拉电阻降低功耗，并且防止由主机设备的下拉电阻引起的误操作。存储卡具有连接到上拉电阻的选择端子。当基于来自选择端子的输入确定存储卡的模式时，在确定定时之前为选择端的上拉电阻选择相对较低的电阻值，并且将上拉电阻恢复到初始值模式确定后的电阻值。相对较高的电阻值减小了选择端子的上拉电阻消耗的漏电流。当下拉电阻连接到与存储卡相连的存储卡主机的端子时，如果上拉电阻的电阻值过高，则会受到电流的影响下拉电阻。如果选择端子的上拉电阻的电阻值在模式确定时降低，则可以避免下拉电阻降低电位的不利影响。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式