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1. 发明授权

US07873785B2 Multi-core multi-thread processor 有权
标题翻译：多核多线程处理器
公开(公告)号：US07873785B2
公开(公告)日：2011-01-18
申请号：US10855233
申请日：2004-05-26
申请人： Kunle A. Olukotun
发明人： Kunle A. Olukotun
IPC分类号： G06F12/08
CPC分类号： G06F9/3834 , G06F9/30032 , G06F9/30047 , G06F9/30087 , G06F9/3009 , G06F9/30141 , G06F9/3828 , G06F9/3851 , G06F9/3861 , G06F9/3891 , G06F12/0811 , G06F12/0813 , G06F12/0842 , G06F15/167 , G06F15/781
摘要： A processor is provided. The processor includes at least two cores. The at least two cores have a first level cache memory and are multi-threaded. A crossbar is included. A plurality of cache bank memories in communication with the at least two cores through the crossbar is provided. Each of the plurality of cache bank memories communicates with a main memory interface. A plurality of input/output interface modules in communication with the main memory interface and providing a link to the at least two cores are included. The link bypasses the plurality of cache bank memories and the crossbar. Threading hardware configured to enable the at least two cores to switch from a first thread to a second thread in a manner hiding delays caused by cache accesses is included. A server and a method for determining when to switch threads in a multi-core multi-thread environment are included.
摘要翻译：提供处理器。处理器包括至少两个核。至少两个内核具有第一级缓存，并且是多线程的。包括交叉开关。提供了通过横杆与至少两个核心通信的多个高速缓存组存储器。多个高速缓存组存储器中的每一个与主存储器接口通信。包括与主存储器接口通信并提供到至少两个核的链接的多个输入/输出接口模块。链路绕过多个缓存组存储器和横杠。被配置为使得至少两个核能够以隐藏由高速缓存访问引起的延迟的方式从第一线程切换到第二线程的线程硬件被包括。包括用于确定何时切换多核多线程环境中的线程的服务器和方法。

2. 发明授权

US07133950B2 Request arbitration in multi-core processor 有权
标题翻译：在多核处理器中请求仲裁
公开(公告)号：US07133950B2
公开(公告)日：2006-11-07
申请号：US10855060
申请日：2004-05-26
申请人： Kunle A. Olukotun
发明人： Kunle A. Olukotun
IPC分类号： G06F13/36
CPC分类号： G06F13/1657 , G06F9/3851 , G06F9/3891 , G06F12/084 , G06F12/0846
摘要： A processor chip is provided. The processor chip includes a plurality of processing cores, where each of the processing cores are multi-threaded. The plurality of processing cores are located in a center region of the processor chip. A plurality of cache bank memories are included. A crossbar enabling communication between the plurality of processing cores and the plurality of cache bank memories is provided. The crossbar includes an arbiter configured to arbitrate multiple requests received from the plurality of processing cores with available outputs. The arbiter includes a barrel shifter configured to rotate the multiple requests for dynamic prioritization, and priority encoders associated with each of the available outputs. Each of the priority encoders have logic gates configured to disable priority encoder outputs. A method for arbitrating requests within a multi-core multi-thread processor is included.
摘要翻译：提供处理器芯片。处理器芯片包括多个处理核心，其中每个处理核心是多线程的。多个处理核心位于处理器芯片的中心区域。包括多个缓存组存储器。提供了能够实现多个处理核与多个高速缓存组存储器之间的通信的交叉开关。交叉开关包括仲裁器，其被配置为通过可用的输出来仲裁从多个处理核心接收到的多个请求。仲裁器包括桶形移位器，其被配置为旋转用于动态优先级的多个请求，以及与每个可用输出相关联的优先级编码器。每个优先编码器具有被配置为禁用优先编码器输出的逻辑门。包括在多核多线程处理器内仲裁请求的方法。

3. 发明授权

US08463996B2 Multi-core multi-thread processor crossbar architecture 有权
标题翻译：多核多线程处理器交叉开关架构
公开(公告)号：US08463996B2
公开(公告)日：2013-06-11
申请号：US10855694
申请日：2004-05-26
申请人： Kunle A. Olukotun
发明人： Kunle A. Olukotun
IPC分类号： G06F12/00 , G06F13/00
CPC分类号： G06F13/1657 , G06F12/0811 , G06F12/0842
摘要： A processor chip is provided. The processor chip includes a plurality of processing cores where each of the processing cores being multi-threaded. The plurality of processing cores are located in a center region of the processor chip. A plurality of cache bank memories are included. A crossbar enabling communication between the plurality of processing cores and the plurality of cache bank memories is provided. The crossbar includes a centrally located arbiter configured to sort multiple requests received from the plurality of processing cores and the crossbar is defined over the plurality of processing cores. In another embodiment, the processor chip is oriented so that the cache bank memories are defined in the center region. A server is also included.
摘要翻译：提供处理器芯片。处理器芯片包括多个处理核心，其中每个处理核心是多线程的。多个处理核心位于处理器芯片的中心区域。包括多个缓存组存储器。提供了能够实现多个处理核与多个高速缓存组存储器之间的通信的交叉开关。交叉开关包括中心定位的仲裁器，其被配置为对从多个处理核心接收到的多个请求进行排序，并且在多个处理核心上定义交叉开关。在另一个实施例中，处理器芯片被定向成使得高速缓存组存储器被定义在中心区域中。还包括服务器。

4. 发明授权

US07209996B2 Multi-core multi-thread processor 有权
标题翻译：多核多线程处理器
公开(公告)号：US07209996B2
公开(公告)日：2007-04-24
申请号：US10272786
申请日：2002-10-16
申请人： Leslie D. Kohn , Kunle A. Olukotun , Michael K. Wong
发明人： Leslie D. Kohn , Kunle A. Olukotun , Michael K. Wong
IPC分类号： G06F13/16
CPC分类号： H04L47/10 , G06F1/3203 , G06F1/3225 , G06F1/3275 , G06F3/1423 , G06F9/30007 , G06F9/30043 , G06F9/3851 , G06F9/3879 , G06F9/3891 , G06F11/108 , G06F12/0811 , G06F12/0813 , G06F12/084 , G06F13/1689 , G06F21/72 , G09G2352/00 , G09G2360/121 , G09G2370/022 , G09G2370/20 , G11C11/4074 , H04L29/06 , H04L45/745 , H04L47/2441 , H04L49/90 , H04L49/9057 , H04L49/9089 , H04L69/22 , Y02D10/13 , Y02D10/14
摘要： In one embodiment, a processor is provided. The processor includes at least two cores, where each of the cores include a first level cache memory. Each of the cores are multi-threaded. In another embodiment, each of the cores includes four threads. In another embodiment a crossbar is included. A plurality of cache bank memories in communication with the at cores through the crossbar is provided. Each of the plurality of cache bank memories are in communication with a main memory interface. In another embodiment a buffer switch core in communication with each of the plurality of cache bank memories is also included. A server and a method for optimizing the utilization of a multithreaded processor core are also provided.
摘要翻译：在一个实施例中，提供处理器。处理器包括至少两个核，其中每个核包括第一级高速缓冲存储器。每个核心都是多线程的。在另一个实施例中，每个芯包括四个螺纹。在另一个实施例中，包括交叉开关。提供了通过横杆与内核通信的多个缓存组存储器。多个高速缓存组存储器中的每一个与主存储器接口通信。在另一个实施例中，还包括与多个高速缓存组存储器中的每一个通信的缓冲器开关核心。还提供了用于优化多线程处理器核的利用率的服务器和方法。

5. 发明授权

US06938119B2 DRAM power management 有权
标题翻译： DRAM电源管理
公开(公告)号：US06938119B2
公开(公告)日：2005-08-30
申请号：US10273806
申请日：2002-10-18
申请人： Leslie D. Kohn , Kunle A. Olukotun , Michael K. Wong
发明人： Leslie D. Kohn , Kunle A. Olukotun , Michael K. Wong
IPC分类号： G06F12/00 , G06F1/32 , G06F9/30 , G06F9/38 , G06F9/46 , G06F11/10 , G06F12/08 , G06F12/16 , G06F13/00 , G06F13/14 , G06F13/16 , G06F13/38 , G06F15/16 , G06F15/167 , G06F15/173 , G06F15/78 , G06F21/00 , G09C1/00 , G11C11/4074 , H04L12/56 , H04L29/06
CPC分类号： H04L47/10 , G06F1/3203 , G06F1/3225 , G06F1/3275 , G06F3/1423 , G06F9/30007 , G06F9/30043 , G06F9/3851 , G06F9/3879 , G06F9/3891 , G06F11/108 , G06F12/0811 , G06F12/0813 , G06F12/084 , G06F13/1689 , G06F21/72 , G09G2352/00 , G09G2360/121 , G09G2370/022 , G09G2370/20 , G11C11/4074 , H04L29/06 , H04L45/745 , H04L47/2441 , H04L49/90 , H04L49/9057 , H04L49/9089 , H04L69/22 , Y02D10/13 , Y02D10/14
摘要： A system and method for limiting power consumption of a computer memory system. The system and method includes selecting a memory access rate. The selected memory access rate corresponds to a desired average memory power consumption rate. A first time interval is started as a current time interval. A memory system is accessed. If the memory access rate has not been exceeded, then the access is applied to the memory system. Alternatively, if the memory access rate has been exceeded, then the access is delayed until the current time interval has expired and a subsequent time interval is started as the current time interval and the access is applied to the memory system.
摘要翻译：一种用于限制计算机存储器系统的功耗的系统和方法。该系统和方法包括选择存储器访问速率。所选择的存储器访问速率对应于期望的平均存储器功耗率。以当前时间间隔开始第一时间间隔。访问存储系统。如果没有超过存储器访问速率，那么访问被应用于存储器系统。或者，如果超过了存储器访问速率，则访问被延迟，直到当前时间间隔期满并且随后的时间间隔开始为当前时间间隔，并且访问被应用于存储器系统。

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