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1. 发明申请

US20180333003A1 COLLAPSIBLE STOKING APPARATUS 审中-公开
公开(公告)号：US20180333003A1
公开(公告)日：2018-11-22
申请号：US15299082
申请日：2016-10-20
申请人： Kuo-Chan Huang
发明人： Kuo-Chan Huang
IPC分类号： A47J37/07
CPC分类号： A47J37/079 , A47J2037/0777
摘要： A stoking apparatus includes two concealable panels, a bent covering panel and a flat covering panel. The concealable panels are pivotally connected to each other. The bent covering panel includes a major portion and a minor portion, with an angle between the major and minor portions. The major portion is pivotally connected to one of the concealable panels. The minor portion is pivotally connected to the flat covering panel. The flat covering panel is further pivotally connected to the other concealable panel. The minor portion provides a gap between the major portion and the flat covering panel to receive the first and second concealable panels when the collapsible stoking apparatus is in a collapsed position.

2. 发明申请

US20140232205A1 ELECTRONIC APPARATUS 有权
标题翻译：电子设备
公开(公告)号：US20140232205A1
公开(公告)日：2014-08-21
申请号：US14182288
申请日：2014-02-18
申请人： Shu-Hao Li , Kuo-Chan Huang , Yi-Hsun Lin , Tzu-Chiang Mi
发明人： Shu-Hao Li , Kuo-Chan Huang , Yi-Hsun Lin , Tzu-Chiang Mi
IPC分类号： H02J9/00
CPC分类号： H02J9/005 , G06F1/3206 , G06F1/3234 , Y10T307/826
摘要： An electronic apparatus is provided. The electronic apparatus includes a controller, a first trigger circuit, a switch unit and a logic circuit. The controller provides a setting signal. The first trigger circuit provides a trigger signal according to at least one of first trigger situations. The switch unit is connected to a power input terminal. The logic circuit adjusts a switching signal according to the setting signal and the trigger signal. The switch unit decides whether to provide an input voltage at the power input terminal to the electronic apparatus according to the switching signal.
摘要翻译：提供电子设备。电子设备包括控制器，第一触发电路，开关单元和逻辑电路。控制器提供设置信号。第一触发电路根据第一触发情况中的至少一个提供触发信号。开关单元连接到电源输入端子。逻辑电路根据设定信号和触发信号调整切换信号。开关单元根据切换信号决定是否在电力输入端子向电子设备提供输入电压。

3. 发明申请

US20110241752A1 Mixed-voltage I/O buffer 有权
标题翻译：混合电压I / O缓冲器
公开(公告)号：US20110241752A1
公开(公告)日：2011-10-06
申请号：US13067598
申请日：2011-06-13
申请人： Chua-Chin Wang , Wei-Chih Chang , Tzung-Je Lee , Kuo-Chan Huang
发明人： Chua-Chin Wang , Wei-Chih Chang , Tzung-Je Lee , Kuo-Chan Huang
IPC分类号： H03K5/08
CPC分类号： H03K19/0013 , H03K3/356113 , H03K19/018521
摘要： A mixed-voltage I/O buffer includes an input buffer circuit. The input buffer circuit includes a first inverter, a first voltage level limiting circuit, a first voltage level pull-up circuit, an input stage circuit, and a logic calibration circuit. The first inverter inverts an input signal to generate a first control signal. The first voltage level limiting circuit limits voltage level of an external signal to generate the input signal transmitted to the first inverter to prevent electrical overstress of the first inverter. The first voltage level pull-up circuit is controlled by the first control signal to pull up voltage level of the input signal inputted into the first inverter. The input stage circuit receives the first control signal to generate corresponding digital signals inputted into a core circuit. The logic calibration circuit calibrates voltage level of the first control signal when the first inverter mis-operates due to the input signal having a low voltage level.
摘要翻译：混合电压I / O缓冲器包括输入缓冲电路。输入缓冲电路包括第一反相器，第一电压电平限制电路，第一电压电平上拉电路，输入级电路和逻辑校准电路。第一反相器反相输入信号以产生第一控制信号。第一电压电平限制电路限制外部信号的电压电平，以产生传输到第一逆变器的输入信号，以防止第一逆变器的电过载。第一电压上拉电路由第一控制信号控制，以提高输入到第一反相器的输入信号的电压电平。输入级电路接收第一控制信号以产生输入到核心电路的相应的数字信号。当由于输入信号具有低电压电平而使第一反相器误操作时，逻辑校准电路校准第一控制信号的电压电平。

4. 发明授权

US07957923B2 Device for jitter measurement and method thereof 有权
标题翻译：抖动测量装置及其方法
公开(公告)号：US07957923B2
公开(公告)日：2011-06-07
申请号：US12117176
申请日：2008-05-08
申请人： An-Sheng Chao , Soon-Jyh Chang , Chih-Haur Huang , Kuo-Chan Huang , Shih-Ming Luo
发明人： An-Sheng Chao , Soon-Jyh Chang , Chih-Haur Huang , Kuo-Chan Huang , Shih-Ming Luo
IPC分类号： G06F19/00 , H04B3/46
CPC分类号： G01R31/31709
摘要： The device for jitter measurement and a method thereof are provided. The device for jitter measure includes a signal retrieving module, a signal amplifying module, an edge detecting module, and a time-to-digital converting module. The signal retrieving module receives a signal-under-test, and retrieves a first pulse signal having a pulse width equal to a period of the signal-under-test. The signal amplifying module amplifies the pulse width of the first pulse signal and thereby generates a second pulse signal. The edge detecting module detects a rising edge and a falling edge of the second pulse signal, and generates a first indication signal and a second indication signal according to the respective detected results. The time-to-digital converting module converts the pulse width of the second pulse signal existed in time domain to a digital signal according to the first indication signal and the second indication signal.
摘要翻译：提供抖动测量装置及其方法。用于抖动测量的装置包括信号检索模块，信号放大模块，边缘检测模块和时间 - 数字转换模块。信号检索模块接收待测信号，并检索具有等于被测信号的周期的脉冲宽度的第一脉冲信号。信号放大模块放大第一脉冲信号的脉冲宽度，从而产生第二脉冲信号。边缘检测模块检测第二脉冲信号的上升沿和下降沿，并根据各个检测结果生成第一指示信号和第二指示信号。时间 - 数字转换模块根据第一指示信号和第二指示信号将时域中存在的第二脉冲信号的脉冲宽度转换为数字信号。

5. 发明授权

US07839174B2 Mixed-voltage tolerant I/O buffer and output buffer circuit thereof 有权
标题翻译：混合电压容限I / O缓冲器及其输出缓冲电路
公开(公告)号：US07839174B2
公开(公告)日：2010-11-23
申请号：US12330768
申请日：2008-12-09
申请人： Chua-Chin Wang , Tzung-Je Lee , Yi-Cheng Liu , Kuo-Chan Huang
发明人： Chua-Chin Wang , Tzung-Je Lee , Yi-Cheng Liu , Kuo-Chan Huang
IPC分类号： H03K19/094
CPC分类号： H03K19/018521
摘要： An output buffer circuit includes a high voltage detecting circuit, a dynamic gate bias generating circuit, an output stage circuit and a pad voltage detector. The high voltage detecting circuit detects a power supply voltage and generates a first and a second determining signals and a first and a second bias voltages according to the power supply voltage. The dynamic gate bias generating circuit is biased by the first and the second bias voltages and receives the first and the second determining signals, for converting logic control signals into corresponding gate bias voltages according to the first and the second determining signals. The pad voltage detector detects a voltage of an I/O pad and provides a pad voltage detecting signal for the output stage circuit to modify an output signal outputted to an I/O pad. A mixed-voltage input/output (I/O) buffer is disclosed herein.
摘要翻译：输出缓冲电路包括高电压检测电路，动态栅极偏置产生电路，输出级电路和焊盘电压检测器。高电压检测电路检测电源电压，并根据电源电压产生第一和第二确定信号以及第一和第二偏置电压。动态栅极偏置产生电路被第一和第二偏置电压偏置，并接收第一和第二确定信号，用于根据第一和第二确定信号将逻辑控制信号转换成相应的栅极偏置电压。焊盘电压检测器检测I / O焊盘的电压，并为输出级电路提供焊盘电压检测信号，以修改输出到I / O焊盘的输出信号。本文公开了混合电压输入/输出（I / O）缓冲器。

6. 发明申请

US20100141324A1 Mixed-Voltage Tolerant I/O Buffer and Output Buffer Circuit Thereof 有权
标题翻译：混合电压容限I / O缓冲器和输出缓冲电路
公开(公告)号：US20100141324A1
公开(公告)日：2010-06-10
申请号：US12330768
申请日：2008-12-09
申请人： Chua-Chin Wang , Tzung-Je Lee , Yi-Cheng Liu , Kuo-Chan Huang
发明人： Chua-Chin Wang , Tzung-Je Lee , Yi-Cheng Liu , Kuo-Chan Huang
IPC分类号： H03L5/00
CPC分类号： H03K19/018521
摘要： An output buffer circuit includes a high voltage detecting circuit, a dynamic gate bias generating circuit, an output stage circuit and a pad voltage detector. The high voltage detecting circuit detects a power supply voltage and generates a first and a second determining signals and a first and a second bias voltages according to the power supply voltage. The dynamic gate bias generating circuit is biased by the first and the second bias voltages and receives the first and the second determining signals, for converting logic control signals into corresponding gate bias voltages according to the first and the second determining signals. The pad voltage detector detects a voltage of an I/O pad and provides a pad voltage detecting signal for the output stage circuit to modify an output signal outputted to an I/O pad. A mixed-voltage input/output (I/O) buffer is disclosed herein.
摘要翻译：输出缓冲电路包括高电压检测电路，动态栅极偏置产生电路，输出级电路和焊盘电压检测器。高电压检测电路检测电源电压，并根据电源电压产生第一和第二确定信号以及第一和第二偏置电压。动态栅极偏置产生电路被第一和第二偏置电压偏置，并接收第一和第二确定信号，用于根据第一和第二确定信号将逻辑控制信号转换成相应的栅极偏置电压。焊盘电压检测器检测I / O焊盘的电压，并为输出级电路提供焊盘电压检测信号，以修改输出到I / O焊盘的输出信号。本文公开了混合电压输入/输出（I / O）缓冲器。

7. 发明申请

US20100097117A1 Mixed-voltage I/O buffer 有权
标题翻译：混合电压I / O缓冲器
公开(公告)号：US20100097117A1
公开(公告)日：2010-04-22
申请号：US12289132
申请日：2008-10-21
申请人： Chua-Chin Wang , Wei-Chih Chang , Tzung-Je Lee , Kuo-Chan Huang
发明人： Chua-Chin Wang , Wei-Chih Chang , Tzung-Je Lee , Kuo-Chan Huang
IPC分类号： H03L5/00
CPC分类号： H03K19/0013 , H03K3/356113 , H03K19/018521
摘要： A mixed-voltage input/output (I/O) buffer includes an output buffer circuit. The output buffer circuit includes an output stage circuit, a gate-tracking circuit and a floating N-well circuit. The output stage circuit includes stacked pull-up P-type transistors and stacked pull-down N-type transistors, in which a first P-type transistor of the stacked pull-up P-type transistors and a first N-type transistor of the stacked pull-down N-type transistors are coupled to an I/O pad. The gate-tracking circuit controls gate voltage of the first P-type transistor in accordance with a voltage of the I/O pad to prevent leakage current. The floating N-well circuit provides N-well voltages for an N-well of the first P-type transistor and an N-well of a second P-type transistor, controlling gate voltage of the first P-type transistor, of the gate-tracking circuit to prevent leakage current.
摘要翻译：混合电压输入/输出（I / O）缓冲器包括输出缓冲电路。输出缓冲电路包括输出级电路，栅极跟踪电路和浮动N阱电路。输出级电路包括堆叠上拉P型晶体管和堆叠式下拉式N型晶体管，其中堆叠上拉P型晶体管的第一P型晶体管和第一N型晶体管堆叠的下拉式N型晶体管耦合到I / O焊盘。栅极跟踪电路根据I / O焊盘的电压来控制第一P型晶体管的栅极电压，以防止漏电流。浮动N阱电路为第一P型晶体管的N阱和第二P型晶体管的N阱提供N阱电压，控制栅极的第一P型晶体管的栅极电压跟踪电路，以防止漏电流。

8. 发明授权

US07602324B1 A/D converter and method for converting analog signals into digital signals 有权
标题翻译： A / D转换器和将模拟信号转换为数字信号的方法
公开(公告)号：US07602324B1
公开(公告)日：2009-10-13
申请号：US12356107
申请日：2009-01-20
申请人： Chih-Haur Huang , Kuo-Chan Huang
发明人： Chih-Haur Huang , Kuo-Chan Huang
IPC分类号： H03M1/20
CPC分类号： H03M1/0641 , H03M1/0695 , H03M1/164 , H03M1/44
摘要： A method for converting analog signals into digital signals includes the steps of: superimposing a dither value on an analog input signal; sampling the superimposition of the analog input signal with the dither value to obtain a sampling signal; converting the sampling signal into corresponding digital values; correcting offsets in the digital values to generate a digital signal; and removing the dither value from the digital signal. An analog-to-digital converter is also disclosed herein.
摘要翻译：一种将模拟信号转换为数字信号的方法包括以下步骤：将抖动值叠加在模拟输入信号上; 对模拟输入信号与抖动值的叠加进行取样以获得采样信号; 将采样信号转换成相应的数字值; 校正数字值中的偏移量以产生数字信号; 并从数字信号中去除抖动值。本文还公开了一种模拟 - 数字转换器。

9. 发明申请

US20090066367A1 INPUT OUTPUT DEVICE FOR MIXED-VOLTAGE TOLERANT 有权
标题翻译：用于混合电压稳定器的输入输出装置
公开(公告)号：US20090066367A1
公开(公告)日：2009-03-12
申请号：US12184271
申请日：2008-08-01
申请人： Chua-Chin Wang , Tzung-Je Lee , Kuo-Chan Huang , Tie-Yan Chang
发明人： Chua-Chin Wang , Tzung-Je Lee , Kuo-Chan Huang , Tie-Yan Chang
IPC分类号： H03K19/0175
CPC分类号： H03K19/00315
摘要： An input output device coupled between a core circuit and a pad and including an output cell, an input cell, and a pre-driver. The output cell includes an output stage and a voltage level converter. The output stage includes a first transistor and a second transistor connected to the first transistor in serial between a first supply voltage and a second voltage. The voltage level converter generates a first gate voltage to the first transistor according to the first voltage and a data signal. When the first supply voltage is increased, the first gate voltage is increased. When the data signal is at a high level, the first transistor is turned on. The input cell includes a pull unit and a first N-type transistor. The pre-driver turns off the first and the second transistors.
摘要翻译：耦合在核心电路和焊盘之间并包括输出单元，输入单元和预驱动器的输入输出设备。输出单元包括输出级和电压电平转换器。输出级包括在第一电源电压和第二电压之间串联连接到第一晶体管的第一晶体管和第二晶体管。电压电平转换器根据第一电压和数据信号产生到第一晶体管的第一栅极电压。当第一电源电压增加时，第一栅极电压增加。当数据信号处于高电平时，第一晶体管导通。输入单元包括拉单元和第一N型晶体管。预驱动器关闭第一和第二晶体管。

10. 发明申请

US20070103208A1 Source driver output stage circuit, buffer circuit and voltage adjusting method thereof 有权
标题翻译：源极驱动器输出级电路，缓冲电路及其电压调整方法
公开(公告)号：US20070103208A1
公开(公告)日：2007-05-10
申请号：US11594774
申请日：2006-11-09
申请人： Kuo-Chan Huang , Chih-Haur Huang
发明人： Kuo-Chan Huang , Chih-Haur Huang
IPC分类号： H03B1/00
CPC分类号： H03F3/217 , G09G2310/0275 , G09G2320/0252 , G09G2330/021 , G09G2330/028 , H03F2200/78
摘要： A buffer circuit applied to a source driver output stage circuit includes a buffer and a D-class amplifier. The buffer is coupled to an input voltage for accordingly outputting an output voltage. The D-class amplifier includes a comparator and a switch device. The comparator is for comparing the input voltage and the output voltage and accordingly outputting a comparison signal. The switch device is coupled to an operational voltage for adjusting the output voltage according to the comparison signal.
摘要翻译：应用于源极驱动器输出级电路的缓冲电路包括缓冲器和D级放大器。缓冲器耦合到输入电压，从而相应地输出输出电压。 D级放大器包括比较器和开关装置。比较器用于比较输入电压和输出电压，从而输出比较信号。开关装置耦合到用于根据比较信号调节输出电压的工作电压。

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