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1. 发明授权

US07853848B2 System and method for signature-based systematic condition detection and analysis 失效
标题翻译：基于签名的系统状态检测和分析的系统和方法
公开(公告)号：US07853848B2
公开(公告)日：2010-12-14
申请号：US11875975
申请日：2007-10-22
申请人： Rao H. Desineni , Maroun Kassab , Leah M. Pastel
发明人： Rao H. Desineni , Maroun Kassab , Leah M. Pastel
IPC分类号： G01R31/28 , G01R31/30 , G01R31/26 , G01R31/08 , G06F17/50
CPC分类号： G01R31/318321
摘要： Disclosed are embodiments of a system, method and service for detecting and analyzing systematic conditions occurring in manufactured devices. Each embodiment comprises generating a unique signature for each of multiple tested devices. The signatures are generated based on an initial set of signature definitions and the values for those signature definitions that are derived at least in part from selected testing data. A systematic condition is detected based on commonalities between the signatures. The systematic condition is then analyzed, alone or in conjunction with additional information, in order to develop a list of underlying similarities between the devices. The analysis results can be used to refine the systematic condition detection and analysis processes by revising the signature definitions set and/or by modifying data selection.
摘要翻译：公开了用于检测和分析在制造的装置中发生的系统状况的系统，方法和服务的实施例。每个实施例包括为多个被测试设备中的每一个产生唯一的签名。基于签名定义的初始集合以及至少部分地从选定的测试数据导出的那些签名定义的值来生成签名。基于签名之间的共同点检测系统条件。然后单独或与附加信息一起分析系统条件，以便开发设备之间的基本相似性列表。分析结果可用于通过修改签名定义集和/或通过修改数据选择来完善系统状态检测和分析过程。

2. 发明申请

US20090106614A1 SYSTEM AND METHOD FOR SIGNATURE-BASED SYSTEMATIC CONDITION DETECTION AND ANALYSIS 失效
标题翻译：用于基于签名的系统状态检测和分析的系统和方法
公开(公告)号：US20090106614A1
公开(公告)日：2009-04-23
申请号：US11875975
申请日：2007-10-22
申请人： Rao H. Desineni , Maroun Kassab , Leah M. Pastel
发明人： Rao H. Desineni , Maroun Kassab , Leah M. Pastel
IPC分类号： G01R31/3181 , G06F11/26
CPC分类号： G01R31/318321
摘要： Disclosed are embodiments of a system, method and service for detecting and analyzing systematic conditions occurring in manufactured devices. Each embodiment comprises generating a unique signature for each of multiple tested devices. The signatures are generated based on an initial set of signature definitions and the values for those signature definitions that are derived at least in part from selected testing data. A systematic condition is detected based on commonalities between the signatures. The systematic condition is then analyzed, alone or in conjunction with additional information, in order to develop a list of underlying similarities between the devices. The analysis results can be used to refine the systematic condition detection and analysis processes by revising the signature definitions set and/or by modifying data selection.
摘要翻译：公开了用于检测和分析在制造的装置中发生的系统状况的系统，方法和服务的实施例。每个实施例包括为多个被测试设备中的每一个产生唯一的签名。基于签名定义的初始集合以及至少部分地从选定的测试数据导出的那些签名定义的值来生成签名。基于签名之间的共同点检测系统条件。然后单独或与附加信息一起分析系统条件，以便开发设备之间的基本相似性列表。分析结果可用于通过修改签名定义集和/或通过修改数据选择来完善系统状态检测和分析过程。

3. 发明授权

US07397263B2 Sensor differentiated fault isolation 有权
标题翻译：传感器差分故障隔离
公开(公告)号：US07397263B2
公开(公告)日：2008-07-08
申请号：US11670001
申请日：2007-02-01
申请人： Kevin L. Condon , Theodore M. Levin , Leah M. Pastel , David P. Vallett
发明人： Kevin L. Condon , Theodore M. Levin , Leah M. Pastel , David P. Vallett
IPC分类号： G01R31/02
CPC分类号： G01R31/311 , G01R31/302 , G01R31/31728 , G01R31/3187
摘要： Disclosed is an apparatus and method for diagnostically testing circuitry within a device. The apparatus and method incorporate the use of energy (e.g., light, heat, magnetic, electric, etc.) applied directly to any location on the device that can affect the electrical activity within the circuitry being tested in order to produce an indicator of a response. A local sensor (e.g., photonic, magnetic, etc.) is positioned at another location on the device where the sensor can detect the indicator of the response within the circuitry. A correlator is configured with response location correlation software and/or circuit tracing software so that when the indicator is detected, the correlator can determine the exact location of a response causing a device failure and/or trace the connectivity of the circuitry, based upon the location of the energy source and the location of the sensor.
摘要翻译：公开了一种用于诊断测试设备内的电路的装置和方法。该装置和方法包括直接应用于设备上可能影响被测电路内的电活动的任何位置的能量（例如光，热，磁，电等）的使用，以便产生一个响应。本地传感器（例如，光子，磁性等）位于设备上的另一位置处，其中传感器可以检测电路内的响应的指示符。相关器被配置有响应位置相关软件和/或电路跟踪软件，使得当检测到指示符时，相关器可基于导致设备故障的确定位置和/或跟踪电路的连通性来确定电路的连接性能源的位置和传感器的位置。

4. 发明授权

US07230335B2 Inspection methods and structures for visualizing and/or detecting specific chip structures 有权
标题翻译：用于可视化和/或检测特定芯片结构的检查方法和结构
公开(公告)号：US07230335B2
公开(公告)日：2007-06-12
申请号：US10711765
申请日：2004-10-04
申请人： Jerome L. Cann , Steven J. Holmes , Leendert M. Huisman , Cherie R. Kagan , Leah M. Pastel , Paul W. Pastel , James R. Salimeno, III , David P. Vallett
发明人： Jerome L. Cann , Steven J. Holmes , Leendert M. Huisman , Cherie R. Kagan , Leah M. Pastel , Paul W. Pastel , James R. Salimeno, III , David P. Vallett
IPC分类号： H01L23/48 , H01L21/302
CPC分类号： H01L21/7684 , H01L21/3212 , H01L21/76843 , H01L21/76865 , H01L21/7688
摘要： The present invention provides inspection methods and structures for facilitating the visualization and/or detection of specific chip structures. Optical or fluorescent labeling techniques are used to “stain” a specific chip structure for easier detection of the structure. Also, a temporary/sacrificial illuminating (e.g., fluorescent) film is added to the semiconductor process to facilitate the detection of a specific chip structure. Further, a specific chip structure is doped with a fluorescent material during the semiconductor process. A method of the present invention comprises: providing a first and a second material; processing the first material to form a portion of a semiconductor structure; and detecting a condition of the second material to determine whether processing of the first material is complete.
摘要翻译：本发明提供了用于促进特定芯片结构的可视化和/或检测的检查方法和结构。光学或荧光标记技术用于“污染”特定的芯片结构，以便于检测结构。此外，向半导体工艺中添加临时/牺牲照明（例如荧光）膜以便于检测特定的芯片结构。此外，在半导体工艺期间，用荧光材料掺杂特定的芯片结构。本发明的方法包括：提供第一和第二材料; 处理所述第一材料以形成半导体结构的一部分; 以及检测所述第二材料的状态以确定所述第一材料的处理是否完成。

5. 发明授权

US08566059B2 Insertion of faults in logic model used in simulation 失效
标题翻译：在模拟中使用的逻辑模型中插入故障
公开(公告)号：US08566059B2
公开(公告)日：2013-10-22
申请号：US12633151
申请日：2009-12-08
申请人： Rao H. Desineni , Maroun Kassab , Mary P. Kusko , Leah M. Pastel
发明人： Rao H. Desineni , Maroun Kassab , Mary P. Kusko , Leah M. Pastel
IPC分类号： G06F17/50 , G01R31/00
CPC分类号： G06F17/5022 , G06F11/261 , G06F2217/70
摘要： A method of selecting fault candidates based on the physical layout of an Integrated Circuit (IC) layout, that includes, identifying failing observation points in an IC layout, determining the failing observation points proximity geometry in the IC circuit layout, determining if a proximity criteria for the failing observation points is met, and identifying faults associated with the failing observation points that meet the proximity criteria; and including the identified faults in a fault candidate set.
摘要翻译：一种基于集成电路（IC）布局的物理布局选择故障候选的方法，其包括：识别IC布局中的故障观察点，确定IC电路布局中的故障观察点接近度几何，确定接近度准则满足故障观测点，识别符合接近度标准的故障观测点相关故障; 并在故障候选集中包括识别的故障。

6. 发明申请

US20090259983A1 METHODS FOR DESIGNING A PRODUCT CHIP A PRIORI FOR DESIGN SUBSETTING, FEATURE ANALYSIS, AND YIELD LEARNING 有权
标题翻译：设计产品芯片的设计方法，设计分析，特征分析和理论学习
公开(公告)号：US20090259983A1
公开(公告)日：2009-10-15
申请号：US12103217
申请日：2008-04-15
申请人： John M. Cohn , Leah M. Pastel , Gustavo E. Tellez
发明人： John M. Cohn , Leah M. Pastel , Gustavo E. Tellez
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F2217/12 , Y02P90/265
摘要： A method for designing a chip a priori for design subsetting, feature analysis, and yield learning. The method includes identifying a plurality of signal paths within a chip design that can be readily identified from chip fail data and removing a fraction of the plurality of signal paths that have physical design constraints to generate a subset of the plurality of signal paths. The method further includes constructing a physical implementation of each of the signal paths in the subset, identifying one or more signal paths in the subset that are not constructed consistently with the respective physical implementation, and removing those signal paths from the subset.
摘要翻译：一种用于设计子集，特征分析和产量学习的芯片设计方法。该方法包括识别可以从芯片故障数据容易地识别的芯片设计中的多个信号路径，并且去除具有物理设计约束以生成多个信号路径的子集的多个信号路径的一部分。该方法还包括构建子集中的每个信号路径的物理实现，识别子集中未与相应物理实现一致构造的一个或多个信号路径，以及从该子集中去除那些信号路径。

7. 发明授权

US06901542B2 Internal cache for on chip test data storage 失效
标题翻译：用于片内测试数据存储的内部缓存
公开(公告)号：US06901542B2
公开(公告)日：2005-05-31
申请号：US09927011
申请日：2001-08-09
申请人： Thomas W. Bartenstein , L. Owen Farnsworth, III , Douglas C. Heaberlin , Edward E. Horton, III , Leendert M. Huisman , Leah M. Pastel , Glen E. Richard , Raymond J. Rosner , Francis Woytowich
发明人： Thomas W. Bartenstein , L. Owen Farnsworth, III , Douglas C. Heaberlin , Edward E. Horton, III , Leendert M. Huisman , Leah M. Pastel , Glen E. Richard , Raymond J. Rosner , Francis Woytowich
IPC分类号： G11C29/26 , G01R31/3193 , G01R31/3177 , G01R31/3187
CPC分类号： G11C29/26
摘要： A method of testing a semiconductor device having a memory is disclosed. The method includes selecting a portion of the memory; testing the selected portion of the memory; designating the selected portion of the memory as a designated memory in response to an acceptable testing result; and storing data in the designated portion of the memory for retrieval at a later time. Provision for soft repair of the selected memory is made. Test data can be compressed before being stored in the designated memory.
摘要翻译：公开了一种测试具有存储器的半导体器件的方法。该方法包括选择存储器的一部分; 测试存储器的选定部分; 响应于可接受的测试结果，将存储器的所选部分指定为指定存储器; 并在稍后的时间将数据存储在存储器的指定部分中以进行检索。对所选择的存储器进行软修复。测试数据可以在存储在指定的存储器中之前进行压缩。

8. 发明授权

US06566681B2 Apparatus for assisting backside focused ion beam device modification 有权
标题翻译：用于辅助背侧聚焦离子束装置修改的装置
公开(公告)号：US06566681B2
公开(公告)日：2003-05-20
申请号：US09908925
申请日：2001-07-19
申请人： David E. Lackey , Theodore M. Levin , Leah M. Pastel
发明人： David E. Lackey , Theodore M. Levin , Leah M. Pastel
IPC分类号： H01L2358
CPC分类号： H01J37/3056 , H01J2237/304 , H01J2237/31737 , H01J2237/31742
摘要： An apparatus for assisting backside focused ion beam (FIB) device modification is disclosed. The apparatus for assisting backside FIB device modification includes an FIB device modification circuit and a control circuit. The FIB device modification circuit includes an input, an output, an FIB input pad, and an FIB output pad. The FIB device modification circuit allows the input to be electrically connected to the output. The control circuit, which is coupled to the FIB device modification circuit, may include a jumper and a cut. The control circuit is preferably located in a proximity of a backside of a substrate to allow the jumper and the cut to be modified by an FIB machine.
摘要翻译：公开了一种用于辅助背侧聚焦离子束（FIB）装置修改的装置。用于辅助背面FIB设备修改的设备包括FIB设备修改电路和控制电路。 FIB设备修改电路包括输入，输出，FIB输入焊盘和FIB输出焊盘。 FIB设备修改电路允许输入电连接到输出。耦合到FIB设备修改电路的控制电路可以包括跳线和切断。控制电路优选位于衬底的背面附近，以允许跳线和切口由FIB机器修改。

9. 发明申请

US20110137602A1 INSERTION OF FAULTS IN LOGIC MODEL USED IN SIMULATION 失效
标题翻译：在模拟中使用的逻辑模型中的故障插入
公开(公告)号：US20110137602A1
公开(公告)日：2011-06-09
申请号：US12633151
申请日：2009-12-08
申请人： Rao H. Desineni , Maroun Kassab , Mary P. Kusko , Leah M. Pastel
发明人： Rao H. Desineni , Maroun Kassab , Mary P. Kusko , Leah M. Pastel
IPC分类号： G01R31/14 , G06F17/50
CPC分类号： G06F17/5022 , G06F11/261 , G06F2217/70
摘要： A method of selecting fault candidates based on the physical layout of an Integrated Circuit (IC) layout, that includes, identifying failing observation points in an IC layout, determining the failing observation points proximity geometry in the IC circuit layout, determining if a proximity criteria for the failing observation points is met, and identifying faults associated with the failing observation points that meet the proximity criteria; and including the identified faults in a fault candidate set.
摘要翻译：一种基于集成电路（IC）布局的物理布局选择故障候选的方法，其包括：识别IC布局中的故障观察点，确定IC电路布局中的故障观察点接近度几何，确定接近度准则满足故障观测点，识别符合接近度标准的故障观测点相关故障; 并在故障候选集中包括识别的故障。

10. 发明授权

US08571299B2 Identifying defects 有权
标题翻译：识别缺陷
公开(公告)号：US08571299B2
公开(公告)日：2013-10-29
申请号：US12871039
申请日：2010-08-30
申请人： Mohammed F. Fayaz , Julie L. Lee , Leah M. Pastel , Maroun Kassab
发明人： Mohammed F. Fayaz , Julie L. Lee , Leah M. Pastel , Maroun Kassab
IPC分类号： G06K9/00
CPC分类号： G01N21/95607 , G01N2021/8864 , H01L22/12 , H01L22/20 , H01L2924/0002 , H01L2924/00
摘要： Identifying systematic defects in wafer processing including performing defect inspection of a plurality of wafers, identifying defects in each of the plurality of wafers as not being associated with a trivial and/or known root cause, determining a physical location on each wafer where each of the defects occurs and correlating the physical locations where each of the defects occurs with cell instances defined for those physical locations.
摘要翻译：识别晶片处理中的系统缺陷，包括执行多个晶片的缺陷检查，将多个晶片中的每一个中的缺陷识别为不与平凡和/或已知的根本原因相关联，确定每个晶片上的每个晶片上的物理位置发生缺陷，并将每个缺陷发生的物理位置与为这些物理位置定义的单元格实例相关联。

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