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1. 发明授权

US07895545B2 Methods for designing a product chip a priori for design subsetting, feature analysis, and yield learning 有权
标题翻译：设计子集，特征分析和产量学习的先验设计方法
公开(公告)号：US07895545B2
公开(公告)日：2011-02-22
申请号：US12103217
申请日：2008-04-15
申请人： John M. Cohn , Leah M. Pastel , Gustavo E. Tellez
发明人： John M. Cohn , Leah M. Pastel , Gustavo E. Tellez
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F2217/12 , Y02P90/265
摘要： A method for designing a chip a priori for design subsetting, feature analysis, and yield learning. The method includes identifying a plurality of signal paths within a chip design that can be readily identified from chip fail data and removing a fraction of the plurality of signal paths that have physical design constraints to generate a subset of the plurality of signal paths. The method further includes constructing a physical implementation of each of the signal paths in the subset, identifying one or more signal paths in the subset that are not constructed consistently with the respective physical implementation, and removing those signal paths from the subset.
摘要翻译：一种用于设计子集，特征分析和产量学习的芯片设计方法。该方法包括识别可以从芯片故障数据容易地识别的芯片设计中的多个信号路径，并且去除具有物理设计约束以生成多个信号路径的子集的多个信号路径的一部分。该方法还包括构建子集中的每个信号路径的物理实现，识别子集中未与相应物理实现一致构造的一个或多个信号路径，以及从该子集中去除那些信号路径。

2. 发明申请

US20090259983A1 METHODS FOR DESIGNING A PRODUCT CHIP A PRIORI FOR DESIGN SUBSETTING, FEATURE ANALYSIS, AND YIELD LEARNING 有权
标题翻译：设计产品芯片的设计方法，设计分析，特征分析和理论学习
公开(公告)号：US20090259983A1
公开(公告)日：2009-10-15
申请号：US12103217
申请日：2008-04-15
申请人： John M. Cohn , Leah M. Pastel , Gustavo E. Tellez
发明人： John M. Cohn , Leah M. Pastel , Gustavo E. Tellez
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F2217/12 , Y02P90/265
摘要： A method for designing a chip a priori for design subsetting, feature analysis, and yield learning. The method includes identifying a plurality of signal paths within a chip design that can be readily identified from chip fail data and removing a fraction of the plurality of signal paths that have physical design constraints to generate a subset of the plurality of signal paths. The method further includes constructing a physical implementation of each of the signal paths in the subset, identifying one or more signal paths in the subset that are not constructed consistently with the respective physical implementation, and removing those signal paths from the subset.
摘要翻译：一种用于设计子集，特征分析和产量学习的芯片设计方法。该方法包括识别可以从芯片故障数据容易地识别的芯片设计中的多个信号路径，并且去除具有物理设计约束以生成多个信号路径的子集的多个信号路径的一部分。该方法还包括构建子集中的每个信号路径的物理实现，识别子集中未与相应物理实现一致构造的一个或多个信号路径，以及从该子集中去除那些信号路径。

3. 发明申请

US20100023913A1 METHOD FOR IC WIRING YIELD OPTIMIZATION, INCLUDING WIRE WIDENING DURING AND AFTER ROUTING 有权
标题翻译： IC接线优化方法，包括在路由和之后的线路宽带化
公开(公告)号：US20100023913A1
公开(公告)日：2010-01-28
申请号：US12572297
申请日：2009-10-02
申请人： John M. Cohn , Jason D. Hibbeler , Gustavo E. Tellez
发明人： John M. Cohn , Jason D. Hibbeler , Gustavo E. Tellez
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： Disclosed are embodiments of a method, service, and computer program product for performing yield-aware IC routing for a design. The method performs an initial global routing which satisfies wiring congestion constraints. Next, the method performs wire spreading and wire widening on the global route, layer by layer, based on, for example, a quadratic congestion optimization. Following this, timing closure is performed on the global route using results of the wire spreading and wire widening. Post-routing wiring width and wire spreading adjustments are made using the critical area yield model. In addition, the method allows for the optimization of already-routed data.
摘要翻译：公开了用于为设计执行屈服感知IC路由的方法，服务和计算机程序产品的实施例。该方法执行满足布线拥塞约束的初始全局路由。接下来，该方法基于例如二次拥塞优化来逐层地在全局路由上执行线扩展和线拓宽。之后，使用电线扩展和线宽加工的结果，在全局路线上执行定时关闭。使用关键区域产量模型进行布线后布线宽度和布线调整。此外，该方法允许优化已经路由的数据。

4. 发明授权

US08230378B2 Method for IC wiring yield optimization, including wire widening during and after routing 有权
标题翻译： IC布线产量优化方法，包括布线期间和之后的线宽
公开(公告)号：US08230378B2
公开(公告)日：2012-07-24
申请号：US12572297
申请日：2009-10-02
申请人： John M. Cohn , Jason D. Hibbeler , Gustavo E. Tellez
发明人： John M. Cohn , Jason D. Hibbeler , Gustavo E. Tellez
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： Disclosed are embodiments of a method, service, and computer program product for performing yield-aware IC routing for a design. The method performs an initial global routing which satisfies wiring congestion constraints. Next, the method performs wire spreading and wire widening on the global route, layer by layer, based on, for example, a quadratic congestion optimization. Following this, timing closure is performed on the global route using results of the wire spreading and wire widening. Post-routing wiring width and wire spreading adjustments are made using the critical area yield model. In addition, the method allows for the optimization of already-routed data.
摘要翻译：公开了用于为设计执行屈服感知IC路由的方法，服务和计算机程序产品的实施例。该方法执行满足布线拥塞约束的初始全局路由。接下来，该方法基于例如二次拥塞优化来逐层地在全局路由上执行线扩展和线拓宽。之后，使用电线扩展和线宽加工的结果，在全局路线上执行定时关闭。使用关键区域产量模型进行布线后布线宽度和布线调整。此外，该方法允许优化已经路由的数据。

5. 发明授权

US07961932B2 Method and apparatus for manufacturing diamond shaped chips 有权
标题翻译：用于制造菱形芯片的方法和装置
公开(公告)号：US07961932B2
公开(公告)日：2011-06-14
申请号：US11865728
申请日：2007-10-01
申请人： Robert J. Allen , John M. Cohn , Scott W. Gould , Peter A. Habitz , Juergen Koehl , Gustavo E. Tellez , Ivan L. Wemple , Paul S. Zuchowski
发明人： Robert J. Allen , John M. Cohn , Scott W. Gould , Peter A. Habitz , Juergen Koehl , Gustavo E. Tellez , Ivan L. Wemple , Paul S. Zuchowski
IPC分类号： G06K9/00
CPC分类号： H01L27/0207
摘要： In a first aspect, an inventive apparatus for imaging a chip on a wafer includes a combined diamond chip image and kerf image having a plurality of sloped sides. The combined diamond chip image and kerf image includes a diamond chip image comprising a plurality of chip image rows that are parallel to at least one diagonal of the diamond chip image, and includes a kerf image adjacent to the diamond chip image. The kerf image comprises at least one kerf image row that is parallel to the at least one diagonal of the diamond chip image. The apparatus further includes a blocking material extending from the combined diamond chip image and kerf image to at least a periphery of an exposure field of a stepper. In a second aspect the imaging apparatus comprises an n-sided polygon-shaped combined chip image and kerf image. Also provided are inventive methods of manufacturing chips, and wafers manufactured in accordance with the inventive methods.
摘要翻译：在第一方面中，用于对晶片上的芯片进行成像的本发明的装置包括具有多个倾斜侧面的组合金刚石芯片图像和切口图像。组合的金刚石芯片图像和切口图像包括金刚石芯片图像，其包括与金刚石芯片图像的至少一个对角线平行的多个芯片图像行，并且包括与金刚石芯片图像相邻的切痕图像。切口图像包括平行于金刚石切片图像的至少一个对角线的至少一个切痕图像行。该装置还包括从组合的金刚石片图像和切痕图像延伸到步进器的曝光场的至少周边的阻挡材料。在第二方面，成像装置包括n侧多边形组合芯片图像和切口图像。还提供了制造芯片的创造性方法和根据本发明方法制造的晶片。

6. 发明授权

US07289659B2 Method and apparatus for manufacturing diamond shaped chips 有权
标题翻译：用于制造菱形芯片的方法和装置
公开(公告)号：US07289659B2
公开(公告)日：2007-10-30
申请号：US10250295
申请日：2003-06-20
申请人： Robert J. Allen , John M. Cohn , Scott W. Gould , Peter A. Habitz , Juergen Koehl , Gustavo E. Tellez , Ivan L. Wemple , Paul S. Zuchowski
发明人： Robert J. Allen , John M. Cohn , Scott W. Gould , Peter A. Habitz , Juergen Koehl , Gustavo E. Tellez , Ivan L. Wemple , Paul S. Zuchowski
IPC分类号： G06K9/00
CPC分类号： H01L27/0207
摘要： In a first aspect, an inventive apparatus for imaging a chip on a wafer includes a combined diamond chip image and kerf image having a plurality of sloped sides. The combined diamond chip image and kerf image includes a diamond chip image comprising a plurality of chip image rows that are parallel to at least one diagonal of the diamond chip image, and includes a kerf image adjacent to the diamond chip image. The kerf image comprises at least one kerf image row that is parallel to the at least one diagonal of the diamond chip image. The apparatus further includes a blocking material extending from the combined diamond chip image and kerf image to at least a periphery of an exposure field of a stepper. In a second aspect the imaging apparatus comprises an n-sided polygon-shaped combined chip image and kerf image. Also provided are inventive methods of manufacturing chips, and wafers manufactured in accordance with the inventive methods.
摘要翻译：在第一方面中，用于对晶片上的芯片进行成像的本发明的装置包括具有多个倾斜侧面的组合金刚石芯片图像和切口图像。组合的金刚石芯片图像和切口图像包括金刚石芯片图像，其包括与金刚石芯片图像的至少一个对角线平行的多个芯片图像行，并且包括与金刚石芯片图像相邻的切痕图像。切口图像包括平行于金刚石切片图像的至少一个对角线的至少一个切痕图像行。该装置还包括从组合的金刚石片图像和切痕图像延伸到步进器的曝光场的至少周边的阻挡材料。在第二方面，成像装置包括n侧多边形组合芯片图像和切口图像。还提供了制造芯片的创造性方法和根据本发明方法制造的晶片。

7. 发明授权

US07657859B2 Method for IC wiring yield optimization, including wire widening during and after routing 失效
标题翻译： IC布线产量优化方法，包括布线期间和之后的线宽
公开(公告)号：US07657859B2
公开(公告)日：2010-02-02
申请号：US11275076
申请日：2005-12-08
申请人： John M. Cohn , Jason D. Hibbeler , Gustavo E. Tellez
发明人： John M. Cohn , Jason D. Hibbeler , Gustavo E. Tellez
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： Disclosed are embodiments of a method, service, and computer program product for performing yield-aware IC routing for a design. The method performs an initial global routing which satisfies wiring congestion constraints. Next, the method performs wire spreading and wire widening on the global route, layer by layer, based on, for example, a quadratic congestion optimization. Following this, timing closure is performed on the global route using results of the wire spreading and wire widening. Post-routing wiring width and wire spreading adjustments are made using the critical area yield model. In addition, the method allows for the optimization of already-routed data.
摘要翻译：公开了用于为设计执行屈服感知IC路由的方法，服务和计算机程序产品的实施例。该方法执行满足布线拥塞约束的初始全局路由。接下来，该方法基于例如二次拥塞优化来逐层地在全局路由上执行线扩展和线拓宽。之后，使用电线扩展和线宽加工的结果，在全局路线上执行定时关闭。使用关键区域产量模型进行布线后布线宽度和布线调整。此外，该方法允许优化已经路由的数据。

8. 发明授权

US07644327B2 System and method of providing error detection and correction capability in an integrated circuit using redundant logic cells of an embedded FPGA 失效
标题翻译：使用嵌入式FPGA的冗余逻辑单元在集成电路中提供错误检测和校正能力的系统和方法
公开(公告)号：US07644327B2
公开(公告)日：2010-01-05
申请号：US12049166
申请日：2008-03-14
申请人： John M. Cohn , Christopher B. Reynolds , Sebastian T. Ventrone , Paul S. Zuchowski
发明人： John M. Cohn , Christopher B. Reynolds , Sebastian T. Ventrone , Paul S. Zuchowski
IPC分类号： G01R31/28
CPC分类号： G01R31/318519 , G01R31/318558 , G06F11/261 , H03K19/00392
摘要： A system and method of providing error detection and correction capability in an IC using redundant logic cells and an embedded field programmable gate array (FPGA). The system and method provide error correction (EC) to enable a defective logic function implemented within an IC chip design to be replaced, wherein at least one embedded FPGA is provided in the IC chip to perform a logic function. If a defective logic function is identified in the IC design, the embedded FPGA is programmed to correctly perform the defective logic function. All inputs in an input cone of logic of the defective logic function are identified and are directed into the embedded FPGA, such that the embedded FPGA performs the logic function of the defective logic function. All outputs in an output cone of logic of the defective logic function are identified, and the output of the FPGA is directed to the output cone of logic of the defective logic unction, such that logic EC is provided within the embedded FPGA structure of the IC chip.
摘要翻译：一种使用冗余逻辑单元和嵌入式现场可编程门阵列（FPGA）在IC中提供错误检测和校正能力的系统和方法。该系统和方法提供纠错（EC），以使得能够替换在IC芯片设计中实现的故障逻辑功能，其中在IC芯片中提供至少一个嵌入式FPGA以执行逻辑功能。如果在IC设计中识别到故障逻辑功能，嵌入式FPGA将被编程为正确执行故障逻辑功能。识别故障逻辑功能逻辑输入锥中的所有输入，并将其引导到嵌入式FPGA中，使嵌入式FPGA执行故障逻辑功能的逻辑功能。识别有缺陷逻辑功能的逻辑输出锥中的所有输出，并将FPGA的输出引导到故障逻辑逻辑的逻辑输出锥，使得在IC的嵌入式FPGA结构内提供逻辑EC 芯片。

9. 发明授权

US07620931B2 Method of adding fabrication monitors to integrated circuit chips 失效
标题翻译：将制造监控器添加到集成电路芯片的方法
公开(公告)号：US07620931B2
公开(公告)日：2009-11-17
申请号：US11859890
申请日：2007-09-24
申请人： James W. Adkisson , Greg Bazan , John M. Cohn , Matthew S. Grady , Thomas G. Sopchak , David P. Vallett
发明人： James W. Adkisson , Greg Bazan , John M. Cohn , Matthew S. Grady , Thomas G. Sopchak , David P. Vallett
IPC分类号： G06F17/50
CPC分类号： H01L22/20 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit, a method and a system for designing and a method fabricating the integrated circuit. The method including: (a) generating a photomask level design of an integrated circuit design of the integrated circuit, the photomask level design comprising a multiplicity of integrated circuit element shapes; (b) designating regions of the photomask level design between adjacent integrated circuit element shapes, the designated regions large enough to require placement of fill shapes between the adjacent integrated circuit elements based on fill shape rules, the fill shapes not required for the operation of the integrated circuit; and (c) placing one or more monitor structure shapes of a monitor structure in at least one of the designated regions, the monitor structure not required for the operation of the integrated circuit.
摘要翻译：一种用于设计的集成电路，方法和系统以及制造集成电路的方法。该方法包括：（a）生成集成电路的集成电路设计的光掩模级设计，光掩模级设计包括多个集成电路元件形状; （b）指定相邻集成电路元件形状之间的光掩模级设计的区域，指定区域足够大以至于基于填充形状规则需要在相邻集成电路元件之间放置填充形状，集成电路; 以及（c）将监视器结构的一个或多个监视器结构形状放置在指定区域中的至少一个中，该集成电路的操作不需要监视器结构。

10. 发明申请

US20080163016A1 SYSTEM AND METHOD OF PROVIDING ERROR DETECTION AND CORRECTION CAPABILITY IN AN INTEGRATED CIRCUIT USING REDUNDANT LOGIC CELLS OF AN EMBEDDED FPGA 失效
标题翻译：使用嵌入式FPGA的冗余逻辑单元在集成电路中提供错误检测和校正能力的系统和方法
公开(公告)号：US20080163016A1
公开(公告)日：2008-07-03
申请号：US12049166
申请日：2008-03-14
申请人： John M. Cohn , Christopher B. Reynolds , Sebastian T. Ventrone , Paul S. Zuchowski
发明人： John M. Cohn , Christopher B. Reynolds , Sebastian T. Ventrone , Paul S. Zuchowski
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/318519 , G01R31/318558 , G06F11/261 , H03K19/00392
摘要： A system and method of providing error detection and correction capability in an IC using redundant logic cells and an embedded field programmable gate array (FPGA). The system and method provide error correction (EC) to enable a defective logic function implemented within an IC chip design to be replaced, wherein at least one embedded FPGA is provided in the IC chip to perform a logic function. If a defective logic function is identified in the IC design, the embedded FPGA is programmed to correctly perform the defective logic function. All inputs in an input cone of logic of the defective logic function are identified and are directed into the embedded FPGA, such that the embedded FPGA performs the logic function of the defective logic function. All outputs in an output cone of logic of the defective logic function are identified, and the output of the FPGA is directed to the output cone of logic of the defective logic unction, such that logic EC is provided within the embedded FPGA structure of the IC chip.
摘要翻译：一种使用冗余逻辑单元和嵌入式现场可编程门阵列（FPGA）在IC中提供错误检测和校正能力的系统和方法。该系统和方法提供纠错（EC），以使得能够替换在IC芯片设计中实现的故障逻辑功能，其中在IC芯片中提供至少一个嵌入式FPGA以执行逻辑功能。如果在IC设计中识别到故障逻辑功能，嵌入式FPGA将被编程为正确执行故障逻辑功能。识别故障逻辑功能逻辑输入锥中的所有输入，并将其引导到嵌入式FPGA中，使嵌入式FPGA执行故障逻辑功能的逻辑功能。识别有缺陷逻辑功能的逻辑输出锥中的所有输出，并将FPGA的输出引导到故障逻辑逻辑的逻辑输出锥，使得在IC的嵌入式FPGA结构内提供逻辑EC 芯片。

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