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1. 发明授权

US08541826B2 Memory array structure and method for forming the same 有权
标题翻译：存储器阵列结构及其形成方法
公开(公告)号：US08541826B2
公开(公告)日：2013-09-24
申请号：US13576944
申请日：2012-07-10
申请人： Liyang Pan , Haozhi Ma
发明人： Liyang Pan , Haozhi Ma
IPC分类号： H01L27/108 , H01L21/8239
CPC分类号： H01L27/10876 , H01L27/10882
摘要： A memory array structure and a method for forming the same are provided. The memory array structure comprises: a substrate; a plurality of memory cells, each memory cell including a vertical transistor, of which a gate structure is formed in a first trench extending in a first direction; a plurality of word lines in the first direction, each word line formed in the first trench; a plurality of bit lines in a second direction, each bit line formed in lower sides of a semiconductor pillars; a plurality of body lines in the first direction, each body line having a first portion formed on the gate electrodes and a second portion covering a part of a top surface of semiconductor pillar for providing a substrate contact to vertical channel regions; and a plurality of data storage device contacts.
摘要翻译：提供了一种存储器阵列结构及其形成方法。存储器阵列结构包括：衬底; 多个存储单元，每个存储单元包括垂直晶体管，其栅极结构形成在沿第一方向延伸的第一沟槽中; 在第一方向上的多个字线，形成在第一沟槽中的每个字线; 在第二方向上的多个位线，每个位线形成在半导体柱的下侧; 在第一方向上的多个体线，每个主体线具有形成在栅电极上的第一部分和覆盖半导体柱的顶表面的一部分的第二部分，用于向垂直沟道区提供衬底接触; 和多个数据存储装置触点。

2. 发明授权

US08748934B2 Vertical selection transistor, memory cell, and three-dimensional memory array structure and method for fabricating the same 有权
标题翻译：垂直选择晶体管，存储单元和三维存储器阵列结构及其制造方法
公开(公告)号：US08748934B2
公开(公告)日：2014-06-10
申请号：US13520166
申请日：2012-03-12
申请人： Liyang Pan , Fang Yuan
发明人： Liyang Pan , Fang Yuan
IPC分类号： H01L29/08 , H01L27/24 , H01L21/70 , H01L29/78
CPC分类号： H01L27/24 , H01L21/70 , H01L27/2445 , H01L27/2481 , H01L29/04 , H01L29/66348 , H01L29/7394 , H01L29/7397 , H01L29/7827 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/141 , H01L45/145 , H01L45/146 , H01L45/1675
摘要： The present disclosure discloses a vertical selection transistor, a memory cell having the vertical selection transistor, a three-dimensional memory array structure and a method for fabricating the three-dimensional memory array structure. The vertical selection transistor comprises: an upper electrode; a lower electrode; a first semiconductor layer, a second semiconductor layer, a third semiconductor layer and a fourth semiconductor layer vertically stacked between the lower electrode and the upper electrode; and a gate stack formed on a side of the second semiconductor layer, in which the first semiconductor layer and the third semiconductor layer are first type doped layers, the second semiconductor layer and the fourth semiconductor layer are second type doped layers, and a doping concentration of the second semiconductor layer is lower than that of the first semiconductor layer or that of the third semiconductor layer respectively.
摘要翻译：本公开公开了一种垂直选择晶体管，具有垂直选择晶体管的存储单元，三维存储器阵列结构和用于制造三维存储器阵列结构的方法。垂直选择晶体管包括：上电极; 下电极第一半导体层，第二半导体层，第三半导体层和垂直堆叠在下电极和上电极之间的第四半导体层; 以及形成在所述第二半导体层的一侧的栅堆叠，其中所述第一半导体层和所述第三半导体层是第一掺杂层，所述第二半导体层和所述第四半导体层是第二掺杂层，并且掺杂浓度分别低于第一半导体层或第三半导体层的厚度。

3. 发明申请

US20130161730A1 MEMORY ARRAY STRUCTURE AND METHOD FOR FORMING THE SAME 有权
标题翻译：存储器阵列结构及其形成方法
公开(公告)号：US20130161730A1
公开(公告)日：2013-06-27
申请号：US13576944
申请日：2012-07-10
申请人： Liyang Pan , Haozhi Ma
发明人： Liyang Pan , Haozhi Ma
IPC分类号： H01L27/088 , H01L21/336
CPC分类号： H01L27/10876 , H01L27/10882
摘要： A memory array structure and a method for forming the same are provided. The memory array structure comprises: a substrate; a plurality of memory cells, each memory cell including a vertical transistor, of which a gate structure is formed in a first trench extending in a first direction; a plurality of word lines in the first direction, each word line formed in the first trench; a plurality of bit lines in a second direction, each bit line formed in lower sides of a semiconductor pillars; a plurality of body lines in the first direction, each body line having a first portion formed on the gate electrodes and a second portion covering a part of a top surface of semiconductor pillar for providing a substrate contact to vertical channel regions; and a plurality of data storage device contacts.
摘要翻译：提供了一种存储器阵列结构及其形成方法。存储器阵列结构包括：衬底; 多个存储单元，每个存储单元包括垂直晶体管，其栅极结构形成在沿第一方向延伸的第一沟槽中; 在第一方向上的多个字线，形成在第一沟槽中的每个字线; 在第二方向上的多个位线，每个位线形成在半导体柱的下侧; 在第一方向上的多个体线，每个主体线具有形成在栅电极上的第一部分和覆盖半导体柱的顶表面的一部分的第二部分，用于向垂直沟道区提供衬底接触; 和多个数据存储装置触点。

4. 发明申请

US20120317345A1 WEAR LEVELING METHOD AND APPARATUS 有权
标题翻译：磨损方法和装置
公开(公告)号：US20120317345A1
公开(公告)日：2012-12-13
申请号：US13519230
申请日：2012-03-15
申请人： Liyang Pan , Chen Tang
发明人： Liyang Pan , Chen Tang
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G06F2212/7211
摘要： The present invention discloses a wear leveling method; the method determines a pool mask for each physical block based on an erase number of each physical block. For different erase numbers, masks of the physical blocks are determined as cool pool mask CPM, normal pool mask NPM or hot pool mask HPM. When the pool mask of one physical block is changed from NPM to HPM, data of any physical block of which the pool mask is CPM is copied to the physical block of which the pool mask is HPM, and the physical block of which the pool mask is CPM is recycled as a garbage block. The present invention discloses a wear leveling apparatus, the method and apparatus can reduce additional wear caused by the wear leveling.
摘要翻译：本发明公开了一种磨损平整方法; 该方法基于每个物理块的擦除次数确定每个物理块的池掩码。对于不同的擦除号码，物理块的掩码被确定为酷池掩码CPM，普通池掩码NPM或热池掩码HPM。当一个物理块的池掩码从NPM更改为HPM时，池掩码为CPM的任何物理块的数据将复制到池掩码为HPM的物理块，并且池掩码的物理块是将CPM作为垃圾块进行回收。本发明公开了一种耐磨均衡装置，该方法和装置可以减少由磨损平整引起的附加磨损。

5. 发明申请

US20130069141A1 VERTICALLY FOLDABLE MEMORY ARRAY STRUCTURE 有权
标题翻译：垂直折叠存储器阵列结构
公开(公告)号：US20130069141A1
公开(公告)日：2013-03-21
申请号：US13520155
申请日：2011-06-27
申请人： Liyang Pan , Fang Yuan
发明人： Liyang Pan , Fang Yuan
IPC分类号： H01L29/792
CPC分类号： H01L29/792 , G11C5/02 , G11C5/063 , G11C8/14 , G11C16/0466 , G11C16/0483 , H01L27/0688 , H01L27/11582 , H01L29/7926
摘要： A vertically foldable memory array structure is provided, comprising: a memory module distributed in columns and rows, comprising: a drain selection transistor; a bottom connecting line and a source selection transistor; and a plurality of memory cell transistors connected between the drain selection transistor and the bottom connecting line and between the source selection transistor and the bottom connecting line, a drain of each drain selection transistor is connected to a bit line, a drain of a drain selection transistor in a Mth vertically foldable memory module in a Nth column and a source of a source selection transistor in a (M−1)th memory module in a (N+1)th column are connected to a same bit line, gates of the drain selection transistors and the source selection transistors in all the memory modules in the Nth column are connected to a same drain selection line and a same source selection line.
摘要翻译：提供了一种可垂直折叠的存储器阵列结构，包括：以列和行分布的存储器模块，包括：漏极选择晶体管; 底部连接线和源极选择晶体管; 连接在漏极选择晶体管和底部连接线之间以及源极选择晶体管和底部连接线之间的多个存储单元晶体管，每个漏极选择晶体管的漏极连接到位线，漏极选择的漏极在第N列中的第M个垂直折叠存储器模块中的晶体管和第（N + 1）列中的第（M-1）个存储器模块中的源选择晶体管的源极连接到相同的位线，第N列的所有存储器模块中的漏极选择晶体管和源极选择晶体管连接到相同的漏极选择线和相同的源极选择线。

6. 发明授权

US09405670B2 Wear leveling method and apparatus 有权
标题翻译：磨损平整方法和装置
公开(公告)号：US09405670B2
公开(公告)日：2016-08-02
申请号：US13519230
申请日：2012-03-15
申请人： Liyang Pan , Chen Tang
发明人： Liyang Pan , Chen Tang
IPC分类号： G06F13/00 , G06F12/02
CPC分类号： G06F12/0246 , G06F2212/7211
摘要： The present invention discloses a wear leveling method; the method determines a pool mask for each physical block based on an erase number of each physical block. For different erase numbers, masks of the physical blocks are determined as cool pool mask CPM, normal pool mask NPM or hot pool mask HPM. When the pool mask of one physical block is changed from NPM to HPM, data of any physical block of which the pool mask is CPM is copied to the physical block of which the pool mask is HPM, and the physical block of which the pool mask is CPM is recycled as a garbage block. The present invention discloses a wear leveling apparatus, the method and apparatus can reduce additional wear caused by the wear leveling.
摘要翻译：本发明公开了一种磨损平整方法; 该方法基于每个物理块的擦除次数确定每个物理块的池掩码。对于不同的擦除号码，物理块的掩码被确定为酷池掩码CPM，普通池掩码NPM或热池掩码HPM。当一个物理块的池掩码从NPM更改为HPM时，池掩码为CPM的任何物理块的数据被复制到池掩码为HPM的物理块，并且其掩码的物理块是将CPM作为垃圾块进行回收。本发明公开了一种耐磨均衡装置，该方法和装置可以减少由磨损平整引起的附加磨损。

7. 发明授权

US08958246B2 Vertically foldable memory array structure 有权
标题翻译：垂直可折叠存储器阵列结构
公开(公告)号：US08958246B2
公开(公告)日：2015-02-17
申请号：US13520155
申请日：2011-06-27
申请人： Liyang Pan , Fang Yuan
发明人： Liyang Pan , Fang Yuan
IPC分类号： G11C11/34 , H01L27/088 , H01L29/792 , G11C5/02 , G11C5/06 , G11C8/14 , G11C16/04 , H01L27/06 , H01L27/115
CPC分类号： H01L29/792 , G11C5/02 , G11C5/063 , G11C8/14 , G11C16/0466 , G11C16/0483 , H01L27/0688 , H01L27/11582 , H01L29/7926
摘要： A vertically foldable memory array structure is provided, comprising: a memory module distributed in columns and rows, comprising: a drain selection transistor; a bottom connecting line and a source selection transistor; and a plurality of memory cell transistors connected between the drain selection transistor and the bottom connecting line and between the source selection transistor and the bottom connecting line, a drain of each drain selection transistor is connected to a bit line, a drain of a drain selection transistor in a Mth vertically foldable memory module in a Nth column and a source of a source selection transistor in a (M−1)th memory module in a (N+1)th column are connected to a same bit line, gates of the drain selection transistors and the source selection transistors in all the memory modules in the Nth column are connected to a same drain selection line and a same source selection line.
摘要翻译：提供了一种可垂直折叠的存储器阵列结构，包括：以列和行分布的存储器模块，包括：漏极选择晶体管; 底部连接线和源极选择晶体管; 连接在漏极选择晶体管和底部连接线之间以及源极选择晶体管和底部连接线之间的多个存储单元晶体管，每个漏极选择晶体管的漏极连接到位线，漏极选择的漏极在第N列中的第M个垂直折叠存储器模块中的晶体管和第（N + 1）列中的第（M-1）个存储器模块中的源选择晶体管的源极连接到相同的位线，第N列的所有存储器模块中的漏极选择晶体管和源极选择晶体管连接到相同的漏极选择线和相同的源极选择线。

8. 发明申请

US20130207067A1 VERTICAL SELECTION TRANSISTOR, MEMORY CELL, AND THREE-DIMENSIONAL MEMORY ARRAY STRUCTURE AND METHOD FOR FABRICATING THE SAME 有权
标题翻译：垂直选择晶体管，存储单元和三维存储器阵列结构及其制造方法
公开(公告)号：US20130207067A1
公开(公告)日：2013-08-15
申请号：US13520166
申请日：2012-03-12
申请人： Liyang Pan , Fang Yuan
发明人： Liyang Pan , Fang Yuan
IPC分类号： H01L27/24 , H01L21/70 , H01L29/78
CPC分类号： H01L27/24 , H01L21/70 , H01L27/2445 , H01L27/2481 , H01L29/04 , H01L29/66348 , H01L29/7394 , H01L29/7397 , H01L29/7827 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/141 , H01L45/145 , H01L45/146 , H01L45/1675
摘要： The present disclosure discloses a vertical selection transistor, a memory cell having the vertical selection transistor, a three-dimensional memory array structure and a method for fabricating the three-dimensional memory array structure. The vertical selection transistor comprises: an upper electrode; a lower electrode; a first semiconductor layer, a second semiconductor layer, a third semiconductor layer and a fourth semiconductor layer vertically stacked between the lower electrode and the upper electrode; and a gate stack formed on a side of the second semiconductor layer, in which the first semiconductor layer and the third semiconductor layer are first type doped layers, the second semiconductor layer and the fourth semiconductor layer are second type doped layers, and a doping concentration of the second semiconductor layer is lower than that of the first semiconductor layer or that of the third semiconductor layer respectively.
摘要翻译：本公开公开了一种垂直选择晶体管，具有垂直选择晶体管的存储单元，三维存储器阵列结构和用于制造三维存储器阵列结构的方法。垂直选择晶体管包括：上电极; 下电极第一半导体层，第二半导体层，第三半导体层和垂直堆叠在下电极和上电极之间的第四半导体层; 以及形成在所述第二半导体层的一侧的栅堆叠，其中所述第一半导体层和所述第三半导体层是第一掺杂层，所述第二半导体层和所述第四半导体层是第二掺杂层，并且掺杂浓度分别低于第一半导体层或第三半导体层的厚度。

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