专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06912624B2 Method and system for exclusive two-level caching in a chip-multiprocessor 有权
标题翻译：芯片多处理器专用二级缓存的方法和系统
公开(公告)号：US06912624B2
公开(公告)日：2005-06-28
申请号：US10769824
申请日：2004-02-02
申请人： Luiz Andre Barroso , Kourosh Gharachorloo , Andreas Nowatzyk
发明人： Luiz Andre Barroso , Kourosh Gharachorloo , Andreas Nowatzyk
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0826 , G06F12/0811 , G06F2212/621
摘要： To maximize the effective use of on-chip cache, a method and system for exclusive two-level caching in a chip-multiprocessor are provided. The exclusive two-level caching in accordance with the present invention involves method relaxing the inclusion requirement in a two-level cache system in order to form an exclusive cache hierarchy. Additionally, the exclusive two-level caching involves providing a first-level tag-state structure in a first-level cache of the two-level cache system. The first tag-state structure has state information. The exclusive two-level caching also involves maintaining in a second-level cache of the two-level cache system a duplicate of the first-level tag-state structure and extending the state information in the duplicate of the first tag-state structure, but not in the first-level tag-state structure itself, to include an owner indication. The exclusive two-level caching further involves providing in the second-level cache a second tag-state structure so that a simultaneous lookup at the duplicate of the first tag-state structure and the second tag-state structure is possible. Moreover, the exclusive two-level caching involves associating a single owner with a cache line at any given time of its lifetime in the chip-multiprocessor.
摘要翻译：为了最大限度地有效利用片上高速缓存，提供了一种用于芯片多处理器中独占二级缓存的方法和系统。根据本发明的独有的两级缓存涉及在二级缓存系统中放宽包含要求的方法，以便形成专用高速缓存层级。此外，独占的两级缓存涉及在二级缓存系统的一级缓存中提供一级标签状态结构。第一个标签状态结构具有状态信息。专有的两级缓存还涉及在二级缓存系统的二级缓存中维护第一级标签状态结构的副本，并扩展第一标签状态结构的副本中的状态信息，但是不在第一级标签状态结构本身，包括所有者指示。专用的两级缓存进一步包括在第二级缓存中提供第二标签状态结构，使得在第一标签状态结构和第二标签状态结构的副本处的同时查找是可能的。此外，独占的两级缓存涉及在单芯片多处理器的任何给定的生命周期将单个所有者与缓存线相关联。

2. 发明授权

US06725334B2 Method and system for exclusive two-level caching in a chip-multiprocessor 有权
公开(公告)号：US06725334B2
公开(公告)日：2004-04-20
申请号：US09877530
申请日：2001-06-08
申请人： Luiz Andre Barroso , Kourosh Gharachorloo , Andreas Nowatzyk
发明人： Luiz Andre Barroso , Kourosh Gharachorloo , Andreas Nowatzyk
IPC分类号： G06F1200
CPC分类号： G06F12/0826 , G06F12/0811 , G06F2212/621
摘要： To maximize the effective use of on-chip cache, a method and system for exclusive two-level caching in a chip-multiprocessor are provided. The exclusive two-level caching in accordance with the present invention involves method relaxing the inclusion requirement in a two-level cache system in order to form an exclusive cache hierarchy. Additionally, the exclusive two-level caching involves providing a first-level tag-state structure in a first-level cache of the two-level cache system. The first tag-state structure has state information. The exclusive two-level caching also involves maintaining in a second-level cache of the two-level cache system a duplicate of the first-level tag-state structure and extending the state information in the duplicate of the first tag-state structure, but not in the first-level tag-state structure itself, to include an owner indication. The exclusive two-level caching further involves providing in the second-level cache a second tag-state structure so that a simultaneous lookup at the duplicate of the first tag-state structure and the second tag-state structure is possible. Moreover, the exclusive two-level caching involves associating a single owner with a cache line at any given time of its lifetime in the chip-multiprocessor.

3. 发明授权

US06748498B2 Scalable multiprocessor system and cache coherence method implementing store-conditional memory transactions while an associated directory entry is encoded as a coarse bit vector 失效
标题翻译：可扩展的多处理器系统和缓存一致性方法实现存储条件存储器事务，而相关联的目录条目被编码为粗位向量
公开(公告)号：US06748498B2
公开(公告)日：2004-06-08
申请号：US10042053
申请日：2002-01-07
申请人： Kourosh Gharachorloo , Luiz Andre Barroso , Mosur K. Ravishankar , Robert J. Stets , Daniel J. Scales
发明人： Kourosh Gharachorloo , Luiz Andre Barroso , Mosur K. Ravishankar , Robert J. Stets , Daniel J. Scales
IPC分类号： G06F1200
CPC分类号： G06F12/0826 , G06F12/0828 , G06F2212/621 , Y10S707/99952
摘要： A system including a plurality of processor nodes is configured to execute a cache coherence protocol that avoids the use of negative acknowledgments and ordering requirements on the underlying transaction-message interconnect/network, and implements store-conditional memory transactions. A store-conditional memory transaction succeeds if a directory tracking the state of a memory line of information unambiguously indicates that the requesting node is the exclusive owner of the memory line, if the directory ambiguously indicates that the requesting node is sharing the memory line and the requesting node is in fact sharing the memory line, or if the directory unambiguously indicates that the requesting node is sharing the memory line. The store-conditional memory transaction fails if the directory unambiguously indicates that the requesting node is not sharing the memory line, or if the directory ambiguously indicates that the requesting node may be sharing the memory line and the requesting node is in fact not sharing the memory line.
摘要翻译：包括多个处理器节点的系统被配置为执行高速缓存一致性协议，其避免对底层事务消息互连/网络使用否定确认和排序要求，并且实现存储条件存储器事务。如果跟踪存储器线的状态的目录明确地指示请求节点是存储器线的专有所有者，则存储条件存储器事务成功，如果目录模糊地指示请求节点正在共享存储器线，并且请求节点实际上共享内存线，或者如果目录明确地指示请求节点正在共享存储器线。如果目录明确地指示请求节点不共享存储器线路，或者如果目录模糊地指示请求节点可能共享存储器线且请求节点实际上不共享存储器，则存储条件存储器事务将失败线。

4. 发明授权

US06738868B2 System for minimizing directory information in scalable multiprocessor systems with logically independent input/output nodes 失效
标题翻译：用于在具有逻辑独立的输入/输出节点的可扩展多处理器系统中最小化目录信息的系统
公开(公告)号：US06738868B2
公开(公告)日：2004-05-18
申请号：US10042035
申请日：2002-01-07
申请人： Kourosh Gharachorloo , Luiz Andre Barroso , Daniel J. Scales
发明人： Kourosh Gharachorloo , Luiz Andre Barroso , Daniel J. Scales
IPC分类号： G06F1200
CPC分类号： G06F12/0826 , G06F12/0828 , G06F2212/621
摘要： A system of scalable shared-memory multiprocessors includes processor nodes and I/O nodes. The I/O nodes connect I/O devices directly to an interconnection network of a system of scalable shared-memory multiprocessors. Each node of the system includes an interface to a local memory subsystem, a memory cache and a protocol engine. The local memory subsystem stores memory lines of information and a directory. Each entry in the directory stores sharing information concerning a memory line of information stored in the local memory subsystem. The protocol engine in each I/O node is configured to limit to a predefined period of time any sharing of a memory line of information from the memory subsystem of any other node. The protocol engine in the home node of the memory line is configured to identify only nodes other than I/O nodes that are sharing the memory line of information. In one embodiment, I/O nodes that share the memory line of information are not identified in the directory entry of the memory line, and instead are represented by a count field, which indicates how many I/O nodes share the memory line of information.
摘要翻译：可扩展共享存储器多处理器的系统包括处理器节点和I / O节点。 I / O节点将I / O设备直接连接到可扩展共享存储器多处理器系统的互连网络。系统的每个节点包括到本地存储器子系统的接口，存储器高速缓存和协议引擎。本地存储器子系统存储信息的存储线和目录。目录中的每个条目存储关于存储在本地存储器子系统中的信息的存储器线的共享信息。每个I / O节点中的协议引擎被配置为限制来自任何其他节点的存储器子系统的信息的存储器线的任何共享的预定时间段。存储器线路的家庭节点中的协议引擎被配置为仅识别正在共享信息的存储器线的I / O节点之外的节点。在一个实施例中，共享存储器信息线的I / O节点不在存储器线的目录条目中标识，而是由计数字段表示，计数字段指示有多少个I / O节点共享信息的存储器线。

5. 发明授权

US06640287B2 Scalable multiprocessor system and cache coherence method incorporating invalid-to-dirty requests 失效
公开(公告)号：US06640287B2
公开(公告)日：2003-10-28
申请号：US10042009
申请日：2002-01-07
申请人： Kourosh Gharachorloo , Luiz Andre Barroso , Mosur Kumaraswamy Ravishankar , Robert J. Stets , Daniel J. Scales
发明人： Kourosh Gharachorloo , Luiz Andre Barroso , Mosur Kumaraswamy Ravishankar , Robert J. Stets , Daniel J. Scales
IPC分类号： G06F1200
CPC分类号： G06F12/0826 , G06F12/0828 , G06F2212/621
摘要： An invalid-to-dirty request permits a transition from an invalid memory state to a dirty state without requiring an up-to-date copy of the memory. The present invention is a system for supporting invalid-to-dirty memory transactions in an aggressive cache coherence protocol that minimizes directory entry locking. The nodes of a multiprocessor system each include a protocol engine that is configured to implement a distinct invalidation request that corresponds to an invalid-to-dirty memory transaction. If node O receives this distinct invalidation request while waiting for a response to an outstanding request for exclusive ownership, the protocol engine of node O is configured to treat the distinct invalidation request as applying to the memory line of information that is the subject of the outstanding request for exclusive ownership. Furthermore, if the node O receives a normal invalidation request, while it has an outstanding exclusive request, the invalidation request applies to a previous copy of the memory line of information held by the node N and therefore the protocol engine of node O is configured to ignore the normal invalidation request in this circumstance.

6. 发明授权

US10339227B1 Data center design 有权
公开(公告)号：US10339227B1
公开(公告)日：2019-07-02
申请号：US12060211
申请日：2008-03-31
申请人： Andrew B. Carlson , Jimmy Clidaras , William Hamburgen , Wolf-Dietrich Weber , Xiaobo Fan , Luiz Andre Barroso
发明人： Andrew B. Carlson , Jimmy Clidaras , William Hamburgen , Wolf-Dietrich Weber , Xiaobo Fan , Luiz Andre Barroso
IPC分类号： G06F17/50 , G06F1/26 , H05K7/20
摘要： A method of designing a data center can include determining a design power density, determining an oversubscription ratio, and determining a spatial layout of the data center using the design power density and the oversubscription ratio. The design power density can be in units of power per unit length.

7. 发明授权

US08621248B1 Load control in a data center 有权
标题翻译：在数据中心进行负载控制
公开(公告)号：US08621248B1
公开(公告)日：2013-12-31
申请号：US13101096
申请日：2011-05-04
申请人： Wolf-Dietrich Weber , Xiaobo Fan , Luiz Andre Barroso
发明人： Wolf-Dietrich Weber , Xiaobo Fan , Luiz Andre Barroso
IPC分类号： G06F1/00
CPC分类号： G06F17/5009 , G06F1/00 , G06F1/3206 , G06F9/5094 , Y02D10/22
摘要： A method of controlling power usage in a data center includes monitoring a power usage of a plurality of computers in the data center, generating a signal indicating that the power usage is within a threshold of a maximum power capacity, and in response to the signal, adjusting performance of at least one computer in the plurality of computers.
摘要翻译：一种控制数据中心的电力使用的方法包括监视数据中心中的多台计算机的电力使用情况，产生指示电力使用量在最大功率容量的阈值内的信号，并且响应于该信号，调整所述多个计算机中的至少一台计算机的性能。

8. 发明授权

US08601287B1 Computer and data center load determination 有权
标题翻译：计算机和数据中心负载确定
公开(公告)号：US08601287B1
公开(公告)日：2013-12-03
申请号：US12134509
申请日：2008-06-06
申请人： Wolf-Dietrich Weber , Xiaobo Fan , Luiz Andre Barroso
发明人： Wolf-Dietrich Weber , Xiaobo Fan , Luiz Andre Barroso
IPC分类号： G06F1/00
CPC分类号： G06F17/5009 , G06F1/00 , G06F1/3206 , G06F9/5094 , Y02D10/22
摘要： A method for use in deploying computers into a data center includes calculating in a computer an expected peak power draw for a plurality of computers. The expected peak power draw for the plurality of computers is less than a sum of individual expected peak power draws for each computer from the plurality of computers.
摘要翻译：用于将计算机部署到数据中心中的方法包括在计算机中计算多个计算机的预期峰值功率消耗。多个计算机的预期峰值功率消耗小于来自多个计算机的每台计算机的单个预期峰值功率的总和。

9. 发明授权

US07386616B1 System and method for providing load balanced processing 有权
标题翻译：提供负载平衡处理的系统和方法
公开(公告)号：US07386616B1
公开(公告)日：2008-06-10
申请号：US10447256
申请日：2003-05-27
申请人： Monika Hildegard Henzinger , Deborah Anne Wallach , Jeffrey Dean , Sanjay Ghemawat , Benjamin Thomas Smith , Luiz Andre Barroso
发明人： Monika Hildegard Henzinger , Deborah Anne Wallach , Jeffrey Dean , Sanjay Ghemawat , Benjamin Thomas Smith , Luiz Andre Barroso
IPC分类号： G06F15/173
CPC分类号： G06F9/505 , H04L67/1002 , H04L67/1008 , H04L67/1019
摘要： A system and method for providing load balanced processing is described. One or more files selected from a set of files are logically duplicated. At least one file and at least one logically duplicated file, is stored at one of a plurality of servers as specified in a load balancing layout. Execution of each operation in an operation stream is scheduled on the server storing at least one staged file required by the operation.
摘要翻译：描述了用于提供负载平衡处理的系统和方法。从一组文件中选择的一个或多个文件在逻辑上被重复。至少一个文件和至少一个逻辑复制的文件被存储在如负载平衡布局中指定的多个服务器中的一个。操作流中的每个操作的执行在存储操作所需的至少一个分段文件的服务器上进行调度。

10. 发明授权

US06988170B2 Scalable architecture based on single-chip multiprocessing 有权
标题翻译：基于单芯片多处理的可扩展架构
公开(公告)号：US06988170B2
公开(公告)日：2006-01-17
申请号：US10693388
申请日：2003-10-24
申请人： Luiz Andre Barroso , Kourosh Gharachorloo , Andreas Nowatzyk
发明人： Luiz Andre Barroso , Kourosh Gharachorloo , Andreas Nowatzyk
IPC分类号： G06F12/00
CPC分类号： G06F12/0811 , G06F12/0826 , G06F2212/621
摘要： A chip-multiprocessing system with scalable architecture, including on a single chip: a plurality of processor cores; a two-level cache hierarchy; an intra-chip switch; one or more memory controllers; a cache coherence protocol; one or more coherence protocol engines; and an interconnect subsystem. The two-level cache hierarchy includes first level and second level caches. In particular, the first level caches include a pair of instruction and data caches for, and private to, each processor core. The second level cache has a relaxed inclusion property, the second-level cache being logically shared by the plurality of processor cores. Each of the plurality of processor cores is capable of executing an instruction set of the ALPHA™ processing core. The scalable architecture of the chip-multiprocessing system is targeted at parallel commercial workloads. A showcase example of the chip-multiprocessing system, called the PIRAHNA™ system, is a highly integrated processing node with eight simpler ALPHA™ processor cores. A method for scalable chip-multiprocessing is also provided.
摘要翻译：具有可扩展架构的芯片多处理系统，包括在单个芯片上：多个处理器内核; 两级缓存层次结构; 片内开关; 一个或多个存储器控制器; 缓存一致性协议; 一个或多个一致性协议引擎; 和互连子系统。两级缓存层次结构包括第一级和第二级缓存。特别地，第一级高速缓存包括用于每个处理器核的私有指令和数据高速缓存。第二级缓存具有轻松的包含属性，第二级缓存由多个处理器核逻辑地共享。多个处理器核心中的每一个能够执行ALPHA TM处理核心的指令集。芯片多处理系统的可扩展架构针对并行商业工作负载。称为PIRAHNA（TM）系统的芯片多处理系统的展示示例是具有八个更简单的ALPHA（TM）处理器内核的高度集成的处理节点。还提供了一种可扩展的芯片多处理方法。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式