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1. 发明授权

US08902650B2 Memory devices and operating methods for a memory device 有权
标题翻译：存储器件的存储器件和操作方法
公开(公告)号：US08902650B2
公开(公告)日：2014-12-02
申请号：US13599208
申请日：2012-08-30
申请人： Matthew Goldman , Mark A. Helm , Jaydip B. Patel , Thomas F. Ryan
发明人： Matthew Goldman , Mark A. Helm , Jaydip B. Patel , Thomas F. Ryan
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C11/5628 , G11C16/10 , G11C2211/5622 , G11C2211/5641
摘要： Devices and methods facilitate memory device operation in all bit line architecture memory devices. In at least one embodiment, memory cells comprising alternating rows are concurrently programmed by row and concurrently sensed by row at a first density whereas memory cells comprising different alternating rows are concurrently programmed by row and concurrently sensed by row at a second density. In at least one additional embodiment, memory cells comprising alternating tiers of memory cells are programmed and sensed by tier at a first density and memory cells comprising different alternating tiers of memory cells are programmed and sensed by tier at a second density.
摘要翻译：器件和方法便于存储器件在所有位线架构存储器件中的操作。在至少一个实施例中，包括交替行的存储器单元同时由行编程并以第一密度由行同时感测，而包括不同交替行的存储单元同时由行编程并且由第二密度同时检测。在至少一个附加实施例中，包括交替层次的存储器单元的存储器单元以第一密度的层被编程和感测，并且包括不同交替层的存储器单元的存储单元由第二密度的层编程和感测。

2. 发明申请

US20110128782A1 REDUCING EFFECTS OF ERASE DISTURB IN A MEMORY DEVICE 有权
标题翻译：减少存储器件中擦除干扰的影响
公开(公告)号：US20110128782A1
公开(公告)日：2011-06-02
申请号：US12628522
申请日：2009-12-01
申请人： Akira Goda , Alessandro Torsi , Carlo Musilli , Mark A. Helm , Doyle Rivers
发明人： Akira Goda , Alessandro Torsi , Carlo Musilli , Mark A. Helm , Doyle Rivers
IPC分类号： G11C7/00 , G11C16/10
CPC分类号： G11C16/3418 , G11C16/0483 , G11C16/14
摘要： Methods for programming and memory devices are disclosed. One such method for programming includes initially biasing a subset of a plurality of control gates of a string of memory cells with a negative voltage, wherein the subset is less than all of the plurality of control gates of the string. The control gate of a selected memory cell is subsequently biased with a programming voltage during a programming phase.
摘要翻译：公开了用于编程和存储器件的方法。一种用于编程的方法包括：初始地利用负电压偏置存储器单元串的多个控制栅极的子集，其中该子集小于该串的多个控制栅极的全部。在编程阶段期间，所选择的存储单元的控制栅随后用编程电压进行偏置。

3. 发明授权

US07262102B2 Reduction of field edge thinning in peripheral devices 有权
公开(公告)号：US07262102B2
公开(公告)日：2007-08-28
申请号：US11233569
申请日：2005-09-23
申请人： Graham R Wolstenholme , Mark A Helm
发明人： Graham R Wolstenholme , Mark A Helm
IPC分类号： H01L21/8239 , H01L21/762
CPC分类号： H01L27/10894 , H01L21/76224 , H01L21/823462 , H01L21/823481 , H01L21/823857 , H01L21/823878 , H01L27/105 , H01L27/1052 , H01L27/10897 , Y10S438/981 , Y10T29/41 , Y10T29/5313
摘要： A dielectric layer (e.g., an interpoly dielectric layer) is deposited over low and high voltage devices of a peripheral memory device. The dielectric behaves as an oxidation and wet oxide etch barrier. The dielectric prevents the devices from being stripped by a wet oxide etch that can result in the exposure of the silicon corners. The exposure of a silicon corner may increase thinning of a gate oxide at the field edge. This causes variability and unreliability in the device. The dielectric is not removed from a device until the device is ready for processing. That is, the dielectric remains on a device until the growing of a gate oxide on that device has begun. This reduces the exposure of the silicon corner. Hedges that result may be removed by exposing a trench in the field oxide at the hedge.

4. 发明授权

US07141850B2 Gated semiconductor assemblies and methods of forming gated semiconductor assemblies 有权
标题翻译：门控半导体组件和形成门控半导体组件的方法
公开(公告)号：US07141850B2
公开(公告)日：2006-11-28
申请号：US10769573
申请日：2004-01-30
申请人： Mark A. Helm , Mark Fischer , John T. Moore , Scott Jeffrey DeBoer
发明人： Mark A. Helm , Mark Fischer , John T. Moore , Scott Jeffrey DeBoer
IPC分类号： H01L29/792
CPC分类号： H01L29/7881 , H01L21/28273 , H01L29/511
摘要： In one aspect, the invention includes a method of forming a gated semiconductor assembly, comprising: a) forming a silicon nitride layer over and against a floating gate; and b) forming a control gate over the silicon nitride layer. In another aspect, the invention includes a method of forming a gated semiconductor assembly, comprising: a) forming a floating gate layer over a substrate; b) forming a silicon nitride layer over the floating gate layer, the silicon nitride layer comprising a first portion and a second portion elevationally displaced from the first portion, the first portion having a greater stoichiometric amount of silicon than the second portion; and c) forming a control gate over the silicon nitride layer. In yet another aspect, the invention includes a gated semiconductor assembly comprising: a) a substrate; b) a floating gate over the substrate; c) a control gate over the floating gate; and d) an electron barrier layer between the floating gate and the control gate, the electron barrier layer comprising a silicon nitride layer, the silicon nitride layer comprising a first portion and a second portion elevationally displaced from the first portion, the first portion having a greater stoichiometric amount of silicon than the second portion.
摘要翻译：一方面，本发明包括一种形成门控半导体组件的方法，包括：a）在浮动栅极上形成氮化硅层; 以及b）在所述氮化硅层上形成控制栅极。另一方面，本发明包括形成门控半导体组件的方法，包括：a）在衬底上形成浮栅; b）在所述浮栅上形成氮化硅层，所述氮化硅层包括从所述第一部分向前倾斜的第一部分和第二部分，所述第一部分具有比所述第二部分更大的化学计量的硅量; 以及c）在所述氮化硅层上形成控制栅极。在另一方面，本发明包括门控半导体组件，其包括：a）衬底; b）衬底上的浮栅; c）浮动门上的控制门; 以及d）在所述浮动栅极和所述控制栅极之间的电子势垒层，所述电子势垒层包括氮化硅层，所述氮化硅层包括第一部分和从所述第一部分向上偏移的第二部分，所述第一部分具有比第二部分更大的化学计量的硅。

5. 发明授权

US06645814B1 Method of forming an array of FLASH field effect transistors and circuitry peripheral to such array 有权
标题翻译：形成FLASH场效应晶体管阵列和这种阵列外围电路的方法
公开(公告)号：US06645814B1
公开(公告)日：2003-11-11
申请号：US10376557
申请日：2003-02-27
申请人： Roger W Lindsay , Mark A. Helm
发明人： Roger W Lindsay , Mark A. Helm
IPC分类号： H01L218232
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11543
摘要： Thermal oxidation of a peripheral area of a semiconductor substrate is globally restricted with an overlying oxidation resistant layer that is not globally received within the array during formation of a sacrificial oxide layer prior to forming any transistor gate dielectric layer within the array. At least some FLASH field effect transistor gates having floating gate dielectric of a first thickness are formed within the array and at least some non-FLASH field effect transistor gates having gate dielectric of a second thickness are formed within the periphery, with the first and second thicknesses being different. Other aspects and implementations are disclosed.
摘要翻译：在形成阵列内的任何晶体管栅极电介质层之前，在形成牺牲氧化物层期间，覆盖抗氧化层在阵列内未被全局接收的情况下，全局限制半导体衬底的外围区域的热氧化。至少一些具有第一厚度的浮置栅极电介质的FLASH场效应晶体管栅极形成在阵列内，并且至少一些具有第二厚度的栅极电介质的非FLASH场效应晶体管栅极形成在外围，其中第一和第二厚度不同。公开了其他方面和实现。

6. 发明授权

US5523258A Method for avoiding lithographic rounding effects for semiconductor fabrication 失效
标题翻译：用于避免半导体制造的光刻圆形效应的方法
公开(公告)号：US5523258A
公开(公告)日：1996-06-04
申请号：US235509
申请日：1994-04-29
申请人： Christopher J. Petti , Andre N. Stolmeijer , Mark A. Helm
发明人： Christopher J. Petti , Andre N. Stolmeijer , Mark A. Helm
IPC分类号： H01L21/768 , H01L21/8234 , H01L21/44
CPC分类号： H01L21/8234 , H01L21/768 , Y10S148/102 , Y10S438/948
摘要： The use of separate masks to pattern the same layer of material formed over a semiconductor substrate serves to reduce or avoid lithographic rounding effects. A layer of material formed over a semiconductor substrate may be patterned in accordance with separate masks. A first mask may have a feature which is substantially perpendicular to a feature of a separate second mask. Where the layer is patterned to form transistor gates, the minimum amount each transistor gate should extend over the edge of its active region under the endcap rule may be reduced. In this regard, a line pattern mask and a gap mask are used to avoid lithographic rounding effects in forming the transistor gates. Semiconductor devices may thus be fabricated with higher packing densities as transistors may be placed closer to one another.
摘要翻译：使用单独的掩模对在半导体衬底上形成的相同材料层进行图案的作用用于减少或避免光刻圆化效应。形成在半导体衬底上的材料层可以根据分开的掩模进行构图。第一掩模可以具有基本上垂直于单独的第二掩模的特征的特征。在层被图案化以形成晶体管栅极的情况下，可以减小每个晶体管栅极在端帽规则下在其有源区域的边缘上延伸的最小量。在这方面，使用线图案掩模和间隙掩模来避免在形成晶体管栅极时的光刻圆形效应。因此，由于晶体管可以彼此更靠近放置，所以半导体器件因此可以以更高的封装密度来制造。

7. 发明申请

US20140063937A1 MEMORY DEVICES AND OPERATING METHODS FOR A MEMORY DEVICE 有权
标题翻译：用于存储器件的存储器件和操作方法
公开(公告)号：US20140063937A1
公开(公告)日：2014-03-06
申请号：US13599208
申请日：2012-08-30
申请人： Matthew Goldman , Mark A. Helm , Jaydip B. Patel , Thomas F. Ryan
发明人： Matthew Goldman , Mark A. Helm , Jaydip B. Patel , Thomas F. Ryan
IPC分类号： G11C16/10 , G11C16/04
CPC分类号： G11C16/0483 , G11C11/5628 , G11C16/10 , G11C2211/5622 , G11C2211/5641
摘要： Devices and methods facilitate memory device operation in all bit line architecture memory devices. In at least one embodiment, memory cells comprising alternating rows are concurrently programmed by row and concurrently sensed by row at a first density whereas memory cells comprising different alternating rows are concurrently programmed by row and concurrently sensed by row at a second density. In at least one additional embodiment, memory cells comprising alternating tiers of memory cells are programmed and sensed by tier at a first density and memory cells comprising different alternating tiers of memory cells are programmed and sensed by tier at a second density.
摘要翻译：器件和方法便于存储器件在所有位线架构存储器件中的操作。在至少一个实施例中，包括交替行的存储器单元同时由行编程并以第一密度由行同时感测，而包括不同交替行的存储单元同时由行编程并以第二密度由行同时检测。在至少一个附加实施例中，包括交替层次的存储器单元的存储器单元以第一密度的层被编程和感测，并且包括不同交替层的存储器单元的存储单元由第二密度的层编程和感测。

8. 发明申请

US20130322170A1 MEMORY CELL SENSING 有权
公开(公告)号：US20130322170A1
公开(公告)日：2013-12-05
申请号：US13486767
申请日：2012-06-01
申请人： Matthew Goldman , Pranav Kalavade , Uday Chandrasekhar , Mark A. Helm
发明人： Matthew Goldman , Pranav Kalavade , Uday Chandrasekhar , Mark A. Helm
IPC分类号： G11C16/28 , G11C16/04
CPC分类号： G11C16/28 , G06F12/0875 , G06F2212/452 , G11C16/04 , G11C16/26 , G11C16/3427
摘要： This disclosure concerns memory cell sensing. One or more methods include determining a data state of a first memory cell coupled to a first data line, determining a data state of a third memory cell coupled to a third data line, transferring determined data of at least one of the first and the third memory cells to a data line control unit corresponding to a second data line to which a second memory cell is coupled, the second data line being adjacent to the first data line and the third data line, and determining a data state of the second memory cell based, at least partially, on the transferred determined data.

9. 发明授权

US06746921B2 Method of forming an array of FLASH field effect transistors and circuitry peripheral to such array 有权
标题翻译：形成FLASH场效应晶体管阵列和这种阵列外围电路的方法
公开(公告)号：US06746921B2
公开(公告)日：2004-06-08
申请号：US10179893
申请日：2002-06-24
申请人： Roger W Lindsay , Mark A. Helm
发明人： Roger W Lindsay , Mark A. Helm
IPC分类号： H01L21336
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11543
摘要： Thermal oxidation of a peripheral area of a semiconductor substrate is globally restricted with an overlying oxidation resistant layer that is not globally received within the array during formation of a sacrificial oxide layer prior to forming any transistor gate dielectric layer within the array. At least some FLASH field effect transistor gates having floating gate dielectric of a first thickness are formed within the array and at least some non-FLASH field effect transistor gates having gate dielectric of a second thickness are formed within the periphery, with the first and second thicknesses being different. Other aspects and implementations are disclosed.
摘要翻译：在形成阵列内的任何晶体管栅极电介质层之前，在形成牺牲氧化物层期间，覆盖抗氧化层在阵列内未被全局接收的情况下，全局限制半导体衬底的外围区域的热氧化。至少一些具有第一厚度的浮置栅极电介质的FLASH场效应晶体管栅极形成在阵列内，并且至少一些具有第二厚度的栅极电介质的非FLASH场效应晶体管栅极形成在外围，其中第一和第二厚度不同。公开了其他方面和实现。

10. 发明授权

US06396100B2 Efficient fabrication process for dual well type structures 失效
标题翻译：双井型结构的高效制造工艺
公开(公告)号：US06396100B2
公开(公告)日：2002-05-28
申请号：US09901035
申请日：2001-07-10
申请人： Mark A. Helm
发明人： Mark A. Helm
IPC分类号： H01L29788
CPC分类号： H01L21/823842 , H01L21/823857 , H01L21/823892
摘要： An efficient method for fabricating dual well type structures uses the same number of masks used in single well type structure fabrication. In a preferred embodiment, the current invention allows low voltage and high voltage n-channel transistors and low voltage and high voltage p-channel transistors to be formed in a single substrate. One mask is used for forming a diffusion well, a second mask for both forming a retrograde well and doping the well to achieve an intermediate threshold voltage in that well, and a third mask for both differentiating the gate oxides for the low voltage devices and doping the threshold voltages to achieve the final threshold voltages.
摘要翻译：用于制造双井型结构的有效方法使用在单井型结构制造中使用的相同数量的掩模。在优选实施例中，本发明允许在单个衬底中形成低电压和高电压n沟道晶体管，并且低电压和高压p沟道晶体管形成。用于形成扩散阱的一个掩模，用于形成逆行阱并掺杂阱以在该阱中实现中间阈值电压的第二掩模，以及用于区分低电压器件的栅极氧化物和掺杂的第三掩模阈值电压以达到最终阈值电压。

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