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1. 发明授权

US09198149B2 Two-step searcher for cell discovery 有权
标题翻译：用于细胞发现的两步搜索器
公开(公告)号：US09198149B2
公开(公告)日：2015-11-24
申请号：US13432320
申请日：2012-03-28
申请人： Mark Hahm , Severine Catreux , Nelson Sollenberger
发明人： Mark Hahm , Severine Catreux , Nelson Sollenberger
IPC分类号： H04W56/00 , H04W36/18 , H03M13/37 , H03M13/39 , H04L1/00
CPC分类号： H04W56/002 , H03M13/3723 , H03M13/3905 , H03M13/3972 , H04L1/005 , H04W36/18
摘要： Disclosed are various embodiments involving a two-step searcher for cell discovery. Multiple scrambling codes associated with multiple neighboring cells are obtained. Slot timing is obtained for a received signal based at least in part on a detection of primary synchronization peak energy in the received signal. One of the scrambling codes for decoding the received signal is identified based at least in part on testing multiple scrambling code hypotheses in parallel during an accumulation time period of the received signal in response to obtaining the slot timing.
摘要翻译：公开了涉及用于细胞发现的两步搜索器的各种实施例。获得与多个相邻小区相关联的多个扰码。至少部分地基于对接收信号中的主同步峰值能量的检测，对于接收信号获得时隙定时。至少部分地基于在接收到的信号的累积时间段期间响应于获得时隙定时来并行测试多个扰码假设来识别用于解码接收信号的扰码之一。

2. 发明授权

US08509698B2 Method and system for a programmable interference suppression module 有权
标题翻译：可编程干扰抑制模块的方法和系统
公开(公告)号：US08509698B2
公开(公告)日：2013-08-13
申请号：US13532410
申请日：2012-06-25
申请人： Mark Hahm , Wei Luo , Thirunathan Sutharsan , Andrew du Preez , Bin Liu , Jun Wu , Severine Catreux-Erceg , Shuangquan Wang
发明人： Mark Hahm , Wei Luo , Thirunathan Sutharsan , Andrew du Preez , Bin Liu , Jun Wu , Severine Catreux-Erceg , Shuangquan Wang
IPC分类号： H04B1/00
CPC分类号： H04B1/71075 , H04B1/7115 , H04B1/712 , H04B2201/70702
摘要： Aspects of a method and system for a programmable interference suppression module may include receiving a communication signal comprising one or more desired signal, and one or more undesired signals. The communication signal may be utilized to generate estimated channel state information. The estimated channel state information may be formatted for use in interference suppression. A reduced interference signal may be generated from a delayed version of said communications signal and the estimated channel state information, wherein the one or more undesired signals may be attenuated. The reduced interference signal may be formatted for post-processing. The desired signals may comprise WCDMA and/or HSDPA signals, and the undesired signals may be inter-cell and/or intra-cell interference. Further processing may comprise HSDPA processing and/or RAKE finger processing. The communication signal may be a Universal Mobile Telecommunication System (UMTS) compliant signal.
摘要翻译：用于可编程干扰抑制模块的方法和系统的方面可以包括接收包括一个或多个期望信号的通信信号以及一个或多个不需要的信号。通信信号可用于产生估计的信道状态信息。估计的信道状态信息可以被格式化以用于干扰抑制。可以从所述通信信号的延迟版本和所估计的信道状态信息产生减小的干扰信号，其中所述一个或多个不需要的信号可以被衰减。减小的干扰信号可以被格式化用于后处理。期望的信号可以包括WCDMA和/或HSDPA信号，并且不期望的信号可以是小区间和/或小区内干扰。进一步的处理可以包括HSDPA处理和/或RAKE手指处理。通信信号可以是符合通用移动通信系统（UMTS）的信号。

3. 发明申请

US20130003785A1 Method and System for Interference Suppression Using Information From Non-Listened Base Stations 有权
标题翻译：使用非听众基站信息进行干扰抑制的方法和系统
公开(公告)号：US20130003785A1
公开(公告)日：2013-01-03
申请号：US13615110
申请日：2012-09-13
申请人： Mark Hahm , Wei Luo
发明人： Mark Hahm , Wei Luo
IPC分类号： H04B1/711 , H04B1/7103
CPC分类号： H04B1/7107 , H04B2201/70702 , H04W36/18
摘要： Aspects of a method and system for interference suppression using information from non-listened base stations are provided. A wireless communication device may be operable to receive a raw signal comprising one or more desired signals from one or more serving base transceiver stations (BTSs) and comprising one or more undesired signals from one or more non-listened BTSs. The wireless communication device may be operable to generate first estimate signals that estimate the one or more undesired signals as transmitted by the one or more non-listened BTSs, generate an interference suppressed version of the raw signal based on the first estimate signals, and recover the one or more desired signals from the interference suppressed version of the raw signal. The non-listened BTSs may comprise one or more BTSs that are not serving the wireless communication device and are not involved in a hand off of the wireless communication device.
摘要翻译：提供了使用来自非收听基站的信息进行干扰抑制的方法和系统的方面。无线通信设备可以用于从一个或多个服务基站收发器（BTS）接收包括一个或多个期望信号的原始信号，并且包括来自一个或多个非收听BTS的一个或多个不需要的信号。无线通信设备可以用于生成估计由一个或多个非收听的BTS发送的一个或多个不需要的信号的第一估计信号，基于第一估计信号产生原始信号的干扰抑制版本，并且恢复来自原始信号的干扰抑制版本的一个或多个期望信号。非收听的BTS可以包括一个或多个BTS，其不服务于无线通信设备，并且不涉及无线通信设备的切换。

4. 发明授权

US08238415B2 Method and system for programmable breakpoints in an integrated embedded image and video accelerator 有权
标题翻译：集成嵌入式图像和视频加速器中可编程断点的方法和系统
公开(公告)号：US08238415B2
公开(公告)日：2012-08-07
申请号：US11353529
申请日：2006-02-14
申请人： Taiyi Cheng , Mark Hahm
发明人： Taiyi Cheng , Mark Hahm
IPC分类号： H04B1/00 , G06T1/20
CPC分类号： G06T1/20
摘要： A method and system for programmable breakpoints in an integrated embedded image and video accelerator are described. Aspects of the system may include circuitry that enables generation of control signals for pipeline processing of video data within a single chip by at least selecting a target location of the video data and generating an interrupt at a time instant corresponding to the pipeline processing of the target location. The system may enable programmable breakpoints to be set and/or triggered based on policies determined in executable software. The ability to set programmable breakpoints may enable flexible utilization of system memory resources.
摘要翻译：描述了集成嵌入式图像和视频加速器中可编程断点的方法和系统。系统的方面可以包括电路，其能够通过至少选择视频数据的目标位置并在对应于目标的流水线处理的时刻产生中断来产生用于在单个芯片内的视频数据的流水线处理的控制信号位置。该系统可以基于在可执行软件中确定的策略来设置和/或触发可编程断点。设置可编程断点的能力可以灵活地利用系统内存资源。

5. 发明授权

US08068681B2 Method and system for pipelined processing in an integrated embedded image and video accelerator 有权
标题翻译：集成嵌入式图像和视频加速器中流水线处理的方法和系统
公开(公告)号：US08068681B2
公开(公告)日：2011-11-29
申请号：US12839591
申请日：2010-07-20
申请人： Taiyi Cheng , Mark Hahm , Li Fung Chang
发明人： Taiyi Cheng , Mark Hahm , Li Fung Chang
IPC分类号： G06K9/36
CPC分类号： H04N19/42
摘要： A method and system for pipelined processing in an integrated embedded image and video accelerator is described. Aspects of a system for pipelined processing in an integrated embedded image and video accelerator may include circuitry that enables pipeline processing of video data within a single chip, wherein the pipeline processing may further include decoding of a block of video data while simultaneously inverse transforming a previously decoded block of video data. Aspects of the system may also include circuitry that enables transformation, within the single chip, of a block of said video data while simultaneously encoding, within said single chip, a previously transformed block of video data.
摘要翻译：描述了集成嵌入式图像和视频加速器中流水线处理的方法和系统。在集成嵌入式图像和视频加速器中用于流水线处理的系统的方面可以包括能够对单个芯片内的视频数据进行流水线处理的电路，其中流水线处理还可以包括对视频数据块进行解码，同时对先前解码的视频数据块。系统的方面还可以包括能够在单个芯片内转换所述视频数据的块的电路，同时在所述单个芯片内同时编码先前转换的视频数据块。

6. 发明申请

US20110151888A1 METHOD AND SYSTEM FOR A PROGRAMMABLE INTERFERENCE SUPPRESSION MODULE 有权
标题翻译：用于可编程干扰抑制模块的方法和系统
公开(公告)号：US20110151888A1
公开(公告)日：2011-06-23
申请号：US12686623
申请日：2010-01-13
申请人： Mark Hahm , Wei Luo , Thirunathan Sutharsan , Andrew du Preez , Bin Liu , Jun Wu , Severine Catreux-Erceg , Shuangquan Wang
发明人： Mark Hahm , Wei Luo , Thirunathan Sutharsan , Andrew du Preez , Bin Liu , Jun Wu , Severine Catreux-Erceg , Shuangquan Wang
IPC分类号： H04W72/04 , H04B7/08
CPC分类号： H04B1/71075 , H04B1/7115 , H04B1/712 , H04B2201/70702
摘要： Aspects of a method and system for a programmable interference suppression module may include receiving a communication signal comprising one or more desired signal, and one or more undesired signals. The communication signal may be utilized to generate estimated channel state information. The estimated channel state information may be formatted for use in interference suppression. A reduced interference signal may be generated from a delayed version of said communications signal and the estimated channel state information, wherein the one or more undesired signals may be attenuated. The reduced interference signal may be formatted for post-processing. The desired signals may comprise WCDMA and/or HSDPA signals, and the undesired signals may be inter-cell and/or intra-cell interference. Further processing may comprise HSDPA processing and/or RAKE finger processing. The communication signal may be a Universal Mobile Telecommunication System (UMTS) compliant signal.
摘要翻译：用于可编程干扰抑制模块的方法和系统的方面可以包括接收包括一个或多个期望信号的通信信号以及一个或多个不需要的信号。通信信号可用于产生估计的信道状态信息。估计的信道状态信息可以被格式化以用于干扰抑制。可以从所述通信信号的延迟版本和所估计的信道状态信息产生减小的干扰信号，其中所述一个或多个不需要的信号可以被衰减。减小的干扰信号可以被格式化用于后处理。期望的信号可以包括WCDMA和/或HSDPA信号，并且不期望的信号可以是小区间和/或小区内干扰。进一步的处理可以包括HSDPA处理和/或RAKE手指处理。通信信号可以是符合通用移动通信系统（UMTS）的信号。

7. 发明授权

US07760951B2 Method and system for pipelined processing in an integrated embedded image and video accelerator 有权
标题翻译：集成嵌入式图像和视频加速器中流水线处理的方法和系统
公开(公告)号：US07760951B2
公开(公告)日：2010-07-20
申请号：US11353528
申请日：2006-02-14
申请人： Taiyi Cheng , Mark Hahm , Li Fung Chang
发明人： Taiyi Cheng , Mark Hahm , Li Fung Chang
IPC分类号： G06K9/36
CPC分类号： H04N19/42
摘要： A method and system for pipelined processing in an integrated embedded image and video accelerator is described. Aspects of a system for pipelined processing in an integrated embedded image and video accelerator may include circuitry that enables pipeline processing of video data within a single chip, wherein the pipeline processing may further include decoding of a block of video data while simultaneously inverse transforming a previously decoded block of video data. Aspects of the system may also include circuitry that enables transformation, within the single chip, of a block of said video data while simultaneously encoding, within said single chip, a previously transformed block of video data.
摘要翻译：描述了集成嵌入式图像和视频加速器中流水线处理的方法和系统。在集成嵌入式图像和视频加速器中用于流水线处理的系统的方面可以包括能够对单个芯片内的视频数据进行流水线处理的电路，其中流水线处理还可以包括对视频数据块进行解码，同时对先前解码的视频数据块。系统的方面还可以包括能够在单个芯片内转换所述视频数据的块的电路，同时在所述单个芯片内同时编码先前转换的视频数据块。

8. 发明申请

US20100057471A1 METHOD AND SYSTEM FOR PROCESSING AUDIO SIGNALS VIA SEPARATE INPUT AND OUTPUT PROCESSING PATHS 审中-公开
标题翻译：通过分离输入和输出处理程序处理音频信号的方法和系统
公开(公告)号：US20100057471A1
公开(公告)日：2010-03-04
申请号：US12248426
申请日：2008-10-09
申请人： Hongwei Kong , Nelson Sollenberger , Taiyi Cheng , Mark Hahm , Todd L. Brooks , Xicheng Jiang
发明人： Hongwei Kong , Nelson Sollenberger , Taiyi Cheng , Mark Hahm , Todd L. Brooks , Xicheng Jiang
IPC分类号： G10L19/00
CPC分类号： H04M1/6025 , H04R1/1091 , H04R25/554 , H04R27/00 , H04R2227/003 , H04R2420/07
摘要： Aspects of a method and system for processing audio signals via separate input and output processing paths are provided. In this regard, a hardware audio CODEC comprising one or more audio inputs and one or more audio outputs and may be enabled to route, via one or more switching elements, audio signals from any of the inputs to any of the outputs. The CODEC may be enabled to simultaneously process a plurality of audio signals based on a configuration of the switching elements. Upstream from the switching elements, received audio signals may be processed independent of an output to which the may be communicated. Downstream from said switching elements audio signals may be processed independent of an input via which the signals were received.
摘要翻译：提供了通过单独的输入和输出处理路径处理音频信号的方法和系统的方面。在这方面，包括一个或多个音频输入和一个或多个音频输出的硬件音频编解码器，并且可以使得能够经由一个或多个开关元件将来自任何输入的音频信号路由到任何输出。可以使CODEC可以基于开关元件的配置来同时处理多个音频信号。从开关元件的上游，接收的音频信号可以独立于可以被传送到的输出进行处理。来自所述开关元件的下游音频信号可以独立于接收信号的输入进行处理。

9. 发明授权

US07668188B2 Method and system for HSDPA bit level processor engine 有权
标题翻译： HSDPA位级处理器引擎的方法和系统
公开(公告)号：US07668188B2
公开(公告)日：2010-02-23
申请号：US11353886
申请日：2006-02-14
申请人： Li Fung Chang , Mark Hahm , Simon Baker
发明人： Li Fung Chang , Mark Hahm , Simon Baker
IPC分类号： H04L12/28 , H04L12/56
CPC分类号： H04L1/0071 , H04L1/0066 , H04L1/0067 , H04L1/0075 , H04L1/08 , H04L1/1812 , H04L1/1845 , H04L2001/0093
摘要： Methods and systems for processing signals in a communication system are disclosed and may include pipelining processing of a received HSDPA bitstream within a single chip. The pipelining may include calculating a memory address for a current portion of a plurality of information bits in the received HSDPA bitstream, while simultaneously storing on-chip, a portion of the plurality of information bits in the received bitstream that is subsequent to the current portion. A portion of the plurality of information bits in the received HSDPA bitstream that is previous to the current portion may be decoded during the calculating and the storing. The calculation of the memory address for the current portion of the plurality of information bits may be achieved without the use of a buffer. Processing of the plurality of information bits may be partitioned into a functional data processing path and a functional address processing path.
摘要翻译：公开了用于在通信系统中处理信号的方法和系统，并且可以包括在单个芯片内接收的HSDPA比特流的流水线处理。流水线可以包括计算接收的HSDPA比特流中的多个信息比特的当前部分的存储器地址，同时在片上存储接收到的当前部分之后的接收比特流中的多个信息比特的一部分。可以在计算和存储期间对接收到的HSDPA比特流中当前部分之前的多个信息比特的一部分进行解码。可以在不使用缓冲器的情况下实现多个信息比特的当前部分的存储器地址的计算。多个信息位的处理可以被划分为功能数据处理路径和功能地址处理路径。

10. 发明申请

US20080132190A1 Method and system for delay matching in a rake receiver 有权
标题翻译：耙式接收机延时匹配的方法和系统
公开(公告)号：US20080132190A1
公开(公告)日：2008-06-05
申请号：US11607438
申请日：2006-12-01
申请人： Hongwei Kong , Nelson Sollenberger , Li Fung Chang , Zoran Kostic , Mark Hahm
发明人： Hongwei Kong , Nelson Sollenberger , Li Fung Chang , Zoran Kostic , Mark Hahm
IPC分类号： H04B1/10
CPC分类号： H04B1/7115 , H04B1/7117 , H04B2201/70701
摘要： Certain aspects of a method and system for delay matching in a rake receiver are disclosed. Aspects of one method may include compensating for a delay associated with at least one or both of the following in a rake receiver: a control channel and a data channel, prior to individual processing of received data by the data channel and individual processing of received data by the control channel. The data channel or the dedicated physical channel (DPCH) may be delayed with respect to the control channel, which may comprise, for example, the common pilot control channel (CPICH), by a particular time period.
摘要翻译：公开了用于耙式接收机中的延迟匹配的方法和系统的某些方面。一种方法的方面可以包括在耙式接收机中补偿与以下中的至少一个或两者相关联的延迟：控制信道和数据信道，在数据信道对接收到的数据进行单独处理之前，以及接收数据的单独处理由控制通道。数据信道或专用物理信道（DPCH）可以相对于可以包括例如公共导频控制信道（CPICH）的控制信道延迟特定时间段。

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