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1. 发明授权

US08466743B2 Ground-referenced common-mode amplifier circuit and related method 有权
标题翻译：接地参考共模放大器电路及相关方法
公开(公告)号：US08466743B2
公开(公告)日：2013-06-18
申请号：US12799598
申请日：2010-04-27
申请人： Xicheng Jiang , Jungwoo Song
发明人： Xicheng Jiang , Jungwoo Song
IPC分类号： H03F3/217
CPC分类号： H03F3/217
摘要： Disclosed is an amplifier circuit configured to amplify a pulse stream. The amplifier circuit comprises a switching block including a first switch operable to couple an output node of the switching block to a positive reference voltage, a second switch operable to couple the output node to a ground reference voltage and a third switch operable to couple the output node to a negative reference voltage. The amplifier circuit is configured to amplify the pulse stream into an amplified signal detectable at the output node such that the amplified signal has a common-mode voltage level substantially equal to zero volts. In one embodiment, the amplifier circuit is configured to amplify the pulse stream in accordance with a Class-D amplification scheme. In one embodiment, the output node can be directly connected to a load device without a DC blocking capacitor being interposed between the output node and the load device.
摘要翻译：公开了一种被配置为放大脉冲流的放大器电路。放大器电路包括切换块，其包括可操作以将切换块的输出节点耦合到正参考电压的第一开关，可操作以将输出节点耦合到接地参考电压的第二开关和可操作以将输出节点到负参考电压。放大器电路被配置为将脉冲流放大到在输出节点处可检测的放大信号，使得放大的信号具有基本上等于零伏特的共模电压电平。在一个实施例中，放大器电路被配置为根据D类放大方案来放大脉冲流。在一个实施例中，输出节点可以直接连接到负载装置，而不会在输出节点和负载装置之间插入直流阻塞电容器。

2. 发明授权

US08288971B2 Integrated and programmable microphone bias generation 有权
标题翻译：集成和可编程麦克风偏置产生
公开(公告)号：US08288971B2
公开(公告)日：2012-10-16
申请号：US12008570
申请日：2008-01-11
申请人： Xicheng Jiang
发明人： Xicheng Jiang
IPC分类号： H04R3/00
CPC分类号： H04R3/00 , H04R2410/00
摘要： A disclosed embodiment is a programmable integrated circuit such as an audio processor or a base band processor for generating a low noise and programmable microphone bias voltage or current. The programmable integrated circuit generates a programmable reference input, where the reference input is programmably generated from at least one power source, such as a on-chip audio power supply, an on-chip power supply, or an off-chip power supply, for use by a regulator. The regulator in the programmable integrated circuit receives a bias input and the programmable reference input and generates a programmable output for biasing a microphone. The bias input for the regulator can be provided by an off-chip power supply or an on-chip power supply. The reference input provided to the regulator can be appropriately filtered to reduce noise. In one embodiment, the programmable reference input and the programmable output are programmed by first and second potentiometers, respectively.
摘要翻译：所公开的实施例是诸如音频处理器或基带处理器的可编程集成电路，用于产生低噪声和可编程麦克风偏置电压或电流。可编程集成电路产生可编程参考输入，其中参考输入可由至少一个电源（例如片上音频电源，片上电源或芯片外电源）至少可编程地产生，用于由监管机构使用。可编程集成电路中的调节器接收偏置输入和可编程参考输入，并产生用于偏置麦克风的可编程输出。调节器的偏置输入可以由片外电源或片上电源提供。提供给调节器的参考输入可以被适当地过滤以减少噪声。在一个实施例中，可编程参考输入和可编程输出分别由第一和第二电位器编程。

3. 发明授权

US08223828B2 Methods and systems for adaptive receiver equalization 有权
标题翻译：自适应接收机均衡的方法和系统
公开(公告)号：US08223828B2
公开(公告)日：2012-07-17
申请号：US11976185
申请日：2007-10-22
申请人： Aaron Buchwald , Xicheng Jiang , Hui Wang , Howard A. Baumer , Avanindra Madisetti
发明人： Aaron Buchwald , Xicheng Jiang , Hui Wang , Howard A. Baumer , Avanindra Madisetti
IPC分类号： H03H7/30
CPC分类号： H04L25/03885 , H03L7/07 , H03L7/0814 , H03L7/091 , H04L7/0025 , H04L7/0274 , H04L7/0337 , H04L25/03006 , H04L2025/03477 , H04L2025/03617
摘要： Methods and systems for minimizing distortions in an analog data signal include equalizing the analog data signal at a receive end. In an embodiment, the invention adapts equalization parameters to a signal path associated with the analog data signal. Adaptive control logic is implemented with analog and/or digital components. In an embodiment, the invention equalizes a discrete-time analog representation of an analog data signal. In an embodiment, the invention digitally controls equalization parameters. In an embodiment, a resultant equalized analog data signal is digitized. In an example implementation, an analog data signal is sampled, a quality of the samples is measured, and one or more equalization parameters are adjusted with digital controls as needed to minimize distortion of the samples. The equalized samples are then digitized. The present invention is suitable for lower rate analog data signals and multi-gigabit data rate analog signals.
摘要翻译：用于最小化模拟数据信号中的失真的方法和系统包括在接收端均衡模拟数据信号。在一个实施例中，本发明使均衡参数适应于与模拟数据信号相关联的信号路径。自适应控制逻辑由模拟和/或数字组件实现。在一个实施例中，本发明使模拟数据信号的离散时间模拟表示相等。在一个实施例中，本发明数字地控制均衡参数。在一个实施例中，所得到的均衡的模拟数据信号被数字化。在示例实现中，对模拟数据信号进行采样，测量样本的质量，并且根据需要使用数字控制来调整一个或多个均衡参数以最小化样本的失真。然后将均衡的样品数字化。本发明适用于低速模拟数据信号和多吉比特数据速率模拟信号。

4. 发明申请

US20070242404A1 Circuit output stage protection system 审中-公开
标题翻译：电路输出级保护系统
公开(公告)号：US20070242404A1
公开(公告)日：2007-10-18
申请号：US11808227
申请日：2007-06-07
申请人： Xicheng Jiang , Ardie Venes
发明人： Xicheng Jiang , Ardie Venes
IPC分类号： H02H3/20
CPC分类号： H03K19/00315 , H01L27/0266 , H03K19/018528
摘要： An output stage protection system for protecting NMOS devices in an integrated circuit (IC) output stage during normal operations and power up/power down. In an embodiment, the output stage includes a pair of relatively low voltage NMOS devices coupled to a current source and IC core outputs. A first pair of relatively high voltage NMOS devices is coupled to the relatively low voltage pair and a biasing circuit. A second pair of relatively high voltage NMOS devices is coupled to a resistor, the first pair, and first and second output nodes, respectively. One or more diodes are coupled in series between the first and second output nodes and the resistor. In an embodiment, the output stage protection system protects NMOS devices in the output stage from electrostatic discharge (ESD). Input/output (I/O) pad ESD protection circuits are coupled to the I/O pads and include a clamp coupled to a local net.
摘要翻译：一种用于在正常操作和上电/掉电期间保护集成电路（IC）输出级中的NMOS器件的输出级保护系统。在一个实施例中，输出级包括耦合到电流源和IC芯输出的一对相对低电压的NMOS器件。第一对相对高电压的NMOS器件耦合到相对低电压对和偏置电路。第二对相对高电压的NMOS器件分别耦合到电阻器，第一对以及第一和第二输出节点。一个或多个二极管串联耦合在第一和第二输出节点和电阻器之间。在一个实施例中，输出级保护系统保护输出级中的NMOS器件不受静电放电（ESD）的影响。输入/输出（I / O）焊盘ESD保护电路耦合到I / O焊盘，并包括耦合到本地网的钳位。

5. 发明授权

US07209848B2 Pulse stretching architecture for phase alignment for high speed data acquisition 有权
标题翻译：用于高速数据采集的相位对准的脉冲拉伸结构
公开(公告)号：US07209848B2
公开(公告)日：2007-04-24
申请号：US11256156
申请日：2005-10-24
申请人： Xicheng Jiang , Chun-Ying Chen , Kevin Miller , Joel Danzig , Beth Wilcher
发明人： Xicheng Jiang , Chun-Ying Chen , Kevin Miller , Joel Danzig , Beth Wilcher
IPC分类号： G01R35/00
CPC分类号： H03K5/135 , H03M9/00 , H04J3/0685 , H04L7/0037 , H04L7/0331 , H04L7/04 , H04L25/14
摘要： Systems and methods for pulse stretching architectures for phase alignment of multi-frequency clocks for high speed data acquisitions are disclosed. A high speed data acquisition system includes a transmitter and a receiver. The receiver includes a multi-frequency clock generator that generates a plurality of clock signals, a pattern check module that detects a test pattern received from the transmitter and outputs a stretch command signal, and a stretch pulse generator that receives the stretch command signal and provides a stretch pulse signal that aligns the phases of the plurality of clock signals generated by the multi-frequency clock generator. Methods for initializing and shifting multi-phase clock signals to optimize error performance of a high speed data acquisition system are also provided.
摘要翻译：公开了用于用于高速数据采集的多频时钟的相位对准的脉冲拉伸架构的系统和方法。高速数据采集系统包括发射机和接收机。接收机包括：多频时钟发生器，产生多个时钟信号;模式检查模块，用于检测从发送器接收的测试模式并输出拉伸命令信号;以及拉伸脉冲发生器，其接收拉伸命令信号并提供拉伸脉冲信号，其对准由多频时钟发生器产生的多个时钟信号的相位。还提供了用于初始化和移位多相时钟信号以优化高速数据采集系统的误差性能的方法。

6. 发明申请

US20050146819A1 Circuit output stage protection system 有权
标题翻译：电路输出级保护系统
公开(公告)号：US20050146819A1
公开(公告)日：2005-07-07
申请号：US10751508
申请日：2004-01-06
申请人： Xicheng Jiang , Ardie Venes
发明人： Xicheng Jiang , Ardie Venes
IPC分类号： H01L27/02 , H03K19/003 , H03K19/0185 , H02H9/00
CPC分类号： H03K19/00315 , H01L27/0266 , H03K19/018528
摘要： An output stage protection system for protecting CMOS devices in an integrated circuit (IC) output stage during normal operations and power up/power down. In an embodiment, the output stage includes a pair of relatively low voltage CMOS devices coupled to a current source and IC core outputs. A first pair of relatively high voltage CMOS devices is coupled to the relatively low voltage pair and a biasing circuit. A second pair of relatively high voltage CMOS devices is coupled to a resistor, the first pair, and first and second output nodes, respectively. One or more diodes are coupled in series between the first and second output nodes and the resistor. In an embodiment, the output stage protection system protects CMOS devices in the output stage from electrostatic discharge (ESD). Input/output (I/O) pad ESD protection circuits are coupled to the I/O pads and include a clamp coupled to a local net.
摘要翻译：一种用于在正常操作和上电/掉电期间保护集成电路（IC）输出级中的CMOS器件的输出级保护系统。在一个实施例中，输出级包括耦合到电流源和IC芯输出的一对相对低电压的CMOS器件。第一对相对高电压的CMOS器件耦合到相对低电压对和偏置电路。第二对相对高电压的CMOS器件分别耦合到电阻器，第一对以及第一和第二输出节点。一个或多个二极管串联耦合在第一和第二输出节点和电阻器之间。在一个实施例中，输出级保护系统保护输出级中的CMOS器件不受静电放电（ESD）的影响。输入/输出（I / O）焊盘ESD保护电路耦合到I / O焊盘，并包括耦合到本地网的钳位。

7. 发明授权

US09413312B2 Real-time short-circuit detection 有权
标题翻译：实时短路检测
公开(公告)号：US09413312B2
公开(公告)日：2016-08-09
申请号：US13304241
申请日：2011-11-23
申请人： Xicheng Jiang , Jianlong Chen , Sasi Kumar Arunachalam
发明人： Xicheng Jiang , Jianlong Chen , Sasi Kumar Arunachalam
IPC分类号： G01R31/14 , H03F3/38 , H03F3/04 , H03F3/217 , H02M1/32 , H03F1/52 , H03F3/187 , G01R31/02
CPC分类号： H03F3/2173 , G01R31/024 , H02M1/32 , H03F1/523 , H03F3/187
摘要： Presented are circuits and methods for providing real-time short-circuit detection, capable of detecting a short-circuit prior to occurrence of an over-limit current event. Such a circuit can be used to provide real-time short-circuit detection for a switched-mode system for a switched-mode system having a pre-driver and a power stage, and includes a reference block for generating a reference voltage according to drive signals provided by the pre-driver, and a comparator, which may be a synchronized comparator. The comparator is configured to compare the reference voltage to a switching node voltage generated in a power stage of the switched-mode system, and to produce an output enabling detection of the short-circuit in the switched-mode system.
摘要翻译：提出了用于提供实时短路检测的电路和方法，能够在发生超限电流事件之前检测短路。这种电路可以用于为具有预驱动器和功率级的开关模式系统的开关模式系统提供实时短路检测，并且包括用于根据驱动产生参考电压的参考块由预驱动器提供的信号，以及可以是同步比较器的比较器。比较器被配置为将参考电压与在开关模式系统的功率级中产生的开关节点电压进行比较，并且产生能够检测开关模式系统中的短路的输出。

8. 发明授权

US09106197B2 Systems and methods to suppress noise and idle tones 有权
标题翻译：抑制噪声和空闲音调的系统和方法
公开(公告)号：US09106197B2
公开(公告)日：2015-08-11
申请号：US13572154
申请日：2012-08-10
申请人： Xicheng Jiang
发明人： Xicheng Jiang
IPC分类号： H04B15/00 , H03G3/34 , H03M3/00
CPC分类号： H03G3/341 , H03M3/346 , H03M3/50
摘要： Systems and methods that reduce or remove idle tones and noise from an audio signal are provided. According to various embodiments, a level of the received input signal is detected and a control signal can be generated based on the detected level. When the detected level is above a pre-determined threshold value, then the input signal (which may have been processed) is output. When the input falls below the pre-determined threshold, then a constant signal is output instead, where the constant signal may be one of a ground signal, or other constant voltage signal.
摘要翻译：提供了减少或消除音频信号中的空闲音调和噪声的系统和方法。根据各种实施例，检测接收到的输入信号的电平，并且可以基于检测到的电平来产生控制信号。当检测到的电平高于预定阈值时，输出输入信号（可能已被处理）。当输入低于预定阈值时，则输出恒定信号，其中恒定信号可以是接地信号或其它恒定电压信号之一。

9. 发明授权

US08705752B2 Low frequency noise reduction circuit architecture for communications applications 有权
标题翻译：用于通信应用的低频降噪电路架构
公开(公告)号：US08705752B2
公开(公告)日：2014-04-22
申请号：US11523693
申请日：2006-09-20
申请人： Xicheng Jiang , Jungwoo Song , Jianlong Chen
发明人： Xicheng Jiang , Jungwoo Song , Jianlong Chen
IPC分类号： H04R5/00
CPC分类号： H04R3/04
摘要： A noise reduction circuit for reducing the effects of low frequency noise such as wind noise in communications applications is described. In one embodiment, the noise reduction circuit features a high pass filter formed by exploiting the existing off-chip AC coupling capacitances in making the connection to the source of audio signals. The filter may be adaptive to environmental low frequency noise level through programming the shunt resistances. A low-noise wide dynamic range programmable gain amplifier is also described. Adaptive equalization of the audio signal is also described through the utilization of programmable front-end resistors and a back-end audio equalizer.
摘要翻译：描述了用于降低通信应用中诸如风噪声的低频噪声的影响的降噪电路。在一个实施例中，噪声降低电路具有通过利用现有的片外AC耦合电容在形成与音频信号源的连接而形成的高通滤波器。滤波器可以通过编程分流电阻来适应环境低频噪声电平。还描述了低噪声宽动态范围可编程增益放大器。还通过利用可编程前端电阻和后端音频均衡器来描述音频信号的自适应均衡。

10. 发明申请

US20130049763A1 Real-Time Short-Circuit Detection 有权
标题翻译：实时短路检测
公开(公告)号：US20130049763A1
公开(公告)日：2013-02-28
申请号：US13304241
申请日：2011-11-23
申请人： Xicheng Jiang , Jianlong Chen , Sasi Kumar Arunachalam
发明人： Xicheng Jiang , Jianlong Chen , Sasi Kumar Arunachalam
IPC分类号： G01R31/14
CPC分类号： H03F3/2173 , G01R31/024 , H02M1/32 , H03F1/523 , H03F3/187
摘要： Presented are circuits and methods for providing real-time short-circuit detection, capable of detecting a short-circuit prior to occurrence of an over-limit current event. Such a circuit can be used to provide real-time short-circuit detection for a switched-mode system for a switched-mode system having a pre-driver and a power stage, and includes a reference block for generating a reference voltage according to drive signals provided by the pre-driver, and a comparator, which may be a synchronized comparator. The comparator is configured to compare the reference voltage to a switching node voltage generated in a power stage of the switched-mode system, and to produce an output enabling detection of the short-circuit in the switched-mode system.
摘要翻译：提出了用于提供实时短路检测的电路和方法，能够在发生超限电流事件之前检测短路。这种电路可以用于为具有预驱动器和功率级的开关模式系统的开关模式系统提供实时短路检测，并且包括用于根据驱动产生参考电压的参考块由预驱动器提供的信号，以及可以是同步比较器的比较器。比较器被配置为将参考电压与在开关模式系统的功率级中产生的开关节点电压进行比较，并且产生能够检测开关模式系统中的短路的输出。

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