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1. 发明授权

US10340375B2 Epitaxial substrate for field effect transistor 有权
公开(公告)号：US10340375B2
公开(公告)日：2019-07-02
申请号：US12527142
申请日：2008-02-12
申请人： Masahiko Hata , Hiroyuki Sazawa , Naohiro Nishikawa
发明人： Masahiko Hata , Hiroyuki Sazawa , Naohiro Nishikawa
IPC分类号： H01L29/06 , H01L31/00 , H01L29/778 , H01L29/207 , H01L29/66 , H01L21/02 , H01L29/20
摘要： The present invention provides an epitaxial substrate for field effect transistor. In the epitaxial substrate for field effect transistor, a nitride-based Group III-V semiconductor epitaxial crystal containing Ga is interposed between the ground layer and the operating layer, and the nitride-based Group III-V semiconductor epitaxial crystal includes the following (i), (ii) and (iii). (i) a first buffer layer containing Ga or Al and containing a high resistivity crystal layer having added thereto compensation impurity element present in the same period as Ga in the periodic table and having small atomic number; (ii) a second buffer layer containing Ga or Al, laminated on the operating layer side of the first buffer layer; and (iii) a high purity epitaxial crystal layer containing acceptor impurities in a slight amount such that non-addition or depletion state can be maintained, provided between the high resistivity layer and the operating layer.

2. 发明授权

US08835906B2 Sensor, semiconductor wafer, and method of producing semiconductor wafer 有权
标题翻译：传感器，半导体晶片和半导体晶片的制造方法
公开(公告)号：US08835906B2
公开(公告)日：2014-09-16
申请号：US13310522
申请日：2011-12-02
申请人： Masahiko Hata , Tomoyuki Takada , Sadanori Yamanaka , Taro Itatani
发明人： Masahiko Hata , Tomoyuki Takada , Sadanori Yamanaka , Taro Itatani
IPC分类号： H01L31/0352 , H01L31/18 , H01L31/103 , H01L27/144 , H01L31/052 , H01L31/0392 , G01J5/02
CPC分类号： H01L27/1446 , G01J5/024 , H01L31/0392 , H01L31/0543 , H01L31/1035 , H01L31/1852 , Y02E10/52 , Y02E10/544 , Y02P70/521
摘要： A sensor includes: a base wafer containing silicon; a seed member provided directly or indirectly on the base wafer; and a photothermal absorber that is made of a Group 3-5 compound semiconductor lattice-matching or pseudo lattice-matching the seed member and being capable of generating a carrier upon absorbing light or heat, where the photothermal absorber outputs an electric signal in response to incident light to be introduced into the photothermal absorber or heat to be applied to the photothermal absorber. A semiconductor wafer includes: a base wafer containing silicon; a seed member provided directly or indirectly on the base wafer; and a photothermal absorber that is made of a Group 3-5 compound semiconductor lattice-matching or pseudo lattice-matching the seed member and being capable of generating a carrier upon absorbing light or heat.
摘要翻译：传感器包括：含有硅的基底晶片; 种子构件直接或间接地设置在基底晶片上; 以及由第3-5族化合物半导体晶格匹配或伪晶格匹配种子构件并且能够在吸收光或热时产生载体的光热吸收体，其中光热吸收体输出响应于入射到光热吸收器中的入射光或被加到光热吸收器上的热量。半导体晶片包括：含有硅的基底晶片; 种子构件直接或间接地设置在基底晶片上; 以及由3-5族化合物半导体晶格匹配或伪晶格匹配种子构件制成并且能够在吸收光或热时产生载体的光热吸收剂。

3. 发明授权

US08809908B2 Semiconductor wafer, semiconductor wafer manufacturing method, and electronic device 有权
标题翻译：半导体晶片，半导体晶片制造方法和电子器件
公开(公告)号：US08809908B2
公开(公告)日：2014-08-19
申请号：US12811038
申请日：2008-12-26
申请人： Tomoyuki Takada , Sadanori Yamanaka , Masahiko Hata
发明人： Tomoyuki Takada , Sadanori Yamanaka , Masahiko Hata
IPC分类号： H01L21/20
CPC分类号： H01L21/02381 , H01L21/02433 , H01L21/0245 , H01L21/02463 , H01L21/02502 , H01L21/02516 , H01L21/02546 , H01L21/0262 , H01L21/02639 , H01L21/8258 , H01L27/0605 , H01L29/22 , H01L29/66318 , H01L29/737 , H01L29/7786
摘要： A high-quality GaAs-type crystal thin film using an inexpensive Si wafer with good thermal release characteristics is achieved. Provided is a semiconductor wafer comprising an Si wafer; a Ge layer that is crystal-grown on the wafer and shaped as an isolated island; a buffer layer that is crystal-grown on the Ge layer and is a group 3-5 compound semiconductor layer containing P; and a functional layer that is crystal-grown on the buffer layer. The Ge layer may be shaped as an island having a size that does not exceed double a distance moved by crystal defects as a result of annealing the Ge layer at a certain temperature for a certain time. The Ge layer may be shaped as an island having a size for which stress due to a difference relative to a thermal expansion coefficient of Si, which is material of the wafer, does not cause crystal defects when the Ge layer is annealed at a certain temperature.
摘要翻译：实现了具有良好热释放特性的廉价Si晶片的高质量GaAs型晶体薄膜。提供了包括Si晶片的半导体晶片; 在晶片上晶体生长并形成孤岛的Ge层; 在Ge层上晶体生长并且是含有P的3-5族化合物半导体层的缓冲层; 以及在缓冲层上晶体生长的功能层。 Ge层可以成形为岛，其尺寸不超过由晶格缺陷移动的距离的两倍，这是由于Ge层在一定温度下退火一定时间的结果。 Ge层可以成形为具有如下尺寸的岛，即当Ge层在一定温度下退火时，具有相对于作为晶片材料的Si的热膨胀系数的差的应力不会引起晶体缺陷的尺寸。

4. 发明授权

US08729677B2 Semiconductor substrate, electronic device and method for manufacturing semiconductor substrate 有权
标题翻译：半导体衬底，电子器件和半导体衬底的制造方法
公开(公告)号：US08729677B2
公开(公告)日：2014-05-20
申请号：US13131498
申请日：2009-11-26
申请人： Sadanori Yamanaka , Masahiko Hata , Tomoyuki Takada
发明人： Sadanori Yamanaka , Masahiko Hata , Tomoyuki Takada
IPC分类号： H01L29/04
CPC分类号： H01L21/8258 , H01L21/02381 , H01L21/0245 , H01L21/02463 , H01L21/02543 , H01L21/02546 , H01L21/02636
摘要： A semiconductor wafer including: a base wafer; a seed crystal disposed on the base wafer; a compound semiconductor disposed above the seed crystal; and a high resistance layer disposed between the seed crystal and the compound semiconductor, the high resistance layer having a larger resistivity than the seed crystal, and the seed crystal lattice matching or pseudo lattice matching the compound semiconductor is provided.
摘要翻译：一种半导体晶片，包括：基底晶片; 设置在基底晶片上的晶种; 设置在晶种上方的化合物半导体; 以及设置在晶种和化合物半导体之间的高电阻层，具有比晶种更大的电阻率的高电阻层，并且提供晶种匹配或伪晶格匹配化合物半导体。

5. 发明申请

US20120267688A1 SEMICONDUCTOR WAFER, SEMICONDUCTOR DEVICE, AND METHOD FOR PRODUCING SEMICONDUCTOR WAFER 有权
标题翻译：半导体晶体管，半导体器件及其制造方法
公开(公告)号：US20120267688A1
公开(公告)日：2012-10-25
申请号：US13495746
申请日：2012-06-13
申请人： Sadanori YAMANAKA , Tomoyuki TAKADA , Masahiko HATA
发明人： Sadanori YAMANAKA , Tomoyuki TAKADA , Masahiko HATA
IPC分类号： H01L29/267 , H01L21/20 , H01L29/06
CPC分类号： H01L21/02639 , H01L21/02381 , H01L21/0243 , H01L21/0245 , H01L21/02532 , H01L21/02546
摘要： To improve the flatness of the surface and improve the reliability of a semiconductor device when expitaxially growing semiconductor crystal layers of different types on a single silicon wafer, provided is a semiconductor wafer which includes: a base wafer having a silicon crystal in the surface thereof, the silicon crystal having a first dent and a second dent; a first Group IVB semiconductor crystal located in the first dent and exposed; a second Group IVB semiconductor crystal located in the second dent; and a Group III-V compound semiconductor crystal located above the second Group IVB semiconductor crystal in the second dent and exposed.
摘要翻译：为了提高表面的平坦度，提高在单晶硅晶片上外延生长不同种类的半导体晶体层时的半导体器件的可靠性，提供了一种半导体晶片，其包括：在其表面具有硅晶体的基底晶片，所述硅晶体具有第一凹陷和第二凹陷; 第一组IVB半导体晶体位于第一凹陷中并暴露; 位于第二凹陷中的第二组IVB半导体晶体; 以及位于第二凹陷中的第二IVB族半导体晶体上方并暴露的III-V族化合物半导体晶体。

6. 发明申请

US20120086044A1 LIGHT EMITTING DEVICE AND METHOD OF PRODUCING LIGHT EMITTING DEVICE 审中-公开
标题翻译：发光装置及其制造发光装置的方法
公开(公告)号：US20120086044A1
公开(公告)日：2012-04-12
申请号：US13327313
申请日：2011-12-15
申请人： Masahiko HATA , Hiroyuki SAZAWA , Sadanori YAMANAKA
发明人： Masahiko HATA , Hiroyuki SAZAWA , Sadanori YAMANAKA
IPC分类号： H01L33/30
CPC分类号： H01L27/15 , B41J2/45 , H01L27/156
摘要： There is provided a light emitting device that includes a base wafer that contains silicon, a plurality of seed bodies provided in contact with the base wafer, and a plurality of Group 3-5 compound semiconductors that are each lattice-matched or pseudo-lattice-matched to corresponding seed bodies. In the device, a light emitting element that emits light in response to current supplied thereto is formed in at least one of the plurality of the Group 3-5 compound semiconductors, and a current limiting element that limits the current supplied to the light emitting element is formed in at least one of the plurality of the Group 3-5 compound semiconductors other than the Group 3-5 compound semiconductor in which the light emitting element is formed.
摘要翻译：提供了一种发光器件，其包括含有硅的基底晶片，与基底晶片接触地设置的多个晶种，以及多个第3-5组化合物半导体，其各自是晶格匹配的或伪晶格的，与相应的种子体相匹配。在该装置中，响应于供给的电流而发光的发光元件形成在多个第3-5组化合物半导体中的至少一个中，限流元件限制供给到发光元件的电流形成在其中形成有发光元件的组3-5化合物半导体之外的多个3-5族化合物半导体中的至少一种。

7. 发明申请

US20110227042A1 METHOD FOR PRODUCING SEMICONDUCTOR SUBSTRATE, SEMICONDUCTOR SUBSTRATE, METHOD FOR MANUFACTURING ELECTRONIC DEVICE, AND REACTION APPARATUS 失效
标题翻译：用于制造半导体衬底的方法，半导体衬底，用于制造电子器件的方法和反应装置
公开(公告)号：US20110227042A1
公开(公告)日：2011-09-22
申请号：US13131523
申请日：2009-11-26
申请人： Tomoyuki Takada , Masahiko Hata , Hisashi Yamada
发明人： Tomoyuki Takada , Masahiko Hata , Hisashi Yamada
IPC分类号： H01L29/165 , H01L21/268 , G05D23/00
CPC分类号： H01L21/02532 , H01L21/02667 , H01L21/2686 , H01L21/67115 , H01L29/78
摘要： There is provided a method of producing a semiconductor wafer by thermally processing a base water having a portion to be thermally processed that is to be thermally processed. The method comprises a step of providing, on the base wafer, a portion to be heated that generates heat through absorption of an electromagnetic wave and selectively heats the portion to be thermally processed, a step of applying an electromagnetic wave to the base wafer, and a step of lowering the lattice defect density of the portion to he thermally processed, by means of the heat generated by the portion to be heated through the absorption of the electromagnetic wave.
摘要翻译：提供了通过热处理具有待热处理部分的基础水来制造半导体晶片的方法。该方法包括在基底晶片上提供通过吸收电磁波产生热并选择性地加热待热处理的部分的加热部分，向基底晶片施加电磁波的步骤，以及借助于被加热部分通过吸收电磁波而产生的热，降低热处理部分的晶格缺陷密度的步骤。

8. 发明申请

US20110180903A1 SEMICONDUCTOR SUBSTRATE, ELECTRONIC DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR SUBSTRATE 审中-公开
标题翻译：半导体衬底，电子器件及制造半导体衬底的方法
公开(公告)号：US20110180903A1
公开(公告)日：2011-07-28
申请号：US13122103
申请日：2009-10-01
申请人： Masahiko Hata
发明人： Masahiko Hata
IPC分类号： H01L29/161 , H01L29/22 , H01L29/20 , H01L21/20
CPC分类号： H01L29/78681 , H01L21/02381 , H01L21/02433 , H01L21/0245 , H01L21/02461 , H01L21/02463 , H01L21/02538 , H01L21/02551 , H01L21/02645 , H01L21/02647 , H01L21/84 , H01L29/66242 , H01L29/66742 , H01L29/7378
摘要： There is provided a semiconductor wafer having a base wafer, an insulating layer, and a SixGe1-x crystal layer (0≦x
摘要翻译：提供了具有基片，绝缘层和SixGe1-x晶层（0＆amp; nlE; x <1）的半导体晶片。在此，至少将SixGe1-x晶体层（0＆nlE; x <1）的部分区域进行退火，半导体晶片包括具有晶格匹配或者与所述至少部分晶格匹配的伪晶格的化合物半导体 6Ge1-x晶体层的区域（0＆nlE; x <1）。此外，提供了一种电子器件，其包括衬底，设置在衬底上的绝缘层，设置在绝缘层上的SixGe1-x晶体层（0＆lt; nlE; x <1），至少部分地形成SixGe1-x晶体已经进行退火的层（0＆amp; nlE; x <1），具有与SixGe1-x晶体层（0＆amp; nlE; x <1）的至少部分区域具有晶格匹配或伪晶格的化合物半导体，以及使用该化合物半导体形成的半导体器件。

9. 发明授权

US07904765B2 Test apparatus and test method 有权
标题翻译：试验装置及试验方法
公开(公告)号：US07904765B2
公开(公告)日：2011-03-08
申请号：US11857449
申请日：2007-09-19
申请人： Masahiko Hata , Shinya Sato
发明人： Masahiko Hata , Shinya Sato
IPC分类号： G11C29/38 , G11C29/50
CPC分类号： G11C29/56 , G11C16/04 , G11C29/006 , G11C2029/0401 , G11C2029/5602
摘要： Provided is a test apparatus including: test signal supply sections supplying a test signal writing test data to the connected memory under test, to a terminal of the memory; terminal correspondence determination sections outputting a terminal unit determination result indicating whether test data from the connected terminal matches an expected value; a determination result selection section selecting, for each memory, terminal unit determination results from the terminal correspondence determination sections; a memory correspondence determination section determining whether writing succeeded to each memory, based on the selection result by the determination result selection section; an identifying section identifying a test signal supply section connected to the memory to which writing succeeded and a test signal supply section connected to the memory to which writing failed; and a mask treatment section instructing each test signal supply section whether to perform re-testing, according to whether writing succeeded.
摘要翻译：提供了一种测试装置，包括：测试信号提供部分，将测试信号提供给连接的被测试的存储器，将测试数据写入存储器的终端; 终端对应确定部分，输出指示来自所连接终端的测试数据是否匹配期望值的终端单元确定结果; 确定结果选择部分，从终端对应确定部分为每个存储器选择终端单元确定结果; 存储器对应决定部，基于所述判定结果选择部的选择结果，确定是否对每个存储器进行写入; 识别部分，识别连接到写入成功的存储器的测试信号提供部分和连接到写入失败的存储器的测试信号提供部分; 以及掩模处理部，根据写入是否成功指示每个测试信号提供部分是否执行重新测试。

10. 发明申请

US20110012175A1 SEMICONDUCTOR WAFER, SEMICONDUCTOR WAFER MANUFACTURING METHOD, AND ELECTRONIC DEVICE 审中-公开
标题翻译：半导体波导，半导体波长制造方法和电子器件
公开(公告)号：US20110012175A1
公开(公告)日：2011-01-20
申请号：US12811073
申请日：2008-12-26
申请人： Tomoyuki Takada , Sadanori Yamanaka , Masahiko Hata , Taketsugu Yamamoto , Kazumi Wada
发明人： Tomoyuki Takada , Sadanori Yamanaka , Masahiko Hata , Taketsugu Yamamoto , Kazumi Wada
IPC分类号： H01L29/73 , H01L29/12 , H01L21/20
CPC分类号： H01L21/8258 , H01L21/02381 , H01L21/02433 , H01L21/0245 , H01L21/02516 , H01L21/02546 , H01L21/0262 , H01L21/02639 , H01L29/66242 , H01L29/66318 , H01L29/737 , H01L29/7786
摘要： A high-quality GaAs-type crystal thin film using an inexpensive Si wafer with good thermal release characteristics is achieved. Provided is a semiconductor wafer comprising an Si wafer; a Ge layer that is crystal-grown on the wafer and shaped as an isolated island; and a functional layer that is crystal-grown on the Ge layer. The Ge layer may be shaped as an island having a size that docs not exceed double a distance moved by crystal defects as a result of annealing the Ge layer at a certain temperature for a certain time. The Ge layer may be shaped as an island having a size for which stress due to a difference relative to a thermal expansion coefficient of Si, which is material of the wafer, does not cause crystal dejects when the Ge layer is annealed at a certain temperature.
摘要翻译：实现了具有良好热释放特性的廉价Si晶片的高质量GaAs型晶体薄膜。提供了包括Si晶片的半导体晶片; 在晶片上晶体生长并形成隔离岛的Ge层; 以及在Ge层上晶体生长的功能层。 Ge层可以被成形为岛，其尺寸不超过由晶格缺陷移动的距离的两倍，这是由于Ge层在一定温度下退火一定时间的结果。 Ge层可以成形为岛，其具有如下尺寸：当Ge层在一定温度下退火时，由于与作为晶片的材料的Si的热膨胀系数的差异而产生的应力不会引起晶体磨损的尺寸。

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