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1. 发明授权

US09804852B2 Conditional execution support for ISA instructions using prefixes 有权
公开(公告)号：US09804852B2
公开(公告)日：2017-10-31
申请号：US13976230
申请日：2011-11-30
申请人： Jonathan D. Combs , Jason W. Brandt , Robert Valentine , Kevin B. Smith , Zia Ansari , Maxim Loktyukhin
发明人： Jonathan D. Combs , Jason W. Brandt , Robert Valentine , Kevin B. Smith , Zia Ansari , Maxim Loktyukhin
IPC分类号： G06F9/30
CPC分类号： G06F9/3016 , G06F9/30072 , G06F9/30094 , G06F9/30185
摘要： In one embodiment, a processor includes an instruction decoder to receive a first instruction having a prefix and an opcode and to generate, by an instruction decoder of the processor, a second instruction executable based on a condition determined based on the prefix, and an execution unit to conditionally execute the second instruction based on the condition determined based on the prefix.

2. 发明申请

US20110153997A1 Bit Range Isolation Instructions, Methods, and Apparatus 有权
标题翻译：位范围隔离说明，方法和设备
公开(公告)号：US20110153997A1
公开(公告)日：2011-06-23
申请号：US12645307
申请日：2009-12-22
申请人： Maxim Loktyukhin , Eric W. Mahurin , Bret L. Toll , Martin G. Dixon , Sean P. Mirkes , David L. Kreitzer , El Moustapha Ould-Ahmed-Vall , Vinodh Gopal
发明人： Maxim Loktyukhin , Eric W. Mahurin , Bret L. Toll , Martin G. Dixon , Sean P. Mirkes , David L. Kreitzer , El Moustapha Ould-Ahmed-Vall , Vinodh Gopal
IPC分类号： G06F9/305 , G06F9/30 , G06F12/02
CPC分类号： G06F9/30145 , G06F9/30018 , G06F9/30029 , G06F9/30094 , G06F9/3802
摘要： Receiving an instruction indicating a source operand and a destination operand. Storing a result in the destination operand in response to the instruction. The result operand may have: (1) first range of bits having a first end explicitly specified by the instruction in which each bit is identical in value to a bit of the source operand in a corresponding position; and (2) second range of bits that all have a same value regardless of values of bits of the source operand in corresponding positions. Execution of instruction may complete without moving the first range of the result relative to the bits of identical value in the corresponding positions of the source operand, regardless of the location of the first range of bits in the result. Execution units to execute such instructions, computer systems having processors to execute such instructions, and machine-readable medium storing such an instruction are also disclosed.
摘要翻译：接收指示源操作数和目标操作数的指令。将结果存储在目标操作数中以响应指令。结果操作数可以具有：（1）具有第一端的第一范围，其中每个位在相应位置中的每个位与源操作数的位相同的指令明确地指定; 和（2）与相应位置中的源操作数的位的值无关的所有位都具有相同值的第二范围。不管移动第一范围的结果相对于源操作数的相应位置中相同值的位，执行指令都可以完成，而不考虑结果中第一个位的位置。还公开了执行这些指令的执行单元，具有执行这种指令的处理器的计算机系统以及存储这种指令的机器可读介质。

3. 发明公开

US20240103865A1 VECTOR MULTIPLY-ADD/SUBTRACT WITH INTERMEDIATE ROUNDING 审中-公开
公开(公告)号：US20240103865A1
公开(公告)日：2024-03-28
申请号：US18193413
申请日：2023-03-30
申请人： Michael ESPIG , Mikko BYCKLING , Maxim LOKTYUKHIN , Dmitry Yurievich BABOKIN , Amit GRADSTEIN , Deepti AGGARWAL
发明人： Michael ESPIG , Mikko BYCKLING , Maxim LOKTYUKHIN , Dmitry Yurievich BABOKIN , Amit GRADSTEIN , Deepti AGGARWAL
IPC分类号： G06F9/30
CPC分类号： G06F9/30145 , G06F9/3001 , G06F9/30036
摘要： Techniques for using and/or supporting multiplication with add and/or subtract instructions with an intermediate (after multiplication) round are described. In some examples, an instruction at least having one or more fields for an opcode and location information for three packed data source operands, wherein the opcode is to indicate execution circuitry is to perform, per packed data element position, a multiplication, a round, addition and/or subtraction, and a round, using the three packed data source operands and storage into a corresponding packed data element position of an identified destination location, wherein which packed data element positions are to be added and subtracted is defined by the opcode is supported.

4. 发明申请

US20130275723A1 CONDITIONAL EXECUTION SUPPORT FOR ISA INSTRUCTIONS USING PREFIXES 有权
标题翻译：使用前缀的ISA指令的条件执行支持
公开(公告)号：US20130275723A1
公开(公告)日：2013-10-17
申请号：US13976230
申请日：2011-11-30
申请人： Jonathan D. Combs , Jason W. Brandt , Robert Valentine , Kevin B. Smith , Zia Ansari , Maxim Loktyukhin
发明人： Jonathan D. Combs , Jason W. Brandt , Robert Valentine , Kevin B. Smith , Zia Ansari , Maxim Loktyukhin
IPC分类号： G06F9/30
CPC分类号： G06F9/3016 , G06F9/30072 , G06F9/30094 , G06F9/30185
摘要： In one embodiment, a processor includes an instruction decoder to receive a first instruction having a prefix and an opcode and to generate, by an instruction decoder of the processor, a second instruction executable based on a condition determined based on the prefix, and an execution unit to conditionally execute the second instruction based on the condition determined based on the prefix.
摘要翻译：在一个实施例中，处理器包括指令解码器，用于接收具有前缀和操作码的第一指令，并且由处理器的指令解码器生成基于基于前缀确定的条件的可执行的第二指令，以及执行基于基于前缀确定的条件来有条件地执行第二指令的单元。

5. 发明申请

US20140281389A1 METHODS AND APPARATUS FOR FUSING INSTRUCTIONS TO PROVIDE OR-TEST AND AND-TEST FUNCTIONALITY ON MULTIPLE TEST SOURCES 有权
标题翻译：用于在多个测试源上提供试验和试验功能的说明的方法和装置
公开(公告)号：US20140281389A1
公开(公告)日：2014-09-18
申请号：US13842754
申请日：2013-03-15
申请人： MAXIM LOKTYUKHIN , ROBERT VALENTINE , JULIAN C. HORN , MARK J. CHARNEY
发明人： MAXIM LOKTYUKHIN , ROBERT VALENTINE , JULIAN C. HORN , MARK J. CHARNEY
IPC分类号： G06F9/30
CPC分类号： G06F9/30196 , G06F8/52 , G06F9/30029 , G06F9/30058 , G06F9/30145 , G06F9/3017 , G06F9/4552
摘要： Methods and apparatus are disclosed for fusing instructions to provide OR-test and AND-test functionality on multiple test sources. Some embodiments include fetching instructions, said instructions including a first instruction specifying a first operand destination, a second instruction specifying a second operand source, and a third instruction specifying a branch condition. A portion of the plurality of instructions are fused into a single micro-operation, the portion including both the first and second instructions if said first operand destination and said second operand source are the same, and said branch condition is dependent upon the second instruction. Some embodiments generate a novel test instruction dynamically by fusing one logical instruction with a prior-art test instruction. Other embodiments generate the novel test instruction through a just-in-time compiler. Some embodiments also fuse the novel test instruction with a subsequent conditional branch instruction, and perform a branch according to how the condition flag is set.
摘要翻译：公开了用于融合指令以在多个测试源上提供OR测试和AND测试功能的方法和装置。一些实施例包括获取指令，所述指令包括指定第一操作数目的地的第一指令，指定第二操作数源的第二指令以及指定分支条件的第三指令。多个指令的一部分被融合成单个微操作，如果所述第一操作数目的地和所述第二操作数源相同，则包括第一和第二指令的部分，并且所述分支条件取决于第二指令。一些实施例通过将一个逻辑指令与现有技术的测试指令进行融合来动态地产生新颖的测试指令。其他实施例通过即时编译器生成新颖的测试指令。一些实施例还将新颖的测试指令与随后的条件分支指令融合，并且根据如何设置条件标志来执行分支。

6. 发明申请

US20130311756A1 ROTATE INSTRUCTIONS THAT COMPLETE EXECUTION WITHOUT READING CARRY FLAG 有权
标题翻译：完全执行无需阅读携带标志的指令
公开(公告)号：US20130311756A1
公开(公告)日：2013-11-21
申请号：US13947958
申请日：2013-07-22
申请人： VINODH GOPAL , JAMES D. GULILFORD , GILBERT M. WOLRICH , WAIDI K. FEGHALI , ERDINC OZTURK , MARTIN G. DIXON , SEAN P. MIRKES , BRET L. TOLL , MAXIM LOKTYUKHIN , MARK C. DAVIS , ALEXANDRE J. FARCY
发明人： VINODH GOPAL , JAMES D. GULILFORD , GILBERT M. WOLRICH , WAIDI K. FEGHALI , ERDINC OZTURK , MARTIN G. DIXON , SEAN P. MIRKES , BRET L. TOLL , MAXIM LOKTYUKHIN , MARK C. DAVIS , ALEXANDRE J. FARCY
IPC分类号： G06F9/30
CPC分类号： G06F9/30032 , G06F9/30094 , G06F9/30098
摘要： A method of one aspect may include receiving a rotate instruction. The rotate instruction may indicate a source operand and a rotate amount. A result may be stored in a destination operand indicated by the rotate instruction. The result may have the source operand rotated by the rotate amount. Execution of the rotate instruction may complete without reading a carry flag.
摘要翻译：一个方面的方法可以包括接收旋转指令。旋转指令可以指示源操作数和旋转量。结果可以存储在由旋转指令指示的目标操作数中。结果可能使源操作数旋转了旋转量。旋转指令的执行可以在不读取进位标志的情况下完成。

7. 发明授权

US09990201B2 Multiplication instruction for which execution completes without writing a carry flag 有权
公开(公告)号：US09990201B2
公开(公告)日：2018-06-05
申请号：US12645383
申请日：2009-12-22
申请人： Vinodh Gopal , James D. Guilford , Wajdi K. Feghali , Erdine Ozturk , Gilbert M. Wolrich , Martin G. Dixon , Mark C. Davis , Sean P. Mirkes , Alexandre Farcy , Bret L. Toll , Maxim Loktyukhin
发明人： Vinodh Gopal , James D. Guilford , Wajdi K. Feghali , Erdine Ozturk , Gilbert M. Wolrich , Martin G. Dixon , Mark C. Davis , Sean P. Mirkes , Alexandre Farcy , Bret L. Toll , Maxim Loktyukhin
IPC分类号： G06F15/00 , G06F7/38 , G06F9/00 , G06F9/44 , G06F9/30
CPC分类号： G06F9/30094 , G06F9/30014
摘要： A method in one aspect may include receiving a multiply instruction. The multiply instruction may indicate a first source operand and a second source operand. A product of the first and second source operands may be stored in one or more destination operands indicated by the multiply instruction. Execution of the multiply instruction may complete without writing a carry flag. Other methods are also disclosed, as are apparatus, systems, and instructions on machine-readable medium.

8. 发明授权

US09483266B2 Fusible instructions and logic to provide OR-test and AND-test functionality using multiple test sources 有权
标题翻译：使用多个测试源提供OR-test和AND-test功能的易熔指令和逻辑
公开(公告)号：US09483266B2
公开(公告)日：2016-11-01
申请号：US13843020
申请日：2013-03-15
申请人： Maxim Loktyukhin , Robert Valentine , Julian C. Horn , Mark J. Charney
发明人： Maxim Loktyukhin , Robert Valentine , Julian C. Horn , Mark J. Charney
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/3822 , G06F9/30029 , G06F9/30058 , G06F9/30094 , G06F9/3836
摘要： Fusible instructions and logic provide OR-test and AND-test functionality on multiple test sources. Some embodiments include a processor decode stage to decode a test instruction for execution, the instruction specifying first, second and third source data operands, and an operation type. Execution units, responsive to the decoded test instruction, perform one logical operation, according to the specified operation type, between data from the first and second source data operands, and perform a second logical operation between the data from the third source data operand and the result of the first logical operation to set a condition flag. Some embodiments generate the test instruction dynamically by fusing one logical instruction with a prior-art test instruction. Other embodiments generate the test instruction through a just-in-time compiler. Some embodiments also fuse the test instruction with a subsequent conditional branch instruction, and perform a branch according to how the condition flag is set.
摘要翻译：易熔指令和逻辑在多个测试源上提供OR测试和与测试功能。一些实施例包括解码用于执行的测试指令的处理器解码级，指定第一，第二和第三源数据操作数的指令以及操作类型。执行单元响应于解码的测试指令，根据指定的操作类型在来自第一和第二源数据操作数的数据之间执行一个逻辑操作，并且执行来自第三源数据操作数的数据和第一个逻辑运算结果设置条件标志。一些实施例通过将一个逻辑指令与现有技术的测试指令进行融合来动态地产生测试指令。其他实施例通过即时编译器生成测试指令。一些实施例还将测试指令与随后的条件分支指令融合，并且根据条件标志的设置来执行分支。

9. 发明授权

US09003170B2 Bit range isolation instructions, methods, and apparatus 有权
标题翻译：位范围隔离指令，方法和设备
公开(公告)号：US09003170B2
公开(公告)日：2015-04-07
申请号：US12645307
申请日：2009-12-22
申请人： Maxim Loktyukhin , Eric W. Mahurin , Bret L. Toll , Martin G. Dixon , Sean P. Mirkes , David L. Kreitzer , El Moustapha Ould-Ahmed-Vall , Vinodh Gopal
发明人： Maxim Loktyukhin , Eric W. Mahurin , Bret L. Toll , Martin G. Dixon , Sean P. Mirkes , David L. Kreitzer , El Moustapha Ould-Ahmed-Vall , Vinodh Gopal
IPC分类号： G06F7/38 , G06F9/00 , G06F9/44 , G06F15/00 , G06F9/30
CPC分类号： G06F9/30145 , G06F9/30018 , G06F9/30029 , G06F9/30094 , G06F9/3802
摘要： Receiving an instruction indicating a source operand and a destination operand. Storing a result in the destination operand in response to the instruction. The result operand may have: (1) first range of bits having a first end explicitly specified by the instruction in which each bit is identical in value to a bit of the source operand in a corresponding position; and (2) second range of bits that all have a same value regardless of values of bits of the source operand in corresponding positions. Execution of instruction may complete without moving the first range of the result relative to the bits of identical value in the corresponding positions of the source operand, regardless of the location of the first range of bits in the result. Execution units to execute such instructions, computer systems having processors to execute such instructions, and machine-readable medium storing such an instruction are also disclosed.
摘要翻译：接收指示源操作数和目标操作数的指令。将结果存储在目标操作数中以响应指令。结果操作数可以具有：（1）具有第一端的第一范围，其中每个位在相应位置中的每个位与源操作数的位相同的指令明确地指定; 和（2）与相应位置中的源操作数的位的值无关的所有位都具有相同值的第二范围。不管移动第一范围的结果相对于源操作数的相应位置中相同值的位，执行指令都可以完成，而不考虑结果中第一个位的位置。还公开了执行这些指令的执行单元，具有执行这种指令的处理器的计算机系统以及存储这种指令的机器可读介质。

10. 发明授权

US08504807B2 Rotate instructions that complete execution without reading carry flag 有权
公开(公告)号：US08504807B2
公开(公告)日：2013-08-06
申请号：US12655213
申请日：2009-12-26
申请人： Vinodh Gopal , James D. Guilford , Gilbert M. Wolrich , Wajdi K. Feghali , Erdinc Ozturk , Martin G. Dixon , Sean P. Mirkes , Bret L. Toll , Maxim Loktyukhin , Mark C. Davis , Alexandre J. Farcy
发明人： Vinodh Gopal , James D. Guilford , Gilbert M. Wolrich , Wajdi K. Feghali , Erdinc Ozturk , Martin G. Dixon , Sean P. Mirkes , Bret L. Toll , Maxim Loktyukhin , Mark C. Davis , Alexandre J. Farcy
IPC分类号： G06F9/00
CPC分类号： G06F9/30032 , G06F9/30094 , G06F9/30098
摘要： A method of one aspect may include receiving a rotate instruction. The rotate instruction may indicate a source operand and a rotate amount. A result may be stored in a destination operand indicated by the rotate instruction. The result may have the source operand rotated by the rotate amount. Execution of the rotate instruction may complete without reading a carry flag.

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