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1. 发明申请

US20130082784A1 OSCILLATOR CALIBRATION APPARATUS AND OSCILLATOR CALIBRATION METHOD 有权
标题翻译：振荡器校准装置和振荡器校准方法
公开(公告)号：US20130082784A1
公开(公告)日：2013-04-04
申请号：US13252171
申请日：2011-10-03
申请人： Chun-Yu Chiu , Yaw-Guang Chang , Meng-Wei Shen
发明人： Chun-Yu Chiu , Yaw-Guang Chang , Meng-Wei Shen
IPC分类号： H03L7/00
CPC分类号： H03L7/097 , H03L7/091
摘要： An oscillator calibration apparatus includes a counter, a comparator and an adjusting unit. The counter is utilized for receiving a first clock signal and a second clock signal, and utilizing the first clock signal to sample the second clock signal to generate at least one counting value, where the first clock signal is generated from a first oscillator, and the second clock signal is generated from a second oscillator different from the first oscillator; the comparator is coupled to the counter, and is utilized for comparing the counting value with a predetermined value to generate at least one calibration signal; and the adjusting unit is coupled to the comparator, and is utilized for adjusting a frequency of the second oscillator according to the calibration signal.
摘要翻译：振荡器校准装置包括计数器，比较器和调整单元。该计数器用于接收第一时钟信号和第二时钟信号，并利用第一时钟信号对第二时钟信号进行采样以产生至少一个计数值，其中第一时钟信号从第一振荡器产生，从与第一振荡器不同的第二振荡器产生第二时钟信号; 比较器被耦合到计数器，并且用于将计数值与预定值进行比较以产生至少一个校准信号; 并且所述调整单元耦合到所述比较器，并且用于根据所述校准信号调整所述第二振荡器的频率。

2. 发明授权

US08171332B2 Integrated circuit with reduced electromagnetic interference induced by memory access and method for the same 有权
标题翻译：具有降低电磁干扰的集成电路由存储器访问引起的方法和相同的方法
公开(公告)号：US08171332B2
公开(公告)日：2012-05-01
申请号：US12464291
申请日：2009-05-12
申请人： Meng-Wei Shen
发明人： Meng-Wei Shen
IPC分类号： G06F1/00 , G06F1/12 , G06F13/42 , G06F1/04 , G06F5/06 , H04L5/00 , H04L7/00
CPC分类号： G06F1/08 , G09G3/3611 , G09G5/18 , G09G5/39 , G09G5/393 , G09G5/395 , G09G2330/06
摘要： The invention provides an integrated circuit with reduced electromagnetic interference induced by memory access. The integrated circuit includes a random code generator, a request receiver and a memory unit. The random code generator generates a plurality of random codes according to a predetermined delay parameter. The request receiver obtains an input clock signal according to a plurality of data requests and spreads the spectrum of the input clock signal based on the random codes to derive a non-periodic output clock signal. The memory unit accesses image data to be displayed in response to the data requests and the output clock signal.
摘要翻译：本发明提供一种具有由存储器访问引起的电磁干扰降低的集成电路。集成电路包括随机码发生器，请求接收器和存储器单元。随机码发生器根据预定的延迟参数产生多个随机码。请求接收器根据多个数据请求获得输入时钟信号，并且基于随机码对输入时钟信号的频谱进行扩频以导出非周期性输出时钟信号。存储单元响应于数据请求和输出时钟信号访问要显示的图像数据。

3. 发明申请

US20100293405A1 INTEGRATED CIRCUIT WITH REDUCED ELECTROMAGNETIC INTERFERENCE INDUCED BY MEMORY ACCESS AND METHOD FOR THE SAME 有权
标题翻译：由存储器访问引起的具有降低的电磁干扰的集成电路及其相关方法
公开(公告)号：US20100293405A1
公开(公告)日：2010-11-18
申请号：US12464291
申请日：2009-05-12
申请人： Meng-Wei Shen
发明人： Meng-Wei Shen
IPC分类号： G06F1/12
CPC分类号： G06F1/08 , G09G3/3611 , G09G5/18 , G09G5/39 , G09G5/393 , G09G5/395 , G09G2330/06
摘要： The invention provides an integrated circuit with reduced electromagnetic interference induced by memory access. The integrated circuit includes a random code generator, a request receiver and a memory unit. The random code generator generates a plurality of random codes according to a predetermined delay parameter. The request receiver obtains an input clock signal according to a plurality of data requests and spreads the spectrum of the input clock signal based on the random codes to derive a non-periodic output clock signal. The memory unit accesses image data to be displayed in response to the data requests and the output clock signal.
摘要翻译：本发明提供一种具有由存储器访问引起的电磁干扰降低的集成电路。集成电路包括随机码发生器，请求接收器和存储器单元。随机码发生器根据预定的延迟参数产生多个随机码。请求接收器根据多个数据请求获得输入时钟信号，并且基于随机码对输入时钟信号的频谱进行扩频以导出非周期性输出时钟信号。存储单元响应于数据请求和输出时钟信号访问要显示的图像数据。

4. 发明授权

US07768854B2 Controlling apparatus and controlling method for controlling a pre-charge activity on a SRAM array 有权
标题翻译：用于控制SRAM阵列上的预充电活动的控制装置和控制方法
公开(公告)号：US07768854B2
公开(公告)日：2010-08-03
申请号：US12112441
申请日：2008-04-30
申请人： Ming-Cheng Chiu , Meng-Wei Shen
发明人： Ming-Cheng Chiu , Meng-Wei Shen
IPC分类号： G11C7/00
CPC分类号： G11C7/12 , G11C7/22 , G11C11/413
摘要： A controlling apparatus and a controlling method for controlling a pre-charge activity on a SRAM array are provided. The controlling apparatus comprises: a detecting module, a controlling module and a pre-charge module. The detecting module is to detect whether the row address of the SRAM array in operation is changed and generate a row-changing signal according to the detection result; the controlling module is to detect an operation mode of the SRAM array and generate a disable signal according to the row-changing signal and the operation mode; and the pre-charge module is to generate a pre-charge signal according to a pseudo-pre-charge signal and the disable signal, wherein the pre-charge signal substantially controls the pre-charge activity on the SRAM cell in operation.
摘要翻译：提供了一种用于控制SRAM阵列上的预充电活动的控制装置和控制方法。控制装置包括：检测模块，控制模块和预充电模块。检测模块是检测运行中的SRAM阵列的行地址是否改变，并根据检测结果生成行更改信号; 控制模块用于检测SRAM阵列的工作模式，并根据行变化信号和操作模式产生禁用信号; 并且预充电模块将根据伪预充电信号和禁用信号产生预充电信号，其中预充电信号在操作中基本上控制在SRAM单元上的预充电活动。

5. 发明授权

US08564374B2 Oscillator calibration apparatus and oscillator calibration method 有权
标题翻译：振荡器校准装置和振荡器校准方法
公开(公告)号：US08564374B2
公开(公告)日：2013-10-22
申请号：US13252171
申请日：2011-10-03
申请人： Chun-Yu Chiu , Yaw-Guang Chang , Meng-Wei Shen
发明人： Chun-Yu Chiu , Yaw-Guang Chang , Meng-Wei Shen
IPC分类号： H03L7/06 , H03L7/183
CPC分类号： H03L7/097 , H03L7/091
摘要： An oscillator calibration apparatus includes a counter, a comparator and an adjusting unit. The counter is utilized for receiving a first clock signal and a second clock signal, and utilizing the first clock signal to sample the second clock signal to generate at least one counting value, where the first clock signal is generated from a first oscillator, and the second clock signal is generated from a second oscillator different from the first oscillator; the comparator is coupled to the counter, and is utilized for comparing the counting value with a predetermined value to generate at least one calibration signal; and the adjusting unit is coupled to the comparator, and is utilized for adjusting a frequency of the second oscillator according to the calibration signal.
摘要翻译：振荡器校准装置包括计数器，比较器和调整单元。该计数器用于接收第一时钟信号和第二时钟信号，并利用第一时钟信号对第二时钟信号进行采样以产生至少一个计数值，其中第一时钟信号从第一振荡器产生，从与第一振荡器不同的第二振荡器产生第二时钟信号; 比较器被耦合到计数器，并且用于将计数值与预定值进行比较以产生至少一个校准信号; 并且所述调整单元耦合到所述比较器，并且用于根据所述校准信号调整所述第二振荡器的频率。

6. 发明申请

US20090273997A1 Controlling Apparatus and Controlling Method for Controlling a Pre-Charge Activity on a SRAM Array 有权
标题翻译：用于控制SRAM阵列上预充电活动的控制装置和控制方法
公开(公告)号：US20090273997A1
公开(公告)日：2009-11-05
申请号：US12112441
申请日：2008-04-30
申请人： Ming-Cheng Chiu , Meng-Wei Shen
发明人： Ming-Cheng Chiu , Meng-Wei Shen
IPC分类号： G11C7/00
CPC分类号： G11C7/12 , G11C7/22 , G11C11/413
摘要： A controlling apparatus and a controlling method for controlling a pre-charge activity on a SRAM array are provided. The controlling apparatus comprises: a detecting module, a controlling module and a pre-charge module. The detecting module is to detect whether the row address of the SRAM array in operation is changed and generate a row-changing signal according to the detection result; the controlling module is to detect an operation mode of the SRAM array and generate a disable signal according to the row-changing signal and the operation mode; and the pre-charge module is to generate a pre-charge signal according to a pseudo-pre-charge signal and the disable signal, wherein the pre-charge signal substantially controls the pre-charge activity on the SRAM cell in operation.
摘要翻译：提供了一种用于控制SRAM阵列上的预充电活动的控制装置和控制方法。控制装置包括：检测模块，控制模块和预充电模块。检测模块是检测运行中的SRAM阵列的行地址是否改变，并根据检测结果生成行更改信号; 控制模块用于检测SRAM阵列的工作模式，并根据行变化信号和操作模式产生禁用信号; 并且预充电模块将根据伪预充电信号和禁用信号产生预充电信号，其中预充电信号在操作中基本上控制在SRAM单元上的预充电活动。

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