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1. 发明授权

US08564374B2 Oscillator calibration apparatus and oscillator calibration method 有权
标题翻译：振荡器校准装置和振荡器校准方法
公开(公告)号：US08564374B2
公开(公告)日：2013-10-22
申请号：US13252171
申请日：2011-10-03
申请人： Chun-Yu Chiu , Yaw-Guang Chang , Meng-Wei Shen
发明人： Chun-Yu Chiu , Yaw-Guang Chang , Meng-Wei Shen
IPC分类号： H03L7/06 , H03L7/183
CPC分类号： H03L7/097 , H03L7/091
摘要： An oscillator calibration apparatus includes a counter, a comparator and an adjusting unit. The counter is utilized for receiving a first clock signal and a second clock signal, and utilizing the first clock signal to sample the second clock signal to generate at least one counting value, where the first clock signal is generated from a first oscillator, and the second clock signal is generated from a second oscillator different from the first oscillator; the comparator is coupled to the counter, and is utilized for comparing the counting value with a predetermined value to generate at least one calibration signal; and the adjusting unit is coupled to the comparator, and is utilized for adjusting a frequency of the second oscillator according to the calibration signal.
摘要翻译：振荡器校准装置包括计数器，比较器和调整单元。该计数器用于接收第一时钟信号和第二时钟信号，并利用第一时钟信号对第二时钟信号进行采样以产生至少一个计数值，其中第一时钟信号从第一振荡器产生，从与第一振荡器不同的第二振荡器产生第二时钟信号; 比较器被耦合到计数器，并且用于将计数值与预定值进行比较以产生至少一个校准信号; 并且所述调整单元耦合到所述比较器，并且用于根据所述校准信号调整所述第二振荡器的频率。

2. 发明申请

US20130082784A1 OSCILLATOR CALIBRATION APPARATUS AND OSCILLATOR CALIBRATION METHOD 有权
标题翻译：振荡器校准装置和振荡器校准方法
公开(公告)号：US20130082784A1
公开(公告)日：2013-04-04
申请号：US13252171
申请日：2011-10-03
申请人： Chun-Yu Chiu , Yaw-Guang Chang , Meng-Wei Shen
发明人： Chun-Yu Chiu , Yaw-Guang Chang , Meng-Wei Shen
IPC分类号： H03L7/00
CPC分类号： H03L7/097 , H03L7/091
摘要： An oscillator calibration apparatus includes a counter, a comparator and an adjusting unit. The counter is utilized for receiving a first clock signal and a second clock signal, and utilizing the first clock signal to sample the second clock signal to generate at least one counting value, where the first clock signal is generated from a first oscillator, and the second clock signal is generated from a second oscillator different from the first oscillator; the comparator is coupled to the counter, and is utilized for comparing the counting value with a predetermined value to generate at least one calibration signal; and the adjusting unit is coupled to the comparator, and is utilized for adjusting a frequency of the second oscillator according to the calibration signal.
摘要翻译：振荡器校准装置包括计数器，比较器和调整单元。该计数器用于接收第一时钟信号和第二时钟信号，并利用第一时钟信号对第二时钟信号进行采样以产生至少一个计数值，其中第一时钟信号从第一振荡器产生，从与第一振荡器不同的第二振荡器产生第二时钟信号; 比较器被耦合到计数器，并且用于将计数值与预定值进行比较以产生至少一个校准信号; 并且所述调整单元耦合到所述比较器，并且用于根据所述校准信号调整所述第二振荡器的频率。

3. 发明申请

US20120098843A1 APPARATUS FOR CONTROLLING MEMORY DEVICE AND RELATED METHOD 有权
标题翻译：用于控制存储器件的装置及相关方法
公开(公告)号：US20120098843A1
公开(公告)日：2012-04-26
申请号：US12910859
申请日：2010-10-24
申请人： Chun-Yu Chiu , Tsung-Han Yang
发明人： Chun-Yu Chiu , Tsung-Han Yang
IPC分类号： G09G5/39
CPC分类号： G09G5/39 , G09G2360/123
摘要： A method for controlling a memory device includes: categorizing a plurality of sub-memory units of the memory device into a first group of sub-memory units and a second group of sub-memory units; sequentially storing pixel data of a plurality of pixels being displayed on a first line of a display screen into the sub-memory units of the first group of sub-memory units; sequentially storing the pixel data of a plurality of pixels being displayed on a second line next to the first line of the display screen into the sub-memory units of the second group of sub-memory units; and, starting from a next but one sub-memory unit to the first selected sub-memory unit, sequentially storing the pixel data of a plurality of pixels being displayed on a third line next to the second line of the display screen into the sub-memory units of the first group of sub-memory units.
摘要翻译：一种用于控制存储器件的方法包括：将存储器件的多个子存储器单元分类成第一组子存储器单元和第二组子存储器单元组; 将显示在显示屏幕的第一行上的多个像素的像素数据顺序地存储到第一组子存储器单元的子存储器单元中; 将显示在显示屏幕的第一行旁边的第二行显示的多个像素的像素数据顺序存储到第二组子存储单元组的子存储单元中; 并且从下一个子存储器单元开始到第一选择子存储器单元，顺序地将显示在显示屏幕的第二行的第三行上显示的多个像素的像素数据存储到子画面中，第一组子存储器单元的存储单元。

4. 发明授权

US08300492B2 Memory 有权
标题翻译：记忆
公开(公告)号：US08300492B2
公开(公告)日：2012-10-30
申请号：US12897078
申请日：2010-10-04
申请人： Chun-Yu Chiu
发明人： Chun-Yu Chiu
IPC分类号： G11C8/00
CPC分类号： G11C11/413 , G11C7/227
摘要： A memory including a memory cell array, a word line decoder, a first and a second reference bit line generators are provided. The memory cell array has first and last bit lines respectively disposed at two sides of the memory cell array. The word line decoder generates a pre-word line signal. The first and the second reference bit line generators respectively detect voltage level variations of the first and last bit lines according to the pre-word line signal, so as to generate a first and a second cut-back signals. The first reference bit line generator transmits the first cut-back signal to the second reference bit line generator, the second reference bit line generator transmits the first and the second cut-back signals to the word line decoder, and the word line decoder generates a word line signal according to the first and the second cut-back signals and the pre-word line signal.
摘要翻译：提供了包括存储单元阵列，字线解码器，第一和第二参考位线发生器的存储器。存储单元阵列具有分别设置在存储单元阵列的两侧的第一和最后位线。字线解码器产生预字线信号。第一和第二参考位线发生器分别根据预字线信号检测第一和最后位线的电压电平变化，以产生第一和第二切断信号。第一参考位线发生器将第一切断信号发送到第二参考位线发生器，第二参考位线发生器将第一和第二切断信号发送到字线解码器，并且字线解码器产生根据第一和第二切断信号和预字线信号的字线信号。

5. 发明授权

US08209478B2 Single-port SRAM and method of accessing the same 有权
标题翻译：单端口SRAM及其访问方法
公开(公告)号：US08209478B2
公开(公告)日：2012-06-26
申请号：US12397269
申请日：2009-03-03
申请人： Chun-Yu Chiu
发明人： Chun-Yu Chiu
IPC分类号： G06F12/00
CPC分类号： G06F13/1626 , Y02D10/14
摘要： A system and method for resolving request collision in a single-port static random access memory (SRAM) are disclosed. A first SRAM part and a second SRAM part of the single-port SRAM are accessed in turn. When request collision occurs, data is temporarily stored in a first or second shadow bank associated with the first or the second SRAM part which is under access. The temporarily stored data is then transferred, at a later time, to an associated one of the first/second SRAM parts while the other one of the first/second SRAM parts is being accessed.
摘要翻译：公开了一种用于解决单端口静态随机存取存储器（SRAM）中的请求冲突的系统和方法。依次访问单端口SRAM的第一个SRAM部分和第二个SRAM部分。当发生请求冲突时，数据被临时存储在与正在访问的第一或第二SRAM部分相关联的第一或第二影子库中。然后，临时存储的数据在稍后的时间被传送到第一/第二SRAM部分中的相关联的一个，而第一/第二SRAM部分中的另一个被访问。

6. 发明授权

US08564603B2 Apparatus for controlling memory device and related method 有权
标题翻译：用于控制存储器件的装置及相关方法
公开(公告)号：US08564603B2
公开(公告)日：2013-10-22
申请号：US12910859
申请日：2010-10-24
申请人： Chun-Yu Chiu , Tsung-Han Yang
发明人： Chun-Yu Chiu , Tsung-Han Yang
IPC分类号： G06F13/00
CPC分类号： G09G5/39 , G09G2360/123
摘要： A method for controlling a memory device includes: categorizing a plurality of sub-memory units of the memory device into a first group of sub-memory units and a second group of sub-memory units; sequentially storing pixel data of a plurality of pixels being displayed on a first line of a display screen into the sub-memory units of the first group of sub-memory units; sequentially storing the pixel data of a plurality of pixels being displayed on a second line next to the first line of the display screen into the sub-memory units of the second group of sub-memory units; and, starting from a next but one sub-memory unit to the first selected sub-memory unit, sequentially storing the pixel data of a plurality of pixels being displayed on a third line next to the second line of the display screen into the sub-memory units of the first group of sub-memory units.
摘要翻译：一种用于控制存储器件的方法包括：将存储器件的多个子存储器单元分类成第一组子存储器单元和第二组子存储器单元组; 将显示在显示屏幕的第一行上的多个像素的像素数据顺序地存储到第一组子存储器单元的子存储器单元中; 将显示在显示屏幕的第一行旁边的第二行显示的多个像素的像素数据顺序存储到第二组子存储单元组的子存储单元中; 并且从下一个子存储器单元开始到第一选择子存储器单元，顺序地将显示在显示屏幕的第二行的第三行上显示的多个像素的像素数据存储到子画面中，第一组子存储器单元的存储单元。

7. 发明申请

US20130028006A1 STATIC RANDOM ACCESS MEMORY STRUCTURE AND CONTROL METHOD THEREOF 有权
标题翻译：静态随机访问存储器结构及其控制方法
公开(公告)号：US20130028006A1
公开(公告)日：2013-01-31
申请号：US13190031
申请日：2011-07-25
申请人： Chun-Yu Chiu
发明人： Chun-Yu Chiu
IPC分类号： G11C11/00
CPC分类号： G11C11/417
摘要： A static random access memory (SRAM) is provided. The SRAM structure includes an SRAM array, a word line decoder, and a reference bit line device. The SRAM array comprises at least one SRAM bit cell made up of six transistors. The word line decoder is used for decoding a word line of the SRAM bit cell array such that the word line is activated at a starting time and is deactivated at a ending time. The reference bit line device is connected between the SRAM array and the word line decoder and is used for pre-deactivating the word line at a predetermined time before the ending time such that a voltage difference between a bit line and a bit line bar of the SRAM bit cell is equal to a predetermined voltage.
摘要翻译：提供了静态随机存取存储器（SRAM）。 SRAM结构包括SRAM阵列，字线解码器和参考位线装置。 SRAM阵列包括由六个晶体管构成的至少一个SRAM位单元。字线解码器用于对SRAM位单元阵列的字线进行解码，使得字线在开始时被激活，并在结束时被去激活。参考位线装置连接在SRAM阵列和字线解码器之间，并且用于在结束时间之前的预定时间预停换字线，使得位线和位线条之间的电压差 SRAM位单元等于预定电压。

8. 发明授权

US07956655B1 Output pad system and pad driving circuit thereof 有权
标题翻译：输出垫系统及其垫驱动电路
公开(公告)号：US07956655B1
公开(公告)日：2011-06-07
申请号：US12659884
申请日：2010-03-24
申请人： Chun-Yu Chiu
发明人： Chun-Yu Chiu
IPC分类号： H03B1/00
CPC分类号： H03K19/017581 , G11C7/1057 , G11C7/1069
摘要： A pad driving circuit includes an output control circuit, a voltage pump circuit, a first buffer series, and a second buffer series. The output control circuit controls whether a pad circuit can pass an input signal, in which the output control circuit enables the pad circuit to output the input signal when an enable signal is asserted. The voltage pump circuit generates a negative supply voltage having voltage less than a zero volt. The first buffer series, electrically connected between the output control circuit and the pad circuit, drives the pad circuit with a positive supply voltage and the negative supply voltage from the voltage pump circuit. The second buffer series drives the pad circuit with a ground voltage and the positive supply voltage.
摘要翻译：焊盘驱动电路包括输出控制电路，电压泵电路，第一缓冲器系列和第二缓冲器系列。输出控制电路控制焊盘电路是否可以通过输入信号，其中输出控制电路使能焊盘电路在使能信号有效时输出输入信号。电压泵电路产生电压低于零伏的负电源电压。电连接在输出控制电路和焊盘电路之间的第一缓冲器系列以正电源电压和来自电压泵电路的负电源电压驱动焊盘电路。第二个缓冲器系列以接地电压和正电源电压驱动焊盘电路。

9. 发明授权

US08432725B2 Static random access memory structure and control method thereof 有权
标题翻译：静态随机存取存储器结构及其控制方法
公开(公告)号：US08432725B2
公开(公告)日：2013-04-30
申请号：US13190031
申请日：2011-07-25
申请人： Chun-Yu Chiu
发明人： Chun-Yu Chiu
IPC分类号： G11C8/08
CPC分类号： G11C11/417
摘要： A static random access memory (SRAM) is provided. The SRAM structure includes an SRAM array, a word line decoder, and a reference bit line device. The SRAM array comprises at least one SRAM bit cell made up of six transistors. The word line decoder is used for decoding a word line of the SRAM bit cell array such that the word line is activated at a starting time and is deactivated at a ending time. The reference bit line device is connected between the SRAM array and the word line decoder and is used for pre-deactivating the word line at a predetermined time before the ending time such that a voltage difference between a bit line and a bit line bar of the SRAM bit cell is equal to a predetermined voltage.
摘要翻译：提供了静态随机存取存储器（SRAM）。 SRAM结构包括SRAM阵列，字线解码器和参考位线装置。 SRAM阵列包括由六个晶体管构成的至少一个SRAM位单元。字线解码器用于对SRAM位单元阵列的字线进行解码，使得字线在开始时被激活，并在结束时被去激活。参考位线装置连接在SRAM阵列和字线解码器之间，并且用于在结束时间之前的预定时间预停换字线，使得位线和位线条之间的电压差 SRAM位单元等于预定电压。

10. 发明授权

US08305384B2 System and method for storing and accessing pixel data in a graphics display device 有权
标题翻译：用于在图形显示装置中存储和访问像素数据的系统和方法
公开(公告)号：US08305384B2
公开(公告)日：2012-11-06
申请号：US12775412
申请日：2010-05-06
申请人： Tsung-Han Yang , Chun-Yu Chiu
发明人： Tsung-Han Yang , Chun-Yu Chiu
IPC分类号： G06F13/00
CPC分类号： G09G5/393 , G09G5/397 , G09G5/399 , G09G2352/00 , G09G2360/123
摘要： A graphics display device comprises a first and second memory, and a data transfer controller coupled with the first and second memory. In some embodiments, a method of storing pixel data comprises receiving and latching first pixel data associated with a first pixel, receiving second pixel data associated with a second pixel, and concurrently writing the first pixel data in the first memory and the second pixel data in the second memory. In other embodiments, a method of accessing pixel data of an image frame comprises accessing the first and second memory for reading out pixel data of each pair of adjacent pixels, when the image frame has an odd total number of pixels determining whether a final pixel data is in a latched state, and reading out the final pixel data from the data transfer controller when the final pixel data is in the latched state.
摘要翻译：图形显示装置包括第一和第二存储器以及与第一和第二存储器耦合的数据传输控制器。在一些实施例中，存储像素数据的方法包括：接收和锁存与第一像素相关联的第一像素数据，接收与第二像素相关联的第二像素数据，以及同时将第一像素数据写入第一存储器，将第二像素数据写入第二个记忆。在其他实施例中，访问图像帧的像素数据的方法包括访问第一和第二存储器以读出每对相邻像素的像素数据，当图像帧具有奇数总像素数量时，确定最终像素数据处于锁存状态，并且当最终像素数据处于锁存状态时，从数据传输控制器读出最终像素数据。

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