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    • 5. 发明申请
    • SYSTEM, MEDIUM, AND METHOD OF ENCODING/DECODING MULTI-CHANNEL AUDIO SIGNALS
    • 系统,媒体和编码/解码多通道音频信号的方法
    • US20120321090A1
    • 2012-12-20
    • US13599147
    • 2012-08-30
    • Junghoe KIMMiao LeiEunmi Oh
    • Junghoe KIMMiao LeiEunmi Oh
    • H04R5/00
    • H03M7/30G10L19/008G10L19/167H04H20/80H04S3/002H04S3/008H04S2420/03
    • An system, method, and method of encoding/decoding a multi-channel audio signal, including a decoding level generation unit producing decoding-level information that helps a bitstream including a number of audio channel signals and space information to be decoded into a number of audio channel signals, wherein the space information includes information about magnitude differences and/or similarities between channels, and an audio decoder decoding the bitstream according to the decoding-level information. Accordingly, even a single input bitstream can be decoded into a suitable number of channels depending on the type of a speaker configuration used. Scalable channel decoding can be achieved by partially decoding an input bitstream. In the scalable channel decoding, a decoder may set decoding levels and outputs audio channel signals according to the decoding levels, thereby reducing decoding complexity.
    • 一种对多声道音频信号进行编码/解码的系统,媒体和方法,包括解码电平生成单元,其产生解码级信息,该解码电平信息有助于将包含多个音频信道信号的位流和空间信息解码为多个 音频信道信号,其中所述空间信息包括关于信道之间的幅度差异和/或相似性的信息,以及根据所述解码级别信息对所述比特流进行解码的音频解码器。 因此,即使单个输入比特流也可以根据所使用的扬声器配置的类型被解码为适当数量的信道。 可以通过对输入比特流进行部分解码来实现可扩展的信道解码。 在可扩展信道解码中,解码器可以根据解码电平设置解码电平并输出音频信道信号,从而降低解码复杂度。
    • 8. 发明授权
    • Parallel testing in a per-pin hardware architecture platform
    • 在每个针脚硬件架构平台上进行并行测试
    • US07853425B1
    • 2010-12-14
    • US12171765
    • 2008-07-11
    • Jerold A. WilliamsonMichael ChaoJoseph N. FurioMiao Lei
    • Jerold A. WilliamsonMichael ChaoJoseph N. FurioMiao Lei
    • G01R31/28G06F11/263
    • G01R31/2834G01R31/31907
    • Provided is a method and system for testing a DUT. The system includes a plurality of testing devices for interacting with the DUT and conducting a plurality of different tests on the DUT, and a computer-readable memory for storing computer-executable instructions defining the plurality of tests to be conducted by the testing device on the DUT. A scheduler component designates at least a first test and a second test from the plurality of tests to be conducted on the DUT in parallel, wherein said designating is based at least in part on content of the computer-executable instructions defining the first test and the second test. And a controller initiates the first test and the second test to be conducted in parallel and initiating at least a third test sequentially relative to at least one of the first and second tests.
    • 提供了一种用于测试DUT的方法和系统。 该系统包括用于与DUT进行交互并在DUT上执行多个不同测试的多个测试装置,以及用于存储计算机可执行指令的计算机可读存储器,该计算机可读存储器用于定义要由所述测试装置进行的多个测试 DUT。 调度器组件至少指定要在DUT上并行进行的多个测试中的至少第一测试和第二测试,其中所述指定至少部分地基于定义第一测试的计算机可执行指令的内容和 第二次测试。 并且控制器启动第一测试并且第二测试并行进行并且相对于第一和第二测试中的至少一个依次启动至少第三测试。
    • 10. 发明授权
    • Parallel test architecture
    • 并行测试架构
    • US07680619B1
    • 2010-03-16
    • US11141451
    • 2005-05-31
    • Miao Lei
    • Miao Lei
    • G06F13/14
    • G01R31/318371
    • A measurement system for testing a DUT includes a plurality of procedures for performing test functions, each procedure having a phase variable; a task queue where the procedures are entered in the task queue with a sign-up value of the phase variable; and a multiphase task executor that arranges the procedures in the queue in response to the sign-up value. The executor changes the phase variable to an execution value and executes the procedures in the task queue after the phase variable has the execution value.
    • 用于测试DUT的测量系统包括用于执行测试功能的多个过程,每个过程具有相位变量; 任务队列,其中过程在阶段变量的注册值中输入到任务队列中; 以及多个任务执行器,用于响应于注册值排列队列中的过程。 执行器将相位变量更改为执行值,并在相位变量具有执行值之后执行任务队列中的过程。