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1. 发明申请

US20100027361A1 Information Handling System with SRAM Precharge Power Conservation 失效
标题翻译：具有SRAM预充电功能的信息处理系统
公开(公告)号：US20100027361A1
公开(公告)日：2010-02-04
申请号：US12185234
申请日：2008-08-04
申请人： Michael Ju Hyeok Lee , Bao G. Truong
发明人： Michael Ju Hyeok Lee , Bao G. Truong
IPC分类号： G11C7/00
CPC分类号： G11C7/12 , G11C11/413
摘要： An information handling system (IHS) includes a processor with on-chip or off-chip SRAM array. After a read operation, a control circuit may instruct the SRAM array to conduct a precharge operation, or alternatively, instruct the SRAM array to conduct an equalize bitline voltage operation. A read operation may follow the precharge operation or the equalize bitline voltage operation. The control circuit may instruct the SRAM array to conduct an equalize bitline voltage operation if an equalized voltage of a bitline pair exhibits more that a predetermined amount of voltage. Otherwise, the control circuit instructs the SRAM array to conduct a precharge operation before the next read operation.
摘要翻译：信息处理系统（IHS）包括具有片上或片外SRAM阵列的处理器。在读取操作之后，控制电路可以指示SRAM阵列进行预充电操作，或者替代地指示SRAM阵列进行均衡的位线电压操作。读取操作可以遵循预充电操作或均衡位线电压操作。如果位线对的均衡电压显示出更多的预定量的电压，则控制电路可以指示SRAM阵列进行均衡的位线电压操作。否则，控制电路指示SRAM阵列在下一次读取操作之前进行预充电操作。

2. 发明申请

US20100002525A1 Array Data Input Latch and Data Clocking Scheme 失效
标题翻译：阵列数据输入锁存器和数据时钟方案
公开(公告)号：US20100002525A1
公开(公告)日：2010-01-07
申请号：US12166421
申请日：2008-07-02
申请人： Yuen Hung Chan , Elspeth Anne Huston , Michael Ju Hyeok Lee
发明人： Yuen Hung Chan , Elspeth Anne Huston , Michael Ju Hyeok Lee
IPC分类号： G11C7/00 , G11C8/18
CPC分类号： G11C7/1078 , G11C7/1087 , G11C7/1093 , G11C7/22
摘要： A data input latch and clocking method and apparatus for high performance SRAM in which an L1 data input latch is controlled by a logical combination of the normal local clock buffer clock signal and the local array clock buffer clock signal. This logical combination of clock signals minimizes the hold time of the L1 latch provides a fast cycle time in which the SRAM macro can process successive write instructions while avoiding early mode issues.
摘要翻译：一种用于高性能SRAM的数据输入锁存和时钟方法和装置，其中L1数据输入锁存器由正常本地时钟缓冲时钟信号和本地阵列时钟缓冲时钟信号的逻辑组合控制。时钟信号的这种逻辑组合使得L1锁存器的保持时间最小化提供了快速周期时间，其中SRAM宏可以处理连续写指令，同时避免早期模式问题。

3. 发明申请

US20080270963A1 SYSTEM AND COMPUTER PROGRAM FOR VERIFYING PERFORMANCE OF AN ARRAY BY SIMULATING OPERATION OF EDGE CELLS IN A FULL ARRAY MODEL 有权
标题翻译：通过模拟边缘细胞在全阵列模型中的操作来验证阵列性能的系统和计算机程序
公开(公告)号：US20080270963A1
公开(公告)日：2008-10-30
申请号：US12166811
申请日：2008-07-02
申请人： Vikas Agarwal , Michael Ju Hyeok Lee , Philip G. Shephard
发明人： Vikas Agarwal , Michael Ju Hyeok Lee , Philip G. Shephard
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： A system and computer program for verifying performance of an array by simulating operation of edge cells in a full array model reduces the computation time required for complete design verification. The edge cells of the array (or each subarray if the array is partitioned) are subjected to a timing simulation while the center cells of the array are logically disabled, but remain in the circuit model, providing proper loading. Additional cells are specified for simulation if calculations indicate a worst-case condition due to a non-edge cell. Wordline arrivals are observed to determine worst-case rows for selection. For write operations, the difference between the wordline edges and the data edges is used to locate any non-edge “outlier” cells. For read operations, the wordline delays are summed with the bitline delays determined from edge column data to locate any outliers.
摘要翻译：通过模拟全阵列模型中边缘单元的操作来验证阵列的性能的系统和计算机程序减少了完整设计验证所需的计算时间。阵列的边缘单元（或阵列分割的每个子阵列）经受定时仿真，而阵列的中心单元在逻辑上被禁用，但保留在电路模型中，从而提供适当的加载。如果计算指示由于非边缘单元造成的最坏情况，则指定额外的单元用于模拟。观察到字线到达以确定最坏情况行进行选择。对于写入操作，字边和数据边之间的差异用于定位任何非边缘“异常值”单元。对于读取操作，字线延迟与从边沿列数据确定的位线延迟相加以定位任何异常值。

4. 发明授权

US07167385B2 Method and apparatus for controlling the timing of precharge in a content addressable memory system 有权
标题翻译：用于控制内容可寻址存储器系统中的预充电时序的方法和装置
公开(公告)号：US07167385B2
公开(公告)日：2007-01-23
申请号：US11055802
申请日：2005-02-11
申请人： Yuen Hung Chan , Masood Ahmed Khan , Michael Ju Hyeok Lee , Ed Seewann
发明人： Yuen Hung Chan , Masood Ahmed Khan , Michael Ju Hyeok Lee , Ed Seewann
IPC分类号： G11C15/00
CPC分类号： G11C15/00
摘要： A CAM system is disclosed in which compare data, for example an address translation request, is provided as input search data to a search line generator. The search line generator presents search line input data, through a buffer, to CAM and RAM array systems that include dynamically precharged and evaluated memory cells. Timing sequences in the CAM system are controlled by a series of individually triggered one shot pulse generators. The one shot pulse generators control the timing of CAM system activities, for example the precharge of CAM subsystems, so that these activities are staggered in time. This timing approach improves power consumption and evaluation time within the CAM system. By distributing precharging activities in time throughout the CAM cycle, current peaking during the CAM cycle is reduced. The CAM system latches results in an output latch that is controlled by a one shot pulse generator.
摘要翻译：公开了一种CAM系统，其中将比较数据（例如地址转换请求）作为输入搜索数据提供给搜索线发生器。搜索线生成器通过缓冲器将搜索线输入数据呈现给包括动态预充电和评估的存储器单元的CAM和RAM阵列系统。 CAM系统中的定时序列由一系列单独触发的单脉冲发生器控制。单脉冲发生器控制CAM系统活动的时间，例如CAM子系统的预充电，以便这些活动及时交错。该定时方法提高了CAM系统的功耗和评估时间。通过在整个CAM循环中及时分配预充电活动，CAM循环期间的当前峰值降低。 CAM系统锁存器产生由单触发脉冲发生器控制的输出锁存器。

5. 发明授权

US07142463B2 Register file method incorporating read-after-write blocking using detection cells 失效
公开(公告)号：US07142463B2
公开(公告)日：2006-11-28
申请号：US11242376
申请日：2005-10-03
申请人： Sam Gat-Shang Chu , Peter Juergen Klim , Michael Ju Hyeok Lee , Jose Angel Paredes
发明人： Sam Gat-Shang Chu , Peter Juergen Klim , Michael Ju Hyeok Lee , Jose Angel Paredes
IPC分类号： G11C7/10
CPC分类号： G11C7/22
摘要： A register file method incorporating read-after-write blocking using detection cells provides improved read access times in high performance register files. One or more detection cells identical to the register file cells and located in the register file array are used to control the read operation in the register file by configuring the detection cells to either alternate value at each write or change to a particular value after a write and then detecting when the write has completed by detecting the state change of an active detection cell. The state change detection can be used to delay the leading edge of a read strobe or may be used in the access control logic to delay generation of a next read strobe. The register file thus provides a scalable design that does not have to be tuned for each application and that tracks over voltage and clock skew variation.

6. 发明授权

US07116569B2 Method and apparatus for selecting operating characteristics of a content addressable memory by using a compare mask 失效
标题翻译：通过使用比较掩码来选择内容可寻址存储器的操作特性的方法和装置
公开(公告)号：US07116569B2
公开(公告)日：2006-10-03
申请号：US11055803
申请日：2005-02-11
申请人： Joaquin Hinojosa , Eric Jason Fluhr , Michael Ju Hyeok Lee , Jose Angel Paredes , Ed Seewann
发明人： Joaquin Hinojosa , Eric Jason Fluhr , Michael Ju Hyeok Lee , Jose Angel Paredes , Ed Seewann
IPC分类号： G11C15/00
CPC分类号： G06F12/1027 , G06F2212/652 , G11C15/00
摘要： A CAM system is disclosed in which requests for address translation are provided as input search data to a dynamic compare bitline generator. The dynamic compare bitline generator also receives a compare mask and applies the compare mask to associated input search data bits on a per bit basis. The mask contains information that specifies a selected page size and a selected logic mode that can be applied to a compare array in which the specified search is conducted. The compare array is coupled to a data array to which the compare array indicates a result of the search.
摘要翻译：公开了一种CAM系统，其中将地址转换请求作为输入搜索数据提供给动态比较位线发生器。动态比较位线发生器还接收比较掩码，并以比特的形式将比较掩码应用于相关的输入搜索数据位。掩码包含指定所选页面大小的信息和可应用于进行指定搜索的比较数组的选定逻辑模式。比较数组耦合到比较数组指示搜索结果的数据阵列。

7. 发明授权

US07012839B1 Register file apparatus and method incorporating read-after-write blocking using detection cells 失效
标题翻译：使用检测单元的注册文件装置和包含读写后封锁的方法
公开(公告)号：US07012839B1
公开(公告)日：2006-03-14
申请号：US10922247
申请日：2004-08-19
申请人： Sam Gat-Shang Chu , Peter Juergen Klim , Michael Ju Hyeok Lee , Jose Angel Paredes
发明人： Sam Gat-Shang Chu , Peter Juergen Klim , Michael Ju Hyeok Lee , Jose Angel Paredes
IPC分类号： G11C5/02
CPC分类号： G11C7/22
摘要： A register file apparatus and method incorporating read-after-write blocking using detection cells provides improved read access times in high performance register files. One or more detection cells identical to the register file cells and located in the register file array are used to control the read operation in the register file by configuring the detection cells to either alternate value at each write or change to a particular value after a write and then detecting when the write has completed by detecting the state change of an active detection cell. The state change detection can be used to delay the leading edge of a read strobe or may be used in the access control logic to delay generation of a next read strobe. The register file thus provides a scalable design that does not have to be tuned for each application and that tracks over voltage and clock skew variation.
摘要翻译：使用检测单元结合读写后阻塞的寄存器文件装置和方法在高性能寄存器文件中提供改进的读访问时间。与寄存器文件单元相同并且位于寄存器文件阵列中的一个或多个检测单元用于通过将检测单元配置为在写入时的交替值或在写入之后变为特定值来控制寄存器文件中的读取操作然后通过检测有源检测单元的状态变化来检测写入是否已经完成。状态改变检测可以用于延迟读选通脉冲的前沿，或者可以在访问控制逻辑中使用以延迟下一个读选通脉冲的产生。寄存器文件因此提供了一种可扩展的设计，不需要针对每个应用进行调整，并且跟踪过电压和时钟偏移变化。

8. 发明授权

US06934181B2 Reducing sub-threshold leakage in a memory array 有权
标题翻译：减少存储器阵列中的次阈值泄漏
公开(公告)号：US06934181B2
公开(公告)日：2005-08-23
申请号：US10361200
申请日：2003-02-06
申请人： Sam Gat-Shang Chu , Peter Juergen Klim , Michael Ju Hyeok Lee , Jose Angel Paredes
发明人： Sam Gat-Shang Chu , Peter Juergen Klim , Michael Ju Hyeok Lee , Jose Angel Paredes
IPC分类号： G11C7/00 , G11C11/00 , G11C11/412
CPC分类号： G11C11/412
摘要： A method and memory array for reducing sub-threshold leakage in a memory array. A memory array may include a plurality of rows where each row may include one or more groups of cells. Within each group of cells, each cell may be coupled to a ground path and to a power path. A device, e.g., n-type transistor, p-type transistor, may be coupled to either the ground or power path in each group of cells thereby permitting the passing of the sub-threshold leakage from those cells in that group through the device. Consequently, the sub-threshold leakage in the memory array may be reduced.
摘要翻译：一种用于减少存储器阵列中的次阈值泄漏的方法和存储器阵列。存储器阵列可以包括多行，其中每行可以包括一个或多个单元组。在每个单元组内，每个单元可以耦合到接地路径和功率路径。诸如n型晶体管p型晶体管的器件可以耦合到每组单元中的接地或电源通路，从而允许从该组中的那些单元通过器件传递子阈值泄漏。因此，可以减少存储器阵列中的次阈值泄漏。

9. 发明授权

US06914450B2 Register-file bit-read method and apparatus 失效
标题翻译：寄存器文件位读取方法和装置
公开(公告)号：US06914450B2
公开(公告)日：2005-07-05
申请号：US10703016
申请日：2003-11-06
申请人： Sam Gat-Shang Chu , Peter Juergen Klim , Michael Ju Hyeok Lee , Jose Angel Paredes
发明人： Sam Gat-Shang Chu , Peter Juergen Klim , Michael Ju Hyeok Lee , Jose Angel Paredes
IPC分类号： G06F7/38 , G11C7/10 , H03K19/0175 , H03K19/173
CPC分类号： G11C7/1048 , G11C2207/007
摘要： A register-file bit read apparatus includes a decoder operable to receive a number of address-bit signals and responsively assert a select signal on one of M select lines. Each select line corresponds to a respective one of M register-file cells. The apparatus also includes a multiplexer having Q output nodes and M selectors. Each selector is coupled to one of the select lines and that select line's corresponding register-file cell. The selectors are in Q groups, each coupled to a respective one of the multiplexer's output nodes. The apparatus also includes an output logic gate having Q inputs, coupled to respective ones of the multiplexer output nodes. The multiplexer includes Q pull-ups, each of which is coupled to a respective one of the multiplexer output nodes and is operable to drive its multiplexer output node responsive to one of the address-bit signals.
摘要翻译：寄存器 - 文件位读取装置包括：解码器，可操作用于接收多个地址位信号，并响应地在M个选择行之一中断言选择信号。每个选择行对应于M个寄存器文件单元中的相应一个。该装置还包括具有Q个输出节点和M个选择器的多路复用器。每个选择器耦合到选择线之一，并选择线对应的寄存器文件单元。选择器处于Q组中，每组耦合到多路复用器的输出节点中的相应一个。该装置还包括具有Q输入的输出逻辑门，耦合到多路复用器输出节点中的相应一个。多路复用器包括Q个上拉，其中每个Q上拉耦合到多路复用器输出节点中的相应一个，并且可操作以响应于地址位信号之一驱动其多路复用器输出节点。

10. 发明授权

US06826090B1 Apparatus and method for a radiation resistant latch 失效
标题翻译：用于防辐射闩锁的装置和方法
公开(公告)号：US06826090B1
公开(公告)日：2004-11-30
申请号：US10455161
申请日：2003-06-05
申请人： Sam Gat-Shang Chu , Peter Juergen Klim , Michael Ju Hyeok Lee , Jose Angel Paredes
发明人： Sam Gat-Shang Chu , Peter Juergen Klim , Michael Ju Hyeok Lee , Jose Angel Paredes
IPC分类号： G11C700
CPC分类号： G11C7/02 , G11C7/24
摘要： In one form of the invention, a radiation resistant latch has an overall output node, and first, second and third sublatches. The sublatches each have input circuitry, an output node coupled to the sublatch's input circuitry and feedback circuitry coupled to the sublatch's output node for reinforcing an output signal of the sublatch. The sublatches are operable to receive a data signal at their respective input circuitry and responsively generate binary-state output signals on their respective output nodes. The first and second sublatches are coupled to the third sublatch and the third sublatch has its output signal coupled to the overall output node such that if any one of the three sublatches is subjected to a radiation induced erroneous change of state, the output signals of the other two sublatches reduce an effect of the third sublatch feedback circuitry on an overall output signal for the latch.
摘要翻译：在本发明的一种形式中，耐辐射闩锁具有总输出节点以及第一，第二和第三子实体。这些分样具有输入电路，耦合到分页输入电路的输出节点和耦合到分页输出节点的反馈电路，用于加强子画面的输出信号。这些副作用可操作以在它们各自的输入电路处接收数据信号，并在其各自的输出节点上响应地产生二进制状态输出信号。第一和第二子集合被耦合到第三子交集，并且第三子选项具有耦合到整个输出节点的输出信号，使得如果三个子集合中的任何一个受到辐射引起的状态的错误改变，则输出信号其他两个分样可以减少第三个分支反馈电路对锁存器的总输出信号的影响。

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