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1. 发明申请

US20060043422A1 Transistor structure with stress modification and capacitive reduction feature in a width direction and method thereof 有权
标题翻译：具有应力改变和宽度方向的电容减小特性的晶体管结构及其方法
公开(公告)号：US20060043422A1
公开(公告)日：2006-03-02
申请号：US10925084
申请日：2004-08-24
申请人： Jian Chen , Michael Mendicino , Vance Adams , Choh-Fei Yeap , Venkat Kolagunta
发明人： Jian Chen , Michael Mendicino , Vance Adams , Choh-Fei Yeap , Venkat Kolagunta
IPC分类号： H01L29/76 , H01L31/113
CPC分类号： H01L29/7843 , H01L21/823807 , H01L21/823814 , H01L21/823828
摘要： A transistor comprises a source and drain positioned within an active region. A gate overlies a channel area of the active region, wherein the channel region separates the source and drain. The transistor further comprises at least one stress modifier and capacitive reduction feature extending from the source to the drain and underlying the gate for reducing capacitance associated with the gate, source and drain. The at least one stress modifier and capacitive reduction feature comprises dielectric and includes a shape defined at least partially by the active region.
摘要翻译：晶体管包括位于有源区域内的源极和漏极。栅极覆盖有源区的沟道区，其中沟道区分离源极和漏极。晶体管还包括至少一个应力调节器和电容降低特征，其从源极延伸到漏极并且在栅极下方，用于减小与栅极，源极和漏极相关联的电容。所述至少一个应力调节剂和电容还原特征包括电介质并且包括至少部分地由有源区限定的形状。

2. 发明申请

US20050275018A1 Semiconductor device with multiple semiconductor layers 审中-公开
标题翻译：具有多个半导体层的半导体器件
公开(公告)号：US20050275018A1
公开(公告)日：2005-12-15
申请号：US10865351
申请日：2004-06-10
申请人： Suresh Venkatesan , Mark Foisy , Michael Mendicino , Marius Orlowski
发明人： Suresh Venkatesan , Mark Foisy , Michael Mendicino , Marius Orlowski
IPC分类号： H01L21/8234 , H01L21/8238 , H01L21/84 , H01L27/12
CPC分类号： H01L21/84 , H01L21/823807 , H01L27/1203
摘要： A semiconductor device structure uses two semiconductor layers to separately optimize N and P channel transistor carrier mobility. The conduction characteristic for determining this is a combination of material type of the semiconductor, crystal plane, orientation, and strain. Hole mobility is improved in P channel transistors when the conduction characteristic is characterized by the semiconductor material being silicon germanium, the strain being compressive, the crystal plane being (100), and the orientation being . In the alternative, the crystal plane can be (111) and the orientation in such case is unimportant. The preferred substrate for N-type conduction is different from the preferred (or optimum) substrate for P-type conduction. The N channel transistors preferably have tensile strain, silicon semiconductor material, and a (100) plane. With the separate semiconductor layers, both the N and P channel transistors can be optimized for carrier mobility.
摘要翻译：半导体器件结构使用两个半导体层来分别优化N沟道晶体管和P沟道晶体管的载流子迁移率。用于确定的导电特性是半导体的材料类型，晶面，取向和应变的组合。当导电特性的特征在于半导体材料为硅锗时，p型沟道晶体管的空穴迁移率得到改善，应变为压缩，晶面为（100），取向为100。或者，晶面可以是（111），在这种情况下的取向是不重要的。用于N型导电的优选衬底不同于用于P型导电的优选（或最佳）衬底。 N沟道晶体管优选具有拉伸应变，硅半导体材料和（100）平面。通过分开的半导体层，N沟道晶体管和P沟道晶体管都可以优化载流子迁移率。

3. 发明申请

US20060043500A1 Transistor structure with stress modification and capacitive reduction feature in a channel direction and method thereof 审中-公开
标题翻译：具有应力改变和通道方向的电容降低特性的晶体管结构及其方法
公开(公告)号：US20060043500A1
公开(公告)日：2006-03-02
申请号：US10925057
申请日：2004-08-24
申请人： Jian Chen , Michael Mendicino , Vance Adams , Choh-Fei Yeap , Venkat Kolagunta
发明人： Jian Chen , Michael Mendicino , Vance Adams , Choh-Fei Yeap , Venkat Kolagunta
IPC分类号： H01L29/76 , H01L29/94
CPC分类号： H01L29/78 , H01L29/7843
摘要： A transistor comprises an active region having a periphery with opposing sides and a source and a drain positioned within the active region. A gate overlies a channel area of the active region, the channel region separating the source and drain. The transistor further includes at least one stress modifying feature extending from an edge of the active region on at least one of a source side or a drain side and toward the channel area but not entering the channel area. The at least one stress modifying feature includes a dielectric.
摘要翻译：晶体管包括具有相对侧边缘的有源区和位于有源区内的源极和漏极。 A栅极覆盖有源区的沟道区，沟道区分离源极和漏极。晶体管还包括至少一个应力调整特征，其从源极侧或漏极侧中的至少一个上方的有源区域的边缘延伸并且朝向沟道区域而不进入沟道区域。所述至少一个应力改变特征包括电介质。

4. 发明申请

US20050167782A1 Semiconductor device having an aligned transistor and capacitive element 有权
标题翻译：具有对准的晶体管和电容元件的半导体器件
公开(公告)号：US20050167782A1
公开(公告)日：2005-08-04
申请号：US11098070
申请日：2005-04-04
申请人： Hector Sanchez , Michael Mendicino , Byoung Min , Kathleen Ju
发明人： Hector Sanchez , Michael Mendicino , Byoung Min , Kathleen Ju
IPC分类号： H01L21/02 , H01L21/768 , H01L21/84 , H01L23/48 , H01L23/522 , H01L27/06 , H01L27/12 , H01L23/053
CPC分类号： H01L27/0688 , H01L21/76838 , H01L21/76898 , H01L21/84 , H01L23/481 , H01L23/5223 , H01L27/1203 , H01L28/40 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor (10) has an active device, such as a transistor, with a directly underlying passive device, such as a capacitor (75, 77, 79), that are connected by a via or conductive region (52) and interconnect (68, 99). The via or conductive region (52) contacts a bottom surface of a diffusion or source region (22) of the transistor and contacts a first (75) of the capacitor electrodes. A laterally positioned vertical via (32, 54, 68) and interconnect (99) contacts a second (79) of the capacitor electrodes. A metal interconnect or conductive material (68) may be used as a power plane that saves circuit area by implementing the power plane underneath the transistor rather than adjacent the transistor.
摘要翻译：半导体（10）具有诸如晶体管的有源器件，其具有通过通孔或导电区域（52）和互连（68）连接的直接下伏的无源器件，例如电容器（75,77,79），99）。通孔或导电区域（52）接触晶体管的扩散或源极区域（22）的底表面并与第一（75）电容器电极接触。横向定位的垂直通孔（32,54,68）和互连件（99）接触电容器电极的第二（79）。金属互连或导电材料（68）可以用作通过在晶体管下面实现功率平面而不是与晶体管相邻来节省电路面积的功率面。

5. 发明申请

US20070184600A1 Stressed-channel CMOS transistors 审中-公开
标题翻译：高通道CMOS晶体管
公开(公告)号：US20070184600A1
公开(公告)日：2007-08-09
申请号：US11348034
申请日：2006-02-06
申请人： Da Zhang , Michael Mendicino , Bich-Yen Nguyen
发明人： Da Zhang , Michael Mendicino , Bich-Yen Nguyen
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823814 , H01L29/165 , H01L29/665 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： Methods for forming portions of source and drain (S/D) regions of a first ensuing transistor (40) to include a semiconductor material (47) having a different composition of non-dopant elements than portions of S/D regions (35) of a second ensuing transistor (30) of opposite conductivity type are provided. The methods additionally include forming another semiconductor material (48) upon at least one set of the S/D regions of the ensuing transistors such that S/D surface layers of the ensuing transistors include substantially the same composition of non-dopant elements. A resulting semiconductor topography includes a pair of CMOS transistors (30, 40) collectively having S/D region surfaces with substantially the same composition of non-dopant elements. The S/D regions of one transistor (40) of the pair of CMOS transistors includes an underlying layer (47) having a different composition of non-dopant elements than underlying layers of the S/D regions (35) of the other transistor (30).
摘要翻译：用于形成第一随后晶体管（40）的源极和漏极（S / D）区域的部分的方法，以包括具有与S / D区域（35）的部分不同的非掺杂元素的不同组成的半导体材料（47）提供了具有相反导电类型的第二随后的晶体管（30）。所述方法还包括在随后的晶体管的至少一组S / D区上形成另一半导体材料（48），使得随后的晶体管的S / D表面层包括基本上相同的非掺杂元素组成。所得到的半导体形貌包括一对共同具有基本上相同组成的非掺杂元素的S / D区域表面的CMOS晶体管（30,40）。该对CMOS晶体管的一个晶体管（40）的S / D区域包括与另一个晶体管的S / D区域（35）的下层不同的非掺杂元素组成的下层（47） 30）。

6. 发明申请

US20060194384A1 SEMICONDUCTOR DEVICE WITH MULTIPLE SEMICONDUCTOR LAYERS 审中-公开
标题翻译：具有多个半导体层的半导体器件
公开(公告)号：US20060194384A1
公开(公告)日：2006-08-31
申请号：US11382432
申请日：2006-05-09
申请人： Suresh Venkatesan , Mark Foisy , Michael Mendicino , Marius Orlowski
发明人： Suresh Venkatesan , Mark Foisy , Michael Mendicino , Marius Orlowski
IPC分类号： H01L21/8238
CPC分类号： H01L21/84 , H01L21/823807 , H01L27/1203
摘要： A semiconductor device structure uses two semiconductor layers to separately optimize N and P channel transistor carrier mobility. The conduction characteristic for determining this is a combination of material type of the semiconductor, crystal plane, orientation, and strain. Hole mobility is improved in P channel transistors when the conduction characteristic is characterized by the semiconductor material being silicon germanium, the strain being compressive, the crystal plane being (100), and the orientation being . In the alternative, the crystal plane can be (111) and the orientation in such case is unimportant. The preferred substrate for N-type conduction is different from the preferred (or optimum) substrate for P-type conduction. The N channel transistors preferably have tensile strain, silicon semiconductor material, and a (100) plane. With the separate semiconductor layers, both the N and P channel transistors can be optimized for carrier mobility.
摘要翻译：半导体器件结构使用两个半导体层来分别优化N沟道晶体管和P沟道晶体管的迁移率。用于确定的导电特性是半导体的材料类型，晶面，取向和应变的组合。当导电特性的特征在于半导体材料为硅锗时，p型沟道晶体管的空穴迁移率得到改善，应变为压缩，晶面为（100），取向为100。或者，晶面可以是（111），在这种情况下的取向是不重要的。用于N型导电的优选衬底不同于用于P型导电的优选（或最佳）衬底。 N沟道晶体管优选具有拉伸应变，硅半导体材料和（100）平面。通过分开的半导体层，N沟道晶体管和P沟道晶体管都可以优化载流子迁移率。

7. 发明申请

US20160278349A1 Immunocompromised Ungulates 审中-公开
标题翻译：免疫受损的有蹄类动物
公开(公告)号：US20160278349A1
公开(公告)日：2016-09-29
申请号：US14665517
申请日：2015-03-23
申请人： David L. Ayares , Michael Mendicino , Kevin Wells , Amy Dandro
发明人： David L. Ayares , Michael Mendicino , Kevin Wells , Amy Dandro
IPC分类号： A01K67/027 , C12N15/85
CPC分类号： A01K67/0276 , A01K67/0273 , A01K67/0275 , A01K2217/052 , A01K2217/075 , A01K2227/108 , A01K2267/01 , A01K2267/0387 , C07K14/70521 , C07K2319/30 , C12N15/8509 , C12N2015/8518 , C12N2015/8527 , G01N33/5088
摘要： Porcine animals, tissue and organs as well as cells and cell lines derived from such animals are provided that lack functional endogenous immunoglobulin loci and are deficient in immunoglobulin expression and B-cells. These animals are useful as model systems for research and for development of new pharmaceutical and biological agents. In addition, methods are provided to prepare such animals.
摘要翻译：提供猪动物，组织和器官以及源自这些动物的细胞和细胞系，其缺乏功能性内源性免疫球蛋白基因座并且缺乏免疫球蛋白表达和B细胞。这些动物可用作研究和开发新的药物和生物制剂的模型系统。此外，提供了制备这种动物的方法。

8. 发明申请

US20120090039A1 Immunocompromised Ungulates 审中-公开
标题翻译：免疫受损的有蹄类动物
公开(公告)号：US20120090039A1
公开(公告)日：2012-04-12
申请号：US13092242
申请日：2011-04-22
申请人： David L. Ayares , Michael Mendicino , Kevin Wells , Amy Dandro
发明人： David L. Ayares , Michael Mendicino , Kevin Wells , Amy Dandro
IPC分类号： G01N33/483 , C12Q1/68 , C12Q1/02 , G01N33/566 , A01K67/027 , C12P21/00
CPC分类号： A01K67/0276 , A01K67/0273 , A01K67/0275 , A01K2217/052 , A01K2217/075 , A01K2227/108 , A01K2267/01 , A01K2267/0387 , C07K14/70521 , C07K2319/30 , C12N15/8509 , C12N2015/8518 , C12N2015/8527 , G01N33/5088
摘要： Porcine animals, tissue and organs as well as cells and cell lines derived from such animals are provided that lack functional endogenous immunoglobulin loci and are deficient in immunoglobulin expression and B-cells. These animals are useful as model systems for research and for development of new pharmaceutical and biological agents. In addition, methods are provided to prepare such animals.
摘要翻译：提供猪动物，组织和器官以及源自这些动物的细胞和细胞系，其缺乏功能性内源性免疫球蛋白基因座并且缺乏免疫球蛋白表达和B细胞。这些动物可用作研究和开发新的药物和生物制剂的模型系统。此外，提供了制备这种动物的方法。

9. 发明申请

US20070200173A1 Embedded substrate interconnect for underside contact to source and drain regions 有权
标题翻译：用于下侧接触源极和漏极区域的嵌入式衬底互连
公开(公告)号：US20070200173A1
公开(公告)日：2007-08-30
申请号：US11356229
申请日：2006-02-16
申请人： Perry Pelley , Troy Cooper , Michael Mendicino
发明人： Perry Pelley , Troy Cooper , Michael Mendicino
IPC分类号： H01L27/12
CPC分类号： H01L29/41733 , H01L21/84 , H01L27/12
摘要： A semiconductor topography (10) is provided which includes a semiconductor-on-insulator (SOI) substrate having a conductive line (16) arranged within an insulating layer (22) of the SOI substrate. A method for forming an SOI substrate with such a configuration includes forming a first conductive line (16) within an insulating layer (22) arranged above a wafer substrate (12) and forming a silicon layer (24) upon surfaces of the first conductive line and the insulating layer. A further method is provided which includes the formation of a transistor gate (28) upon an SOI substrate having a conductive line (16) embedded therein and implanting dopants within the semiconductor topography to form source and drain regions (30) within an upper semiconductor layer (24) of the SOI substrate such that an underside of one of the source and drain regions is in contact with the conductive line.
摘要翻译：提供一种半导体图形（10），其包括绝缘体上半导体（SOI）基板，其具有布置在SOI衬底的绝缘层（22）内的导线（16）。一种用于形成具有这种结构的SOI衬底的方法包括在布置在晶片衬底（12）上方的绝缘层（22）内形成第一导电线（16），并在第一导线的表面上形成硅层（24）和绝缘层。提供了一种另外的方法，其包括在SOI衬底上形成晶体管栅极（28），该SOI衬底具有嵌入其中的导电线（16），并且在半导体拓扑图内注入掺杂剂以在上半导体层内形成源区和漏区（30）（24），使得源极和漏极区域之一的下侧与导电线接触。

10. 发明申请

US20050042867A1 Semiconductor device having electrical contact from opposite sides 有权
标题翻译：具有来自相对侧的电接触的半导体器件
公开(公告)号：US20050042867A1
公开(公告)日：2005-02-24
申请号：US10946758
申请日：2004-09-22
申请人： Hector Sanchez , Michael Mendicino , Byoung Min , Kathleen Yu
发明人： Hector Sanchez , Michael Mendicino , Byoung Min , Kathleen Yu
IPC分类号： H01L21/02 , H01L21/768 , H01L21/84 , H01L23/48 , H01L23/522 , H01L27/06 , H01L27/12 , H01L21/20
CPC分类号： H01L27/0688 , H01L21/76838 , H01L21/76898 , H01L21/84 , H01L23/481 , H01L23/5223 , H01L27/1203 , H01L28/40 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor (10) has an active device, such as a transistor, with a directly underlying passive device, such as a capacitor (75, 77, 79), that are connected by a via or conductive region (52) and interconnect (68, 99). The via or conductive region (52) contacts a bottom surface of a diffusion or source region (22) of the transistor and contacts a first (75) of the capacitor electrodes. A laterally positioned vertical via (32, 54, 68) and interconnect (99) contacts a second (79) of the capacitor electrodes. A metal interconnect or conductive material (68) may be used as a power plane that saves circuit area by implementing the power plane underneath the transistor rather than adjacent the transistor.
摘要翻译：半导体（10）具有诸如晶体管的有源器件，其具有通过通孔或导电区域（52）和互连（68）连接的直接下伏的无源器件，例如电容器（75,77,79），99）。通孔或导电区域（52）接触晶体管的扩散或源极区域（22）的底表面并与第一（75）电容器电极接触。横向定位的垂直通孔（32,54,68）和互连件（99）接触电容器电极的第二（79）。金属互连或导电材料（68）可以用作通过在晶体管下面实现功率平面而不是与晶体管相邻来节省电路面积的功率面。

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