专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07772932B1 Quadrature local oscillator generation for direct conversion radio transceiver 有权
标题翻译：用于直接转换无线电收发器的正交本地振荡器生成
公开(公告)号：US07772932B1
公开(公告)日：2010-08-10
申请号：US11952027
申请日：2007-12-06
申请人： Michael P. Mack
发明人： Michael P. Mack
IPC分类号： H03B21/02
CPC分类号： H03B21/01
摘要： A method of generating a quadrature local oscillator (LO) frequencies is provided. In this method, a voltage-controlled oscillator (VCO) frequency can be mixed with a divided version of the VCO frequency to generate mixed signals. A lower sideband of the mixed signals can be selected for the quadrature LO frequencies to minimize the occurrence of spurs. Notably, the divided version is 1/N of the VCO frequency and the VCO frequency is a radio frequency (RF) channel frequency times a ratio N/(N−1).
摘要翻译：提供了一种产生正交本地振荡器（LO）频率的方法。在该方法中，压控振荡器（VCO）频率可以与VCO频率的分割版本混合以产生混合信号。可以为正交LO频率选择混合信号的下边带以最小化马刺的发生。值得注意的是，分频版本是VCO频率的1 / N，VCO频率是射频（RF）信道频率乘以比率N /（N-1）。

2. 发明授权

US07613430B1 Dual synthesizer RF frequency plan optimized for interference avoidance 有权
标题翻译：双合成器RF频率计划优化用于避免干扰
公开(公告)号：US07613430B1
公开(公告)日：2009-11-03
申请号：US11317876
申请日：2005-12-22
申请人： Michael P. Mack
发明人： Michael P. Mack
IPC分类号： H04B1/40 , H04B1/18
CPC分类号： H04B1/28 , H04B1/10
摘要： Using separate synthesizers in a radio frequency (RF) device can facilitate avoiding interference. Specifically, a first synthesizer can be programmed to generate a first output frequency signal having an Frf frequency. A second synthesizer can be programmed to generate a second output frequency signal having an Fif frequency. Notably, a sum of the Frf and Fif frequencies equals an Fchannel frequency of the RF device. Thus, any RF channel can be received (or transmitted) with a plurality of VCO frequencies for each of the two synthesizers. A table of Frf/Fif combinations can be used to determine an Frf/Fif combination that avoids a known interfering source. Alternatively, Frf/Fif combinations can be randomly chosen until an interfering source is avoided.
摘要翻译：在射频（RF）设备中使用单独的合成器可以有助于避免干扰。具体地说，第一合成器可被编程以产生具有Frf频率的第一输出频率信号。可以对第二合成器进行编程以产生具有Fif频率的第二输出频率信号。值得注意的是，Frf和Fif频率之和等于RF器件的Fchannel频率。因此，可以为两个合成器中的每一个的多个VCO频率接收（或发送）任何RF信道。 Frf / Fif组合表可用于确定避免已知干扰源的Frf / Fif组合。或者，可以随机选择Frf / Fif组合，直到避免干扰源。

3. 发明授权

US06928127B2 Frequency synthesizer with prescaler 失效
标题翻译：带预分频器的频率合成器
公开(公告)号：US06928127B2
公开(公告)日：2005-08-09
申请号：US10387231
申请日：2003-03-11
申请人： Michael P. Mack , Srenik Mehta
发明人： Michael P. Mack , Srenik Mehta
IPC分类号： H03J1/00 , H03L7/197 , H04L7/00
CPC分类号： H03L7/1974 , H03J1/0041
摘要： A frequency synthesizer and a method for frequency synthesis are disclosed. The frequency synthesizer comprises a voltage controlled oscillator for generating an output signal having a synthesized frequency, and a prescaler connected to the VCO for receiving the output signal and providing a feedback signal. The prescaler programmatically selects between an integer divider value and a fractional divider value to divide the synthesized frequency of the output signal.
摘要翻译：公开了频率合成器和频率合成方法。频率合成器包括用于产生具有合成频率的输出信号的压控振荡器和连接到VCO的预分频器，用于接收输出信号并提供反馈信号。预分频器以编程方式选择整数分频值和分数分频值，以分频输出信号的合成频率。

4. 发明授权

US06566908B2 Pulse width distortion correction logic level converter 有权
标题翻译：脉宽失真校正逻辑电平转换器
公开(公告)号：US06566908B2
公开(公告)日：2003-05-20
申请号：US09687119
申请日：2000-10-13
申请人： Michael P. Mack
发明人： Michael P. Mack
IPC分类号： H03K19094
CPC分类号： H03K5/1565 , H03K19/0175
摘要： A pulse width distortion correction logic level converter converts differential logic while preserving the pulse width of the original signal. The converter converts a differential input signal to a single-ended signal having a same pulse width as the differential input signal. The present invention receives and converts the differential input signal at a first converter and a second converter, wherein the first converter generates a first output signal, and the second converter generates a second output signal, respectively. Latching the first output signal of the first converter and the second output signal of the second converter produces a fill swing single-ended output signal having the same pulse width as the input differential signal. The first output signal sets the latching device with an edge of the first output signal of the first converter and resets the latching device with an edge of the second output signal of the second converter. The first and second output signals generate a full swing single-ended output signal width that is not sensitive to an absolute delay through the first and second converters.
摘要翻译：脉冲宽度失真校正逻辑电平转换器转换差分逻辑，同时保持原始信号的脉冲宽度。该转换器将差分输入信号转换成具有与差分输入信号相同的脉冲宽度的单端信号。本发明在第一转换器和第二转换器处接收和转换差分输入信号，其中第一转换器产生第一输出信号，第二转换器分别产生第二输出信号。锁存第一转换器的第一输出信号和第二转换器的第二输出信号产生具有与输入差分信号相同的脉冲宽度的填充摆幅单端输出信号。第一输出信号将锁存装置设置为具有第一转换器的第一输出信号的边沿，并且以第二转换器的第二输出信号的边沿复位锁存装置。第一和第二输出信号产生对通过第一和第二转换器的绝对延迟不敏感的全摆幅单端输出信号宽度。

5. 发明授权

US5844941A Parallel adaptive equalizer circuit 失效
标题翻译：并行自适应均衡电路
公开(公告)号：US5844941A
公开(公告)日：1998-12-01
申请号：US795450
申请日：1997-02-03
申请人： Michael P. Mack , Kenneth T. McBride
发明人： Michael P. Mack , Kenneth T. McBride
IPC分类号： H03H7/30
CPC分类号： H04L25/0268
摘要： An adaptive equalizer is configured to reconstruct electronic signals which are transmitted over signal cables, such as twisted pair cables. The equalizer satisfactorily reconstructs the signals over a broad range of cable lengths. Using the known degradation characteristics for a cable over a desired range of lengths, the adaptive equalizer includes multiple equalization paths, each of which are configured to reconstruct the input voltage signal optimized for a particular cable length. The degraded input signal is split according to a predetermined relationship into an appropriate two of the multiple equalization paths as controlled by a control logic circuit. Though each path is optimized to reconstruct the signal for a particular length of cable, the adaptive control adds a function of the actual cable length for more accurately reconstructing the signal. Each of the two active paths forms a partially reconstructed signal which is summed to form a composite reconstructed output signal. The control logic circuitry monitors the level of the output signal and adjusts a control signal appropriately in order to maintain the amplitude of the output signal in the required range. The control signal is used to determine the ratio of the input signal between the two active paths. A separate offset correction circuit also monitors the output signal for any offset and provides a correction signal to the input of the equalizer to compensate for the presence of any offset within the signal.
摘要翻译：自适应均衡器被配置为重建通过信号电缆（例如双绞线电缆）传输的电子信号。均衡器在宽范围的电缆长度上令人满意地重建信号。在所期望的长度范围内使用已知的电缆劣化特性，自适应均衡器包括多个均衡路径，每个均衡路径被配置为重建针对特定电缆长度优化的输入电压信号。劣化的输入信号根据预定的关系被分割成由控制逻辑电路控制的多个均衡路径中的适当的两个。虽然每个路径被优化以重建特定长度的电缆的信号，但是自适应控制增加了实际电缆长度的功能以更准确地重建信号。两个有效路径中的每一个形成部分重构的信号，其被相加以形成复合重建的输出信号。控制逻辑电路监视输出信号的电平并适当调整控制信号，以便将输出信号的幅度保持在所需范围内。控制信号用于确定两个有效路径之间的输入信号的比率。单独的偏移校正电路还监视输出信号以获得任何偏移，并且向均衡器的输入端提供校正信号，以补偿信号内任何偏移的存在。

6. 发明授权

US08427252B2 Oscillators with low power mode of operation 有权
标题翻译：低功耗运行模式的振荡器
公开(公告)号：US08427252B2
公开(公告)日：2013-04-23
申请号：US13149662
申请日：2011-05-31
申请人： Michael P. Mack
发明人： Michael P. Mack
IPC分类号： H03B5/30
CPC分类号： H03B5/30 , H03B2200/0082
摘要： A method and apparatus for configuring an oscillator circuit to selectively switch between a low power mode and a normal mode of operation. The oscillator circuit includes an oscillator core in parallel with a dynamically configurable gain circuit. The oscillator core is configured to generate a clock signal. One or more gain elements of the gain circuit can be selectively disabled to reduce the operating power level of the oscillator circuit during a low power mode.
摘要翻译：一种用于配置振荡器电路以选择性地在低功率模式和正常操作模式之间切换的方法和装置。振荡器电路包括与可动态配置的增益电路并联的振荡器磁芯。振荡器核心被配置为产生时钟信号。可以选择性地禁用增益电路的一个或多个增益元件，以在低功率模式期间降低振荡器电路的工作功率电平。

7. 发明申请

US20120306585A1 OSCILLATORS WITH LOW POWER MODE OF OPERATION 有权
标题翻译：具有低功耗操作模式的振荡器
公开(公告)号：US20120306585A1
公开(公告)日：2012-12-06
申请号：US13149662
申请日：2011-05-31
申请人： Michael P. MACK
发明人： Michael P. MACK
IPC分类号： H03L5/00
CPC分类号： H03B5/30 , H03B2200/0082
摘要： A method and apparatus for configuring an oscillator circuit to selectively switch between a low power mode and a normal mode of operation. The oscillator circuit includes an oscillator core in parallel with a dynamically configurable gain circuit. The oscillator core is configured to generate a clock signal. One or more gain elements of the gain circuit can be selectively disabled to reduce the operating power level of the oscillator circuit during a low power mode.
摘要翻译：一种用于配置振荡器电路以选择性地在低功率模式和正常操作模式之间切换的方法和装置。振荡器电路包括与可动态配置的增益电路并联的振荡器磁芯。振荡器核心被配置为产生时钟信号。可以选择性地禁用增益电路的一个或多个增益元件，以在低功率模式期间降低振荡器电路的工作功率电平。

8. 发明申请

US20120236447A1 INPUT-OUTPUT ESD PROTECTION 审中-公开
标题翻译：输入输出ESD保护
公开(公告)号：US20120236447A1
公开(公告)日：2012-09-20
申请号：US13179415
申请日：2011-07-08
申请人： Michael P. MACK , Sunetra Mendis
发明人： Michael P. MACK , Sunetra Mendis
IPC分类号： H02H9/00
CPC分类号： H02H9/046
摘要： A method and apparatus for protecting an input-out (I/O) circuit against electro-static discharge (ESD) events. An ESD circuit used to protect the I/O circuit against an ESD event is coupled to the I/O circuit. The ESD circuit includes a diode clamp circuit that couples an I/O pad to a power supply and a ground pad. The ESD circuit further includes an active clamp circuit that is configured to clamp the I/O pad without turning on the diode clamp circuit during the ESD event.
摘要翻译：一种用于保护输入输出（I / O）电路免受静电放电（ESD）事件的保护的方法和装置。用于保护I / O电路免受ESD事件的ESD电路耦合到I / O电路。 ESD电路包括将I / O焊盘耦合到电源和接地焊盘的二极管钳位电路。 ESD电路还包括有源钳位电路，其被配置为在ESD事件期间钳位I / O焊盘而不接通二极管钳位电路。

9. 发明授权

US5838723A Dual 10BASE-T and 100BASE-TX transmission termination circuit 失效
标题翻译：双10BASE-T和100BASE-TX传输终端电路
公开(公告)号：US5838723A
公开(公告)日：1998-11-17
申请号：US624189
申请日：1996-03-28
申请人： Michael P. Mack , Phillip R. Marzolf
发明人： Michael P. Mack , Phillip R. Marzolf
IPC分类号： H04B1/40
CPC分类号： H04L25/0266
摘要： A transmission termination circuit able to reduce transmission signal reflections and resultant data corruption such that a single network may selectively communicate data using either a voltage driven transceiver or a current driven transceiver. A 10BASE-T transceiver has differential voltage driven outputs. A first output is coupled to a first terminal of a primary winding of a transformer through a first resistor. A second output is coupled to a second terminal of the first primary winding through a second resistor. A 100BASE-TX transceiver has differential current driven outputs. A first output is coupled to a first terminal of a second primary winding of the transformer. A second output is coupled to a second terminal of the second primary winding. A resistive snubber comprising a resistor in series with a capacitor is coupled across the 100BASE-TX outputs. A twisted-pair network is coupled to a secondary winding of the transformer. When transmitting in 10BASE-T format, the resistive snubber suppresses voltage transients caused by a leakage inductance in series with the reflected 10BASE-T circuit. The snubber has a time constant which is large enough suppress transients during transmission by the 100BASE-TX circuit, but small enough to not interfere with transmission by the 10BASE-T transceiver. The snubber matches impedances of the 10BASE-T and the 100BASE-TX transceivers over a wide range of frequencies to prevent signal reflections.
摘要翻译：传输终端电路能够减少传输信号反射和结果数据损坏，使得单个网络可以使用电压驱动收发器或电流驱动的收发器选择性地传送数据。 10BASE-T收发器具有差分电压驱动输出。第一输出通过第一电阻耦合到变压器的初级绕组的第一端子。第二输出通过第二电阻耦合到第一初级绕组的第二端。 100BASE-TX收发器具有差分电流驱动输出。第一输出耦合到变压器的第二初级绕组的第一端子。第二输出耦合到第二初级绕组的第二端子。包括与电容器串联的电阻器的电阻缓冲器跨过100BASE-TX输出端耦合。双绞线网络耦合到变压器的次级绕组。当以10BASE-T格式发送时，电阻缓冲器抑制与反射的10BASE-T电路串联的漏电感引起的电压瞬变。缓冲器具有足够大的时间常数，可以在100BASE-TX电路传输期间抑制瞬变，但足够小，不会干扰10BASE-T收发器的传输。缓冲器在宽范围的频率上匹配10BASE-T和100BASE-TX收发器的阻抗，以防止信号反射。

10. 发明授权

US08565343B1 Transmit power control utilizing loopback error vector magnitude thresholds 失效
标题翻译：使用环回误差矢量幅度阈值发射功率控制
公开(公告)号：US08565343B1
公开(公告)日：2013-10-22
申请号：US13171236
申请日：2011-06-28
申请人： Paul J. Husted , Michael P. Mack , Soner Ozgur , Yann Ly-Gagnon
发明人： Paul J. Husted , Michael P. Mack , Soner Ozgur , Yann Ly-Gagnon
IPC分类号： H04L25/49 , H04B1/04
CPC分类号： H04B1/0475 , H03G3/3042 , H04L27/367
摘要： A device and method for adjusting transmit power in a wireless communication device. The wireless communication device comprises a transmitter having a power amplifier, wherein the amplifier may introduce distortion into the transmit signal. The method may periodically determine an error vector magnitude (EVM) level in the transmitter of the wireless communication device. The EVM level may be determined based on differences between an ideal transmit signal without amplification, and an actual transmit signal with amplification. The method may then adjust one or more transmit gain settings of at least one gain stage of the wireless device based on the measured EVM level in the transmitter. In one embodiment, as the EVM increases, indicating that more distortion is being introduced, the method may reduce the gain settings of the gain stage(s) to reduce this distortion. If the EVM decreases, the method may increase the gain of the gain stage(s).
摘要翻译：一种用于在无线通信设备中调整发射功率的设备和方法。无线通信设备包括具有功率放大器的发射机，其中放大器可以将失真引入到发射信号中。该方法可以周期性地确定无线通信设备的发射机中的误差向量幅度（EVM）。 EVM电平可以基于没有放大的理想发送信号和具有放大的实际发送信号之间的差异来确定。该方法然后可以基于发射机中测量的EVM电平来调整无线设备的至少一个增益级的一个或多个发射增益设置。在一个实施例中，随着EVM增加，指示正在引入更多的失真，该方法可以减小增益级的增益设置以减少该失真。如果EVM降低，则该方法可以增加增益级的增益。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式