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    • 3. 发明授权
    • Dual 10BASE-T and 100BASE-TX transmission termination circuit
    • 双10BASE-T和100BASE-TX传输终端电路
    • US5838723A
    • 1998-11-17
    • US624189
    • 1996-03-28
    • Michael P. MackPhillip R. Marzolf
    • Michael P. MackPhillip R. Marzolf
    • H04B1/40
    • H04L25/0266
    • A transmission termination circuit able to reduce transmission signal reflections and resultant data corruption such that a single network may selectively communicate data using either a voltage driven transceiver or a current driven transceiver. A 10BASE-T transceiver has differential voltage driven outputs. A first output is coupled to a first terminal of a primary winding of a transformer through a first resistor. A second output is coupled to a second terminal of the first primary winding through a second resistor. A 100BASE-TX transceiver has differential current driven outputs. A first output is coupled to a first terminal of a second primary winding of the transformer. A second output is coupled to a second terminal of the second primary winding. A resistive snubber comprising a resistor in series with a capacitor is coupled across the 100BASE-TX outputs. A twisted-pair network is coupled to a secondary winding of the transformer. When transmitting in 10BASE-T format, the resistive snubber suppresses voltage transients caused by a leakage inductance in series with the reflected 10BASE-T circuit. The snubber has a time constant which is large enough suppress transients during transmission by the 100BASE-TX circuit, but small enough to not interfere with transmission by the 10BASE-T transceiver. The snubber matches impedances of the 10BASE-T and the 100BASE-TX transceivers over a wide range of frequencies to prevent signal reflections.
    • 传输终端电路能够减少传输信号反射和结果数据损坏,使得单个网络可以使用电压驱动收发器或电流驱动的收发器选择性地传送数据。 10BASE-T收发器具有差分电压驱动输出。 第一输出通过第一电阻耦合到变压器的初级绕组的第一端子。 第二输出通过第二电阻耦合到第一初级绕组的第二端。 100BASE-TX收发器具有差分电流驱动输出。 第一输出耦合到变压器的第二初级绕组的第一端子。 第二输出耦合到第二初级绕组的第二端子。 包括与电容器串联的电阻器的电阻缓冲器跨过100BASE-TX输出端耦合。 双绞线网络耦合到变压器的次级绕组。 当以10BASE-T格式发送时,电阻缓冲器抑制与反射的10BASE-T电路串联的漏电感引起的电压瞬变。 缓冲器具有足够大的时间常数,可以在100BASE-TX电路传输期间抑制瞬变,但足够小,不会干扰10BASE-T收发器的传输。 缓冲器在宽范围的频率上匹配10BASE-T和100BASE-TX收发器的阻抗,以防止信号反射。
    • 4. 发明授权
    • Transmit power control utilizing loopback error vector magnitude thresholds
    • 使用环回误差矢量幅度阈值发射功率控制
    • US08565343B1
    • 2013-10-22
    • US13171236
    • 2011-06-28
    • Paul J. HustedMichael P. MackSoner OzgurYann Ly-Gagnon
    • Paul J. HustedMichael P. MackSoner OzgurYann Ly-Gagnon
    • H04L25/49H04B1/04
    • H04B1/0475H03G3/3042H04L27/367
    • A device and method for adjusting transmit power in a wireless communication device. The wireless communication device comprises a transmitter having a power amplifier, wherein the amplifier may introduce distortion into the transmit signal. The method may periodically determine an error vector magnitude (EVM) level in the transmitter of the wireless communication device. The EVM level may be determined based on differences between an ideal transmit signal without amplification, and an actual transmit signal with amplification. The method may then adjust one or more transmit gain settings of at least one gain stage of the wireless device based on the measured EVM level in the transmitter. In one embodiment, as the EVM increases, indicating that more distortion is being introduced, the method may reduce the gain settings of the gain stage(s) to reduce this distortion. If the EVM decreases, the method may increase the gain of the gain stage(s).
    • 一种用于在无线通信设备中调整发射功率的设备和方法。 无线通信设备包括具有功率放大器的发射机,其中放大器可以将失真引入到发射信号中。 该方法可以周期性地确定无线通信设备的发射机中的误差向量幅度(EVM)。 EVM电平可以基于没有放大的理想发送信号和具有放大的实际发送信号之间的差异来确定。 该方法然后可以基于发射机中测量的EVM电平来调整无线设备的至少一个增益级的一个或多个发射增益设置。 在一个实施例中,随着EVM增加,指示正在引入更多的失真,该方法可以减小增益级的增益设置以减少该失真。 如果EVM降低,则该方法可以增加增益级的增益。
    • 6. 发明授权
    • Current mode pulse frequency modulation switching regulator
    • 电流模式脉冲频率调制开关调节器
    • US07728567B1
    • 2010-06-01
    • US11627907
    • 2007-01-26
    • Michael P. Mack
    • Michael P. Mack
    • G05F1/59G05F1/565
    • H02M3/156
    • A method of providing current mode pulse frequency modulation (PFM) for a switching regulator can include resetting a driver input for a fixed duration when a first current in the driver reaches a first value set by an error amplifier output. The first current can be associated with PMOS switching transistors in the driver. The method can also include setting the driver input signal for the same fixed duration when a second current in the driver reaches a second value. This second current can be associated with NMOS switching transistors in the driver. In one embodiment, the driver can be tristated to ignore both the resetting and the setting. Using this method, perturbations of the inductor current can be substantially corrected and have limited impact on the current waveform beyond the cycle in which they occur.
    • 为开关稳压器提供电流模式脉冲频率调制(PFM)的方法可以包括当驱动器中的第一电流达到由误差放大器输出设置的第一值时将固定持续时间的驱动器输入复位。 第一电流可以与驱动器中的PMOS开关晶体管相关联。 该方法还可以包括当驱动器中的第二电流达到第二值时将驱动器输入信号设置为相同的固定持续时间。 该第二电流可以与驱动器中的NMOS开关晶体管相关联。 在一个实施例中,驱动器可以被三态化以忽略复位和设置。 使用这种方法,可以基本上校正电感器电流的扰动,并且对它们发生的周期以外的电流波形具有有限的影响。
    • 7. 发明授权
    • Standalone testing of a receiver
    • 接收机的独立测试
    • US08270459B1
    • 2012-09-18
    • US12562997
    • 2009-09-18
    • Michael P. Mack
    • Michael P. Mack
    • H04B3/46
    • H04B1/1027
    • A system and/or integrated circuit are disclosed that may include a receiver, a harmonic signal generator and a signal injector. The receiver may use at least one signal line to create a baseband signal to further create a quality measure used to improve the quality of reception and based upon the receiver response to the baseband signal. The harmonic signal generator may generate harmonic signal(s) including at least one harmonic component within the receiver's reception range. The signal injector may receive the harmonic signal and a control signal to generate the signal line from the harmonic signal in response to the control signal. The receiver may implement WLAN, Bluetooth, GPS, AM, mobile TV, FM, and/or Television. A transmitter compatible with the receiver may or may not be included, and may be configured to couple at least one of its outputs to the receiver to create a second quality measure.
    • 公开了可包括接收器,谐波信号发生器和信号注入器的系统和/或集成电路。 接收机可以使用至少一条信号线来创建基带信号,以进一步创建用于提高接收质量的质量测量,并且基于接收机对基带信号的响应。 谐波信号发生器可以产生包括接收机接收范围内的至少一个谐波分量的谐波信号。 信号注射器可以接收谐波信号和控制信号,以响应于控制信号从谐波信号产生信号线。 接收机可以实现WLAN,蓝牙,GPS,AM,移动电视,FM和/或电视。 与接收机兼容的发射机可以被包括或可以不被包括,并且可以被配置为将其输出中的至少一个耦合到接收机以创建第二质量度量。
    • 9. 发明授权
    • Pulse width distortion correction logic level converter
    • 脉宽失真校正逻辑电平转换器
    • US06175248B1
    • 2001-01-16
    • US09314426
    • 1999-05-18
    • Michael P. Mack
    • Michael P. Mack
    • H03K190175
    • H03K5/1565H03K19/0175
    • A pulse width distortion correction logic level converter converts differential logic while preserving the pulse width of the original signal. The converter converts a differential input signal to a single-ended signal having a same pulse width as the differential input signal. The present invention receives and converts the differential input signal at a first converter and a second converter, wherein the first converter generates a first output signal, and the second converter generates a second output signal, respectively. Latching the first output signal of the first converter and the second output signal of the second converter produces a full swing single-ended output signal having the same pulse width as the input differential signal. The first output signal sets the latching device with an edge of the first output signal of the first converter and resets the latching device with an edge of the second output signal of the second converter. The first and second output signals generate a full swing single-ended output signal width that is not sensitive to an absolute delay through the first and second converters.
    • 脉冲宽度失真校正逻辑电平转换器转换差分逻辑,同时保持原始信号的脉冲宽度。 该转换器将差分输入信号转换成具有与差分输入信号相同的脉冲宽度的单端信号。 本发明在第一转换器和第二转换器处接收和转换差分输入信号,其中第一转换器产生第一输出信号,第二转换器分别产生第二输出信号。 锁存第一转换器的第一输出信号和第二转换器的第二输出信号产生具有与输入差分信号相同的脉冲宽度的全摆幅单端输出信号。 第一输出信号将锁存装置设置为具有第一转换器的第一输出信号的边沿,并且以第二转换器的第二输出信号的边沿复位锁存装置。 第一和第二输出信号产生对通过第一和第二转换器的绝对延迟不敏感的全摆幅单端输出信号宽度。