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1. 发明授权

US08503466B2 Network on chip input/output nodes 有权
标题翻译：网络片上输入/输出节点
公开(公告)号：US08503466B2
公开(公告)日：2013-08-06
申请号：US12870382
申请日：2010-08-27
申请人： Michel Harrand
发明人： Michel Harrand
IPC分类号： H04L12/28 , H04L12/56
CPC分类号： G06F13/4022 , G06F15/7825
摘要： The present invention relates to a torus network comprising a matrix of infrastructure routers, each of which is connected to two other routers belonging to the same row and to two other routers belonging to the same column; and input/output routers, each of which is connected by two internal inputs to two other routers belonging either to the same row, or to the same column, and comprising an external input for supplying the network with data. Each input/output router is devoid of queues for its internal inputs and comprises queues assigned to its external input managed by an arbiter which is configured to also manage the queues of an infrastructure router connected to the input/output router.
摘要翻译：环形网络技术领域本发明涉及一种环面网络，其包括基础设施路由器的矩阵，每个路由器连接到属于同一行的另外两个路由器和属于同一列的另外两个路由器; 以及输入/输出路由器，每个路由器通过两个内部输入连接到属于同一行或同一列的另外两个路由器，并且包括用于向网络提供数据的外部输入。每个输入/输出路由器缺少其内部输入的队列，并且包括分配给由仲裁器管理的外部输入的队列，该仲裁器被配置为还管理连接到输入/输出路由器的基础设施路由器的队列。

2. 发明申请

US20130054811A1 EXTENSIBLE NETWORK-ON-CHIP 有权
标题翻译：可扩展的网络芯片
公开(公告)号：US20130054811A1
公开(公告)日：2013-02-28
申请号：US13572213
申请日：2012-08-10
申请人： Michel HARRAND
发明人： Michel HARRAND
IPC分类号： G06F15/173
CPC分类号： G06F15/7825
摘要： An integrated circuit comprises compute nodes arranged in an array; a torus topology network-on-chip interconnecting the compute nodes; and a network extension unit at each end of each row or column of the array, inserted in a network link between two compute nodes. The extension unit has a normal mode establishing the continuity of the network link between the two corresponding compute nodes, and an extension mode dividing the network link in two independent segments that are accessible from outside the integrated circuit.
摘要翻译：集成电路包括排列成阵列的计算节点; 圆环拓扑网络片上互连计算节点; 以及插入在两个计算节点之间的网络链路中的阵列的每一行或每列的每一端的网络扩展单元。扩展单元具有建立两个对应的计算节点之间的网络链路的连续性的正常模式，以及将网络链路划分为可从集成电路外部访问的两个独立的段中的扩展模式。

3. 发明授权

US5349547A Bidimensional FIR filter 失效
标题翻译：二维FIR滤波器
公开(公告)号：US5349547A
公开(公告)日：1994-09-20
申请号：US111624
申请日：1993-08-25
申请人： Michel Harrand
发明人： Michel Harrand
IPC分类号： H04N5/14 , G06T5/20 , H03H17/02 , H04N5/205 , H04N7/26 , G06F15/31
CPC分类号： H04N19/80 , H03H17/0202
摘要： A bidimensional Finite Impulse Response (FIR) filter of rank 2p+1 for processing data associates a "vertical" filter and a "horizontal" filter. Each filter comprises 2p+1 cells and circuitry for vertically scanning the data according to stripes having a height of p data; circuitry for simultaneously providing on a first line a datum of a stripe, on a second line a datum of the former stride shifted by p data, and on a third line, a datum of the still former stripe again shifted by p data; and circuitry for, at each clock time, connecting each cell input to one of the three lines.
摘要翻译：用于处理数据的2p + 1的二维有限脉冲响应（FIR）滤波器将“垂直”滤波器和“水平”滤波器相关联。每个滤波器包括2p + 1个单元和用于根据具有p数据高度的条带垂直扫描数据的电路; 电路，用于同时在第一行上提供条纹的数据，在第二行上，前移一个p数据的第一行的数据，以及在第三行上再次移位p数据的第一行的数据; 以及用于在每个时钟时间将每个单元输入连接到三条线之一的电路。

4. 发明授权

US09064092B2 Extensible network-on-chip 有权
标题翻译：可扩展的片上网络
公开(公告)号：US09064092B2
公开(公告)日：2015-06-23
申请号：US13572213
申请日：2012-08-10
申请人： Michel Harrand
发明人： Michel Harrand
IPC分类号： G06F13/36 , G06F15/78
CPC分类号： G06F15/7825
摘要： An integrated circuit comprises compute nodes arranged in an array; a torus topology network-on-chip interconnecting the compute nodes; and a network extension unit at each end of each row or column of the array, inserted in a network link between two compute nodes. The extension unit has a normal mode establishing the continuity of the network link between the two corresponding compute nodes, and an extension mode dividing the network link in two independent segments that are accessible from outside the integrated circuit.
摘要翻译：集成电路包括排列成阵列的计算节点; 圆环拓扑网络片上互连计算节点; 以及插入在两个计算节点之间的网络链路中的阵列的每行或每列的每一端的网络扩展单元。扩展单元具有建立两个对应的计算节点之间的网络链路的连续性的正常模式，以及将网络链路划分为可从集成电路外部访问的两个独立的段中的扩展模式。

5. 发明申请

US20110058569A1 NETWORK ON CHIP INPUT/OUTPUT NODES 有权
标题翻译：芯片输入/输出节点上的网络
公开(公告)号：US20110058569A1
公开(公告)日：2011-03-10
申请号：US12870382
申请日：2010-08-27
申请人： Michel Harrand
发明人： Michel Harrand
IPC分类号： H04L12/28
CPC分类号： G06F13/4022 , G06F15/7825
摘要： The present invention relates to a torus network comprising a matrix of infrastructure routers, each of which is connected to two other routers belonging to the same row and to two other routers belonging to the same column; and input/output routers, each of which is connected by two internal inputs to two other routers belonging either to the same row, or to the same column, and comprising an external input for supplying the network with data. Each input/output router is devoid of queues for its internal inputs and comprises queues assigned to its external input managed by an arbiter which is configured to also manage the queues of an infrastructure router connected to the input/output router.
摘要翻译：环形网络技术领域本发明涉及一种环面网络，其包括基础设施路由器的矩阵，每个路由器连接到属于同一行的另外两个路由器和属于同一列的另外两个路由器; 以及输入/输出路由器，每个路由器通过两个内部输入连接到属于同一行或同一列的另外两个路由器，并且包括用于向网络提供数据的外部输入。每个输入/输出路由器缺少其内部输入的队列，并且包括分配给由仲裁器管理的外部输入的队列，该仲裁器被配置为还管理连接到输入/输出路由器的基础设施路由器的队列。

6. 发明申请

US20100306480A1 Shared Memory 有权
标题翻译：共享内存
公开(公告)号：US20100306480A1
公开(公告)日：2010-12-02
申请号：US12675382
申请日：2008-08-14
申请人： Michel Harrand
发明人： Michel Harrand
IPC分类号： G06F12/00
CPC分类号： G11C7/1075 , G11C5/02 , G11C7/1012 , G11C7/1048 , G11C2207/108
摘要： The present invention relates to a shared memory (20) made on a chip based on semiconductors. The shared memory comprises: an integer number m, greater than one, of data buses (24); m address and control buses (200); m input/output interfaces (PI/PO, PO′), each input/output interface (PI/PO, PO′) being connected to one of the m data buses (24) and to one of the m address and control buses (200); an integer number p, greater than one, of memory banks (21, 22, 23), each memory bank (21, 22, 23) comprising: a memory (210, 220, 230), comprising a data input/output (I/O) and an address and control input (I) controlled by each of the address and control buses (200); a block of m switches (214, 224, 234), each of the m switches (214, 224, 234) being connected on the one hand to a memory data bus (213, 223, 233), said memory data bus (213, 223, 233) being connected to the data input/output (I/O) of the memory (210, 220, 230), and on the other hand to one of the m data buses (24). The shared memory (20) finds notably its application in the field of microelectronics.
摘要翻译：本发明涉及基于半导体的芯片上制作的共享存储器（20）。共享存储器包括：数据总线（24）中的大于1的整数m; m地址和控制总线（200）; m个输入/输出接口（PI / PO，PO'），每个输入/输出接口（PI / PO，PO'）连接到m个数据总线（24）之一和m个地址和控制总线 200）; 每个存储体（21,22,23）的整数p大于1，每个存储体（21,22,23）包括：存储器（210,220,230），包括数据输入/输出（I / O）和由每个地址和控制总线（200）控制的地址和控制输入（I）; 一组m个开关（214,224,234），一个m开关（214,224,234）中的每一个一方面连接到存储器数据总线（213,223,233），所述存储器数据总线（213 ，223,233）连接到存储器（210,220,230）的数据输入/输出（I / O），另一方面连接到m个数据总线（24）中的一个。共享存储器（20）显着地发现其在微电子领域的应用。

7. 发明授权

US06914908B1 Multitask processing system 失效
标题翻译：多任务处理系统
公开(公告)号：US06914908B1
公开(公告)日：2005-07-05
申请号：US09420129
申请日：1999-10-19
申请人： Michel Harrand , Claire Henry
发明人： Michel Henry
IPC分类号： G06F15/16 , G06F13/12 , G06F13/16 , G06F15/177 , G06T1/20 , H04N7/26 , H04J3/02
CPC分类号： G06F13/1605 , G06F13/126
摘要： The invention relates to a multitask processing system including a data bus and a command bus. Each one of a plurality of operators is provided to perform a processing determined by an instruction and is likely to issue a command request in order to receive an instruction from the command bus and to issue a transfer request on response to an acknowledgment of the command request, in order to receive or provide data being processed, through the data bus. A memory controller arbitrates the transfer requests and manages the data transfers on the data bus between the operators and a memory. A sequencer arbitrates the command requests, determines instructions to provide the operators with, and manages the instruction transfer through the command bus.
摘要翻译：本发明涉及包括数据总线和命令总线的多任务处理系统。提供多个运算符中的每一个以执行由指令确定的处理，并且可能发出命令请求以便从命令总线接收指令并且响应于命令请求的确认发出转移请求，以便通过数据总线接收或提供正在处理的数据。存储器控制器仲裁传送请求并管理数据总线上的操作员和存储器之间的数据传输。定序器仲裁命令请求，确定提供操作者的指令，并通过命令总线管理指令传输。

8. 发明授权

US06631441B2 DRAM read and write circuit 有权
标题翻译： DRAM读写电路
公开(公告)号：US06631441B2
公开(公告)日：2003-10-07
申请号：US09730498
申请日：2000-12-04
申请人： Michel Harrand , David Boise
发明人： Michel Harrand , David Boise
IPC分类号： G06F1200
CPC分类号： G11C7/106 , G06F12/0893 , G11C7/1051 , G11C7/1078 , G11C2207/2245
摘要： A dynamic random access memory circuit including a memory plane formed of an array of memory cells, as well as at least two cache registers enabling access to the memory plane and adapted to ensure the reading from and the writing into the memory. The circuit also includes several registers indicating the location of new words to be written, each of the indicative registers being coupled with one of the cache registers adapted to ensuring the writing into the memory.
摘要翻译：包括由存储器单元阵列形成的存储器平面的动态随机存取存储器电路，以及至少两个高速缓存寄存器，其能够访问存储器平面并适于确保从存储器的读取和写入。电路还包括指示要写入的新字的位置的几个寄存器，每个指示寄存器与适于确保写入存储器的高速缓存寄存器中的一个耦合。

9. 发明授权

US5987488A Matrix processor 失效
标题翻译：矩阵处理器
公开(公告)号：US5987488A
公开(公告)日：1999-11-16
申请号：US994953
申请日：1997-12-19
申请人： Michel Harrand , Jose Sanches
发明人： Michel Harrand , Jose Sanches
IPC分类号： G06F17/16 , G06F7/32
CPC分类号： G06F17/16
摘要： A matrix computation processor comprises a control unit and a data memory, and a plurality of computation units. The plurality of computation units are controlled by the control unit by means of a control bus comprising: a first group of wires connected to the plurality of computation units conveying a common instruction to the plurality of computation units; and a plurality of second groups of at least one wire, each being connected respectively to one of the plurality of computation units, conveying an instruction complement specific to each computation unit of the plurality of computation units.
摘要翻译：矩阵计算处理器包括控制单元和数据存储器以及多个计算单元。所述多个计算单元由所述控制单元通过控制总线控制，所述控制总线包括：连接到所述多个计算单元的第一组线，其向所述多个计算单元传送公共指令; 以及多个第二组至少一根线，各自分别连接到所述多个计算单元中的一个，传送对所述多个计算单元中的每个计算单元特有的指令补码。

10. 发明授权

US08656116B2 Integrating plurality of processors with shared memory on the same circuit based semiconductor 有权
标题翻译：在相同的基于电路的半导体上将多个处理器与共享存储器集成
公开(公告)号：US08656116B2
公开(公告)日：2014-02-18
申请号：US12675382
申请日：2008-08-14
申请人： Michel Harrand
发明人： Michel Harrand
IPC分类号： G11C7/00 , G11C8/00 , G06F12/00
CPC分类号： G11C7/1075 , G11C5/02 , G11C7/1012 , G11C7/1048 , G11C2207/108
摘要： A shared memory made on a chip based on semiconductors comprising: an integer number m, greater than one, of data buses; m address and control buses; m input/output interfaces, each input/output interface being connected to one of the m data buses and to one of the m address and control buses; an integer number p, greater than one, of memory banks, each memory bank comprising: a memory, comprising a data input/output and an address and control input controlled by each of the address and control buses; a block of m switches, each of the m switches being connected on the one hand to a memory data bus, said memory data bus being connected to the data input/output of the memory, and on the other hand to one of the m data buses.
摘要翻译：一种基于半导体的芯片制成的共享存储器，包括：数据总线m的大于1的整数; m地址和控制总线; m个输入/输出接口，每个输入/输出接口连接到m个数据总线之一和m个地址和控制总线中的一个; 每个存储器组包括：存储器，包括数据输入/输出以及由每个地址和控制总线控制的地址和控制输入; 一组m个开关，一个m个开关一方面连接到存储器数据总线，所述存储器数据总线连接到存储器的数据输入/输出，另一方面连接到m个数据之一巴士

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