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1. 发明授权

US09183414B2 Memory controller and memory device including the memory controller 有权
标题翻译：内存控制器和内存设备包括内存控制器
公开(公告)号：US09183414B2
公开(公告)日：2015-11-10
申请号：US12391521
申请日：2009-02-24
申请人： Min-soo Lim
发明人： Min-soo Lim
IPC分类号： G06F11/30 , G06F21/78 , G06F12/14 , G06F21/57
CPC分类号： G06F21/78 , G06F12/1408 , G06F21/575
摘要： A memory controller includes a security key and parameter storage unit and a security engine. The security key and parameter storage unit stores at least one security key and at least one parameter that are used during encryption or decryption. The security engine receives encrypted data stored in an external boot memory, decrypts the received encrypted data by using the security key and the parameter, and outputs the decrypted data to a central processing unit (CPU), in a security operation mode.
摘要翻译：存储器控制器包括安全密钥和参数存储单元以及安全引擎。安全密钥和参数存储单元存储在加密或解密期间使用的至少一个安全密钥和至少一个参数。安全引擎接收存储在外部引导存储器中的加密数据，通过使用安全密钥和参数对接收到的加密数据进行解密，并以安全操作模式将解密的数据输出到中央处理单元（CPU）。

2. 发明授权

US08650388B2 Multi-processor systems and booting methods thereof 有权
标题翻译：多处理器系统及其引导方法
公开(公告)号：US08650388B2
公开(公告)日：2014-02-11
申请号：US13064200
申请日：2011-03-10
申请人： Jong-Ho Roh , Min-Soo Lim
发明人： Jong-Ho Roh , Min-Soo Lim
IPC分类号： G06F9/00
CPC分类号： G06F9/4405 , G06F15/177
摘要： Multi-processor systems and methods thereof are provided. In an example, the multi-processor system may include a boot memory including a plurality of boot codes, each of the plurality of boot codes configured to facilitate an initialization process at one of a plurality of intellectual property (IP) blocks, each of the plurality of IP blocks having shared access to the boot memory. In another example, the multi-processor system may receive, from a first processor, a request to provide one of a plurality of boot codes from a boot memory, the received request sent in response to a system initializing signal, may read the requested boot code from the boot memory and may transfer, from a second processor, the read boot code to the first processor.
摘要翻译：提供了多处理器系统及其方法。在一个示例中，多处理器系统可以包括引导存储器，其包括多个引导代码，所述多个引导代码中的每一个被配置为便于在多个知识产权（IP）块之一处的初始化处理，多个IP块具有对引导存储器的共享访问。在另一示例中，多处理器系统可以从第一处理器接收从引导存储器提供多个引导代码中的一个的请求，响应于系统初始化信号发送的接收到的请求可以读取所请求的引导来自引导存储器的代码，并且可以从第二处理器将读取引导代码传送到第一处理器。

3. 发明申请

US20050256986A1 Slave devices and methods for operating the same 有权
标题翻译：从设备及其操作方法
公开(公告)号：US20050256986A1
公开(公告)日：2005-11-17
申请号：US11124271
申请日：2005-05-09
申请人： Kyoung-Park Kim , Sung-Ho Ryu , Min-Soo Lim
发明人： Kyoung-Park Kim , Sung-Ho Ryu , Min-Soo Lim
IPC分类号： G06F13/38 , G06F1/32 , G06F13/00
CPC分类号： G06F1/3203
摘要： A slave device may be configured to receive at least one bus interface clock and bus interface signals from a bus coupled to the at least one bus interface unit. The slave device may also be configured to operate independently of at least one main function clock
摘要翻译：从设备可以被配置为从耦合到至少一个总线接口单元的总线接收至少一个总线接口时钟和总线接口信号。从设备还可以被配置为独立于至少一个主功能时钟来操作

4. 发明申请

US20090228711A1 Processor apparatus having a security function 有权
标题翻译：具有安全功能的处理器装置
公开(公告)号：US20090228711A1
公开(公告)日：2009-09-10
申请号：US12381114
申请日：2009-03-06
申请人： Min-soo Lim
发明人： Min-soo Lim
IPC分类号： G06F21/00
CPC分类号： G06F21/575 , G06F21/71 , G06F2221/2113 , G06F2221/2149
摘要： A processor apparatus capable of operating in a security mode includes a hash value storage unit and a security control unit including a plurality of access authentication hash values. The hash value storage value stores a plurality of hash values including a user authentication hash value and a plurality of access authentication hash values. The security control unit checks whether a boot code transmitted from a boot memory and a hash value from among the hash values, which corresponds to the boot code, are identical, and determines whether a boot operation and a debugging operation of the processor apparatus are allowed and whether an external user is allowed to have access to a predetermined intellectual property (IP) block. The processor apparatus can ensure debugging, security for the processor itself or security for a predetermined block included in the processor apparatus.
摘要翻译：能够以安全模式操作的处理器装置包括散列值存储单元和包括多个访问认证散列值的安全控制单元。散列值存储值存储包括用户认证散列值和多个访问认证散列值的多个散列值。安全控制单元检查从引导存储器发送的引导代码和与启动代码相对应的散列值中的哈希值是否相同，并且确定是否允许处理器装置的引导操作和调试操作以及是否允许外部用户访问预定的知识产权（IP）块。处理器装置可以确保处理器本身的调试，安全性或包括在处理器装置中的预定块的安全性。

5. 发明授权

US07930530B2 Multi-processor system that reads one of a plurality of boot codes via memory interface buffer in response to requesting processor 有权
标题翻译：多处理器系统，响应于请求处理器，经由存储器接口缓冲器读取多个引导代码之一
公开(公告)号：US07930530B2
公开(公告)日：2011-04-19
申请号：US11704202
申请日：2007-02-09
申请人： Jong-Ho Roh , Min-Soo Lim
发明人： Jong-Ho Roh , Min-Soo Lim
IPC分类号： G06F9/00
CPC分类号： G06F9/4405 , G06F15/177
摘要： Multi-processor systems and methods thereof are provided. In an example, the multi-processor system may include a boot memory including a plurality of boot codes, each of the plurality of boot codes configured to facilitate an initialization process at one of a plurality of intellectual property (IP) blocks, each of the plurality of IP blocks having shared access to the boot memory. In another example, the multi-processor system may receive, from a first processor, a request to provide one of a plurality of boot codes from a boot memory, the received request sent in response to a system initializing signal, may read the requested boot code from the boot memory and may transfer, from a second processor, the read boot code to the first processor.
摘要翻译：提供了多处理器系统及其方法。在一个示例中，多处理器系统可以包括引导存储器，其包括多个引导代码，所述多个引导代码中的每一个被配置为便于在多个知识产权（IP）块之一处的初始化处理，多个IP块具有对引导存储器的共享访问。在另一示例中，多处理器系统可以从第一处理器接收从引导存储器提供多个引导代码中的一个的请求，响应于系统初始化信号发送的接收到的请求可以读取所请求的引导来自引导存储器的代码，并且可以从第二处理器将读取引导代码传送到第一处理器。

6. 发明申请

US20090262940A1 MEMORY CONTROLLER AND MEMORY DEVICE INCLUDING THE MEMORY CONTROLLER 有权
标题翻译：内存控制器和包含存储器控制器的存储器件
公开(公告)号：US20090262940A1
公开(公告)日：2009-10-22
申请号：US12391521
申请日：2009-02-24
申请人： Min-soo Lim
发明人： Min-soo Lim
IPC分类号： G06F12/14 , H04L9/00
CPC分类号： G06F21/78 , G06F12/1408 , G06F21/575
摘要： A memory controller includes a security key and parameter storage unit and a security engine. The security key and parameter storage unit stores at least one security key and at least one parameter that are used during encryption or decryption. The security engine receives encrypted data stored in an external boot memory, decrypts the received encrypted data by using the security key and the parameter, and outputs the decrypted data to a central processing unit (CPU), in a security operation mode.
摘要翻译：存储器控制器包括安全密钥和参数存储单元以及安全引擎。安全密钥和参数存储单元存储在加密或解密期间使用的至少一个安全密钥和至少一个参数。安全引擎接收存储在外部引导存储器中的加密数据，通过使用安全密钥和参数对接收到的加密数据进行解密，并以安全操作模式将解密的数据输出到中央处理单元（CPU）。

7. 发明授权

US07327617B2 Memory address generating circuit and memory controller using the same 有权
标题翻译：存储器地址产生电路和使用其的存储器控制器
公开(公告)号：US07327617B2
公开(公告)日：2008-02-05
申请号：US11349860
申请日：2006-02-08
申请人： Min-Soo Lim
发明人： Min-Soo Lim
IPC分类号： G11C7/00
CPC分类号： G11C11/408 , G06F12/0607 , G11C11/406 , G11C11/40622 , Y02D10/13
摘要： Provided are a memory address generating circuit through which a user can freely select a method of generating an address of a memory according to an environment in which the memory is applied, and a memory controller including the memory address generating circuit. The memory address generating circuit includes a CAS address selecting circuit and an RAS address selecting circuit. The CAS address selecting circuit outputs a CAS address signal using N (N is an integer) column address signals and M (M is an integer) CAS address select signals. The RAS address selecting circuit which outputs an RAS address signal using K (K is an integer) row address signals and L (L is an integer) RAS address select signals. The memory address generating circuit controls the CAS address select signals and the RAS address select signals to perform a memory mapping most suitable for a system in which the memory is used.
摘要翻译：提供了一种存储器地址产生电路，用户可以根据应用存储器的环境自由选择产生存储器的地址的方法，以及存储器控制器，其包括存储器地址生成电路。存储器地址产生电路包括一个CAS地址选择电路和一个RAS地址选择电路。 CAS地址选择电路使用N（N为整数）列地址信号和M（M为整数）CAS地址选择信号输出CAS地址信号。使用K（K是整数）行地址信号和L（L是整数）RAS地址选择信号来输出RAS地址信号的RAS地址选择电路。存储器地址产生电路控制CAS地址选择信号和RAS地址选择信号以执行最适合于使用存储器的系统的存储器映射。

8. 发明申请

US20070192529A1 Multi-processor systems and methods thereof 有权
标题翻译：多处理器系统及其方法
公开(公告)号：US20070192529A1
公开(公告)日：2007-08-16
申请号：US11704202
申请日：2007-02-09
申请人： Jong-Ho Roh , Min-Soo Lim
发明人： Jong-Ho Roh , Min-Soo Lim
IPC分类号： G06F12/00
CPC分类号： G06F9/4405 , G06F15/177
摘要： Multi-processor systems and methods thereof are provided. In an example, the multi-processor system may include a boot memory including a plurality of boot codes, each of the plurality of boot codes configured to facilitate an initialization process at one of a plurality of intellectual property (IP) blocks, each of the plurality of IP blocks having shared access to the boot memory. In another example, the multi-processor system may receive, from a first processor, a request to provide one of a plurality of boot codes from a boot memory, the received request sent in response to a system initializing signal, may read the requested boot code from the boot memory and may transfer, from a second processor, the read boot code to the first processor.
摘要翻译：提供了多处理器系统及其方法。在一个示例中，多处理器系统可以包括引导存储器，其包括多个引导代码，所述多个引导代码中的每一个被配置为便于在多个知识产权（IP）块之一处的初始化处理，多个IP块具有对引导存储器的共享访问。在另一示例中，多处理器系统可以从第一处理器接收从引导存储器提供多个引导代码中的一个的请求，响应于系统初始化信号发送的接收到的请求可以读取所请求的引导来自引导存储器的代码，并且可以从第二处理器将读取引导代码传送到第一处理器。

9. 发明申请

US20060181940A1 Memory address generating circuit and memory controller using the same 有权
标题翻译：存储器地址产生电路和使用其的存储器控制器
公开(公告)号：US20060181940A1
公开(公告)日：2006-08-17
申请号：US11349860
申请日：2006-02-08
申请人： Min-Soo Lim
发明人： Min-Soo Lim
IPC分类号： G11C7/00
CPC分类号： G11C11/408 , G06F12/0607 , G11C11/406 , G11C11/40622 , Y02D10/13
摘要： Provided are a memory address generating circuit through which a user can freely select a method of generating an address of a memory according to an environment in which the memory is applied, and a memory controller including the memory address generating circuit. The memory address generating circuit includes a CAS address selecting circuit and an RAS address selecting circuit. The CAS address selecting circuit outputs a CAS address signal using N (N is an integer) column address signals and M (M is an integer) CAS address select signals. The RAS address selecting circuit which outputs an RAS address signal using K (K is an integer) row address signals and L (L is an integer) RAS address select signals. The memory address generating circuit controls the CAS address select signals and the RAS address select signals to perform a memory mapping most suitable for a system in which the memory is used.
摘要翻译：提供了一种存储器地址产生电路，用户可以根据应用存储器的环境自由选择产生存储器的地址的方法，以及存储器控制器，其包括存储器地址生成电路。存储器地址产生电路包括一个CAS地址选择电路和一个RAS地址选择电路。 CAS地址选择电路使用N（N为整数）列地址信号和M（M为整数）CAS地址选择信号输出CAS地址信号。使用K（K是整数）行地址信号和L（L是整数）RAS地址选择信号来输出RAS地址信号的RAS地址选择电路。存储器地址产生电路控制CAS地址选择信号和RAS地址选择信号以执行最适合于使用存储器的系统的存储器映射。

10. 发明授权

US08489888B2 Processor apparatus having a security function 有权
公开(公告)号：US08489888B2
公开(公告)日：2013-07-16
申请号：US12381114
申请日：2009-03-06
申请人： Min-soo Lim
发明人： Min-soo Lim
IPC分类号： G06F21/00
CPC分类号： G06F21/575 , G06F21/71 , G06F2221/2113 , G06F2221/2149
摘要： A processor apparatus capable of operating in a security mode includes a hash value storage unit and a security control unit including a plurality of access authentication hash values. The hash value storage value stores a plurality of hash values including a user authentication hash value and a plurality of access authentication hash values. The security control unit checks whether a boot code transmitted from a boot memory and a hash value from among the hash values, which corresponds to the boot code, are identical, and determines whether a boot operation and a debugging operation of the processor apparatus are allowed and whether an external user is allowed to have access to a predetermined intellectual property (IP) block. The processor apparatus can ensure debugging, security for the processor itself or security for a predetermined block included in the processor apparatus.

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