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1. 发明授权

US08650388B2 Multi-processor systems and booting methods thereof 有权
标题翻译：多处理器系统及其引导方法
公开(公告)号：US08650388B2
公开(公告)日：2014-02-11
申请号：US13064200
申请日：2011-03-10
申请人： Jong-Ho Roh , Min-Soo Lim
发明人： Jong-Ho Roh , Min-Soo Lim
IPC分类号： G06F9/00
CPC分类号： G06F9/4405 , G06F15/177
摘要： Multi-processor systems and methods thereof are provided. In an example, the multi-processor system may include a boot memory including a plurality of boot codes, each of the plurality of boot codes configured to facilitate an initialization process at one of a plurality of intellectual property (IP) blocks, each of the plurality of IP blocks having shared access to the boot memory. In another example, the multi-processor system may receive, from a first processor, a request to provide one of a plurality of boot codes from a boot memory, the received request sent in response to a system initializing signal, may read the requested boot code from the boot memory and may transfer, from a second processor, the read boot code to the first processor.
摘要翻译：提供了多处理器系统及其方法。在一个示例中，多处理器系统可以包括引导存储器，其包括多个引导代码，所述多个引导代码中的每一个被配置为便于在多个知识产权（IP）块之一处的初始化处理，多个IP块具有对引导存储器的共享访问。在另一示例中，多处理器系统可以从第一处理器接收从引导存储器提供多个引导代码中的一个的请求，响应于系统初始化信号发送的接收到的请求可以读取所请求的引导来自引导存储器的代码，并且可以从第二处理器将读取引导代码传送到第一处理器。

2. 发明授权

US07930530B2 Multi-processor system that reads one of a plurality of boot codes via memory interface buffer in response to requesting processor 有权
标题翻译：多处理器系统，响应于请求处理器，经由存储器接口缓冲器读取多个引导代码之一
公开(公告)号：US07930530B2
公开(公告)日：2011-04-19
申请号：US11704202
申请日：2007-02-09
申请人： Jong-Ho Roh , Min-Soo Lim
发明人： Jong-Ho Roh , Min-Soo Lim
IPC分类号： G06F9/00
CPC分类号： G06F9/4405 , G06F15/177
摘要： Multi-processor systems and methods thereof are provided. In an example, the multi-processor system may include a boot memory including a plurality of boot codes, each of the plurality of boot codes configured to facilitate an initialization process at one of a plurality of intellectual property (IP) blocks, each of the plurality of IP blocks having shared access to the boot memory. In another example, the multi-processor system may receive, from a first processor, a request to provide one of a plurality of boot codes from a boot memory, the received request sent in response to a system initializing signal, may read the requested boot code from the boot memory and may transfer, from a second processor, the read boot code to the first processor.
摘要翻译：提供了多处理器系统及其方法。在一个示例中，多处理器系统可以包括引导存储器，其包括多个引导代码，所述多个引导代码中的每一个被配置为便于在多个知识产权（IP）块之一处的初始化处理，多个IP块具有对引导存储器的共享访问。在另一示例中，多处理器系统可以从第一处理器接收从引导存储器提供多个引导代码中的一个的请求，响应于系统初始化信号发送的接收到的请求可以读取所请求的引导来自引导存储器的代码，并且可以从第二处理器将读取引导代码传送到第一处理器。

3. 发明申请

US20070192529A1 Multi-processor systems and methods thereof 有权
标题翻译：多处理器系统及其方法
公开(公告)号：US20070192529A1
公开(公告)日：2007-08-16
申请号：US11704202
申请日：2007-02-09
申请人： Jong-Ho Roh , Min-Soo Lim
发明人： Jong-Ho Roh , Min-Soo Lim
IPC分类号： G06F12/00
CPC分类号： G06F9/4405 , G06F15/177
摘要： Multi-processor systems and methods thereof are provided. In an example, the multi-processor system may include a boot memory including a plurality of boot codes, each of the plurality of boot codes configured to facilitate an initialization process at one of a plurality of intellectual property (IP) blocks, each of the plurality of IP blocks having shared access to the boot memory. In another example, the multi-processor system may receive, from a first processor, a request to provide one of a plurality of boot codes from a boot memory, the received request sent in response to a system initializing signal, may read the requested boot code from the boot memory and may transfer, from a second processor, the read boot code to the first processor.
摘要翻译：提供了多处理器系统及其方法。在一个示例中，多处理器系统可以包括引导存储器，其包括多个引导代码，所述多个引导代码中的每一个被配置为便于在多个知识产权（IP）块之一处的初始化处理，多个IP块具有对引导存储器的共享访问。在另一示例中，多处理器系统可以从第一处理器接收从引导存储器提供多个引导代码中的一个的请求，响应于系统初始化信号发送的接收到的请求可以读取所请求的引导来自引导存储器的代码，并且可以从第二处理器将读取引导代码传送到第一处理器。

4. 发明申请

US20110167253A1 Multi-processor systems and methods thereof 有权
标题翻译：多处理器系统及其方法
公开(公告)号：US20110167253A1
公开(公告)日：2011-07-07
申请号：US13064200
申请日：2011-03-10
申请人： Jong-Ho Roh , Min-Soo Lim
发明人： Jong-Ho Roh , Min-Soo Lim
IPC分类号： G06F9/22
CPC分类号： G06F9/4405 , G06F15/177
摘要： Multi-processor systems and methods thereof are provided. In an example, the multi-processor system may include a boot memory including a plurality of boot codes, each of the plurality of boot codes configured to facilitate an initialization process at one of a plurality of intellectual property (IP) blocks, each of the plurality of IP blocks having shared access to the boot memory. In another example, the multi-processor system may receive, from a first processor, a request to provide one of a plurality of boot codes from a boot memory, the received request sent in response to a system initializing signal, may read the requested boot code from the boot memory and may transfer, from a second processor, the read boot code to the first processor.
摘要翻译：提供了多处理器系统及其方法。在一个示例中，多处理器系统可以包括引导存储器，其包括多个引导代码，所述多个引导代码中的每一个被配置为便于在多个知识产权（IP）块之一处的初始化处理，多个IP块具有对引导存储器的共享访问。在另一示例中，多处理器系统可以从第一处理器接收从引导存储器提供多个引导代码中的一个的请求，响应于系统初始化信号发送的接收到的请求可以读取所请求的引导来自引导存储器的代码，并且可以从第二处理器将读取引导代码传送到第一处理器。

5. 发明授权

US09355615B2 Apparatuses, systems, and methods for converting a display driver sync signal into an image sensor sync signal 有权
标题翻译：用于将显示驱动器同步信号转换为图像传感器同步信号的装置，系统和方法
公开(公告)号：US09355615B2
公开(公告)日：2016-05-31
申请号：US14451029
申请日：2014-08-04
申请人： Jong-Ho Roh , Jae-Sop Kong
发明人： Jong-Ho Roh , Jae-Sop Kong
IPC分类号： G09G5/12 , G06F3/147 , G09G5/00
CPC分类号： G09G5/12 , G06F3/147 , G09G5/005 , G09G2330/021 , G09G2340/02 , G09G2340/0435 , G09G2360/18 , G09G2370/04
摘要： In one embodiment, the converter is configured to receive a first sync signal from a display driver and to convert the first sync signal into a second sync signal. The second sync signal is for controlling image sensing.
摘要翻译：在一个实施例中，转换器被配置为从显示驱动器接收第一同步信号并将第一同步信号转换为第二同步信号。第二同步信号用于控制图像感测。

6. 发明授权

US08319785B2 Image display system and method for preventing image tearing effect 有权
标题翻译：图像显示系统及防止图像撕裂效果的方法
公开(公告)号：US08319785B2
公开(公告)日：2012-11-27
申请号：US12072552
申请日：2008-02-27
申请人： Jong-Ho Roh
发明人： Jong-Ho Roh
IPC分类号： G06F12/00 , G09G5/39
CPC分类号： G09G5/397 , G09G5/393 , G09G5/395 , G09G2320/02
摘要： An image display system includes: a frame buffer including plurality of lines; a memory controller conducting writing and reading operations with the frame buffer; an image data provider supplying image data to the memory controller and generating a writing address; a display controller generating a reading address and receiving image data that is read from the frame buffer by the memory controller; a tearing-protection bus arbiter storing a burst length, receiving the writing and reading addresses, and selectively outputting the writing and reading addresses; and a display device displaying the image data by the display controller. The reading address contains a start address for the reading operation and the writing address contains a start address for the writing operation. If the writing and reading addresses are the same or if a difference between the start addresses for the writing and reading operations is less than the burst length, the tearing-protection bus arbiter outputs the reading address to the memory controller and holds the writing address.
摘要翻译：一种图像显示系统，包括：包括多行的帧缓冲器; 存储器控制器，用帧缓冲器进行写入和读取操作; 图像数据提供者向存储器控制器提供图像数据并产生写入地址; 显示控制器，其生成读取地址并接收由所述存储器控制器从所述帧缓冲器读取的图像数据; 存储突发长度的撕裂保护总线仲裁器，接收写入和读取地址，并且选择性地输出写入和读取地址; 以及通过显示控制器显示图像数据的显示装置。读取地址包含读取操作的起始地址，写入地址包含写入操作的起始地址。如果写入和读取地址相同或写入和读取操作的起始地址之间的差异小于突发长度，则撕裂保护总线仲裁器将读取地址输出到存储器控制器并保持写入地址。

7. 发明申请

US20080204464A1 Image display system and method for preventing image tearing effect 有权
标题翻译：图像显示系统及防止图像撕裂效果的方法
公开(公告)号：US20080204464A1
公开(公告)日：2008-08-28
申请号：US12072552
申请日：2008-02-27
申请人： Jong-Ho Roh
发明人： Jong-Ho Roh
IPC分类号： G09G5/39 , G09G5/36
CPC分类号： G09G5/397 , G09G5/393 , G09G5/395 , G09G2320/02
摘要： An image display system includes: a frame buffer including plurality of lines; a memory controller conducting writing and reading operations with the frame buffer; an image data provider supplying image data to the memory controller and generating a writing address; a display controller generating a reading address and receiving image data that is read from the frame buffer by the memory controller; a tearing-protection bus arbiter storing a burst length, receiving the writing and reading addresses, and selectively outputting the writing and reading addresses; and a display device displaying the image data by the display controller. The reading address contains a start address for the reading operation and the writing address contains a start address for the writing operation. If the writing and reading addresses are the same or if a difference between the start addresses for the writing and reading operations is less than the burst length, the tearing-protection bus arbiter outputs the reading address to the memory controller and holds the writing address.
摘要翻译：一种图像显示系统，包括：包括多行的帧缓冲器; 存储器控制器，用帧缓冲器进行写入和读取操作; 图像数据提供者向存储器控制器提供图像数据并产生写入地址; 显示控制器，其生成读取地址并接收由所述存储器控制器从所述帧缓冲器读取的图像数据; 存储突发长度的撕裂保护总线仲裁器，接收写入和读取地址，并且选择性地输出写入和读取地址; 以及通过显示控制器显示图像数据的显示装置。读取地址包含读取操作的起始地址，写入地址包含写入操作的起始地址。如果写入和读取地址相同或写入和读取操作的起始地址之间的差异小于突发长度，则撕裂保护总线仲裁器将读取地址输出到存储器控制器并保持写入地址。

8. 发明授权

US08737732B2 Image processing device 有权
标题翻译：图像处理装置
公开(公告)号：US08737732B2
公开(公告)日：2014-05-27
申请号：US13361325
申请日：2012-01-30
申请人： Kyoung-Man Kim , Jong-Ho Roh
发明人： Kyoung-Man Kim , Jong-Ho Roh
IPC分类号： G06K9/00
CPC分类号： G06T5/009
摘要： An image processing device includes a first image enhancer and a second image enhancer. The first image enhancer receives first image data and generates first image enhancement information by analyzing the first image data. The second image enhancer receives second image data and generates second image enhancement information by analyzing the second image data. The first image enhancer converts the first image data into first enhanced image data based on the first image enhancement information and the second image enhancement information. The second image enhancer converts the second image data into second enhanced image data based on the first image enhancement information and the second image enhancement information.
摘要翻译：图像处理装置包括第一图像增强器和第二图像增强器。第一图像增强器接收第一图像数据，并通过分析第一图像数据来生成第一图像增强信息。第二图像增强器接收第二图像数据，并通过分析第二图像数据产生第二图像增强信息。第一图像增强器基于第一图像增强信息和第二图像增强信息将第一图像数据转换为第一增强图像数据。第二图像增强器基于第一图像增强信息和第二图像增强信息将第二图像数据转换为第二增强图像数据。

9. 发明申请

US20120194512A1 THREE-DIMENSIONAL IMAGE DATA DISPLAY CONTROLLER AND THREE-DIMENSIONAL IMAGE DATA DISPLAY SYSTEM 审中-公开
标题翻译：三维图像数据显示控制器和三维图像数据显示系统
公开(公告)号：US20120194512A1
公开(公告)日：2012-08-02
申请号：US13348198
申请日：2012-01-11
申请人： Kyoung-Man Kim , Jong-Ho Roh , Jong-Jin Lee
发明人： Kyoung-Man Kim , Jong-Ho Roh , Jong-Jin Lee
IPC分类号： G06T15/00
CPC分类号： G06T15/503 , H04N13/161 , H04N13/305 , H04N13/31 , H04N13/324 , H04N13/337 , H04N13/341 , H04N13/398
摘要： A display controller can include a blending coefficient storing unit and an image mixing unit. The blending coefficient storing unit can store blending coefficients. The image mixing unit can receive left-eye image data and right-eye image data, and generate three-dimensional image data by performing a blending operation on the left-eye image data and the right-eye image data using the blending coefficients stored in the blending coefficient storing unit.
摘要翻译：显示控制器可以包括混合系数存储单元和图像混合单元。混合系数存储单元可以存储混合系数。图像混合单元可以接收左眼图像数据和右眼图像数据，并且通过使用存储在左眼图像数据和右眼图像数据中的混合系数对左眼图像数据和右眼图像数据执行混合操作来生成三维图像数据混合系数存储单元。

10. 发明授权

US07739535B2 System including an operating speed detection apparatus, an operating speed detection apparatus and method thereof 有权
标题翻译：包括操作速度检测装置，操作速度检测装置及其方法的系统
公开(公告)号：US07739535B2
公开(公告)日：2010-06-15
申请号：US11340671
申请日：2006-01-27
申请人： Hyun-Wook Ha , Jong-Ho Roh
发明人： Hyun-Wook Ha , Jong-Ho Roh
IPC分类号： G06F1/00
CPC分类号： G06F1/06 , H03K5/133
摘要： A system including an operating speed detection apparatus, an operating speed detection apparatus and method thereof. In the example method, a received clock signal may be delayed to generate a plurality of delayed clock signals. A plurality of detection signals may be generated based on the plurality of delayed clock signals and the received clock signal. An operating speed (e.g., of a system) may be determined based at least in part on the plurality of detection signals. In an example, the example method may be performed by an operating speed detection apparatus. In another example, the example method may be performed by a system including the operating speed detection apparatus.
摘要翻译：一种包括操作速度检测装置，操作速度检测装置及其方法的系统。在示例性方法中，可以延迟接收的时钟信号以产生多个延迟的时钟信号。可以基于多个延迟的时钟信号和接收到的时钟信号来生成多个检测信号。可以至少部分地基于多个检测信号来确定操作速度（例如，系统）。在一个示例中，示例性方法可以由操作速度检测装置执行。在另一示例中，示例性方法可以由包括操作速度检测装置的系统执行。

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