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1. 发明授权

US09195460B1 Using condition codes in the presence of non-numeric values 有权
标题翻译：在非数值存在的情况下使用条件代码
公开(公告)号：US09195460B1
公开(公告)日：2015-11-24
申请号：US11415781
申请日：2006-05-02
申请人： Robert Steven Glanville , John Erik Lindholm , Ming Y. Siu
发明人： Robert Steven Glanville , John Erik Lindholm , Ming Y. Siu
IPC分类号： G06F9/45 , G06F9/30
CPC分类号： G06F9/30094 , G06F9/30058
摘要： Systems and methods for compiling programs using condition codes and executing those programs when non-numeric values are present allow for explicit handling of non-numeric values. In addition to the conventional condition code values of positive, negative, and zero, a fourth value may be encoded, not a number (NaN) representing a non-numeric value. New condition tests are defined that explicitly account for condition code values of NaN. A compiler may produce code using the new condition tests to represent if and if-else statements. The code including the new condition tests generates deterministic results during execution when non-numeric values are present.
摘要翻译：使用条件代码编译程序的系统和方法，并且当存在非数字值时执行这些程序允许显式处理非数字值。除了正，负和零的常规条件代码值之外，第四值可以被编码，而不是表示非数值的数字（NaN）。定义新条件测试，明确说明NaN的条件代码值。编译器可以使用新的条件测试来生成代码来表示if和if-else语句。包含新条件测试的代码在执行时产生确定性结果，当非数值存在时。

2. 发明授权

US09058672B2 Using a pixel offset for evaluating a plane equation 有权
标题翻译：使用像素偏移来评估平面方程
公开(公告)号：US09058672B2
公开(公告)日：2015-06-16
申请号：US12898537
申请日：2010-10-05
申请人： John Erik Lindholm , Henry Packard Moreton , Ming Y. Siu , Stuart F. Oberman
发明人： John Erik Lindholm , Henry Packard Moreton , Ming Y. Siu , Stuart F. Oberman
IPC分类号： G06K9/32 , G06T3/40
CPC分类号： G06T3/4007
摘要： One embodiment of the present invention sets forth a technique controlling the pixel location at which the plane equation is evaluated. Multiple pixel offsets (dx, dy) may be specified that each define to a sub-pixel sample position. Attributes are then calculated for each sub-pixel sample position that is covered by a geometric primitive. One advantage of the technique is that anti-aliasing quality may be improved since high frequency color components may be selectively supersampled for particular geometric primitives.
摘要翻译：本发明的一个实施例提出了一种控制平面方程被评估的像素位置的技术。可以指定多个像素偏移（dx，dy），每个像素偏移定义为子像素采样位置。然后对由几何图元覆盖的每个子像素样本位置计算属性。该技术的一个优点是可以改善抗混叠质量，因为可以对特定几何基元选择性地超采样高频彩色分量。

3. 发明授权

US08645638B2 Shared single-access memory with management of multiple parallel requests 有权
标题翻译：具有管理多个并行请求的共享单访问存储器
公开(公告)号：US08645638B2
公开(公告)日：2014-02-04
申请号：US13466057
申请日：2012-05-07
申请人： Brett W. Coon , Ming Y. Siu , Weizhong Xu , Stuart F. Oberman , John R. Nickolls , Peter C. Mills
发明人： Brett W. Coon , Ming Y. Siu , Weizhong Xu , Stuart F. Oberman , John R. Nickolls , Peter C. Mills
IPC分类号： G06F12/00 , G06F13/00
CPC分类号： G06F12/084 , Y02D10/13
摘要： A memory is used by concurrent threads in a multithreaded processor. Any addressable storage location is accessible by any of the concurrent threads, but only one location at a time is accessible. The memory is coupled to parallel processing engines that generate a group of parallel memory access requests, each specifying a target address that might be the same or different for different requests. Serialization logic selects one of the target addresses and determines which of the requests specify the selected target address. All such requests are allowed to proceed in parallel, while other requests are deferred. Deferred requests may be regenerated and processed through the serialization logic so that a group of requests can be satisfied by accessing each different target address in the group exactly once.
摘要翻译：多线程处理器中的并发线程使用内存。任何可寻址的存储位置都可以由任何并发线程访问，但一次只能访问一个位置。存储器耦合到并行处理引擎，其产生一组并行存储器访问请求，每个指定对于不同请求可能相同或不同的目标地址。序列化逻辑选择一个目标地址，并确定哪个请求指定所选择的目标地址。允许所有这些请求并行进行，而其他请求被推迟。可以通过序列化逻辑重新生成和处理延迟请求，以便通过一次访问组中的每个不同的目标地址来满足一组请求。

4. 发明授权

US08533435B2 Reordering operands assigned to each one of read request ports concurrently accessing multibank register file to avoid bank conflict 有权
标题翻译：对分配给每个读取请求端口的操作数重新排序并发访问多银行寄存器文件以避免银行冲突
公开(公告)号：US08533435B2
公开(公告)日：2013-09-10
申请号：US12875843
申请日：2010-09-03
申请人： Xiaogang Qiu , Ming Y. Siu , Yan Yan Tang , John Erik Lindholm , Michael C. Shebanow , Stuart F. Oberman
发明人： Xiaogang Qiu , Ming Y. Siu , Yan Yan Tang , John Erik Lindholm , Michael C. Shebanow , Stuart F. Oberman
IPC分类号： G06F9/34
CPC分类号： G06F9/3012 , G06F9/30098 , G06F9/3824 , G06F9/3851 , G06F9/3885 , G06F9/3887 , G06F9/3889
摘要： One embodiment of the present invention sets forth a technique for collecting operands specified by an instruction. As a sequence of instructions is received the operands specified by the instructions are assigned to ports, so that each one of the operands specified by a single instruction is assigned to a different port. Reading of the operands from a multi-bank register file is scheduled by selecting an operand from each one of the different ports to produce an operand read request and ensuring that two or more of the selected operands are not stored in the same bank of the multi-bank register file. The operands specified by the operand read request are read from the multi-bank register file in a single clock cycle. Each instruction is then executed as the operands specified by the instruction are read from the multi-bank register file and collected over one or more clock cycles.
摘要翻译：本发明的一个实施例提出了一种用于收集由指令指定的操作数的技术。由于接收到指令序列，指令指定的操作数被分配给端口，以便将由单个指令指定的每个操作数分配给不同的端口。通过从不同端口中的每一个选择一个操作数来调度来自多存储器寄存器文件的操作数，以产生操作数读取请求，并确保所选择的操作数中的两个或更多个不存储在多个存储区的同一个存储区中银行寄存器文件。由操作数读取请求指定的操作数在单个时钟周期内从多存储体寄存器文件读取。然后由指令指定的操作数从多存储寄存器文件中读取并在一个或多个时钟周期内采集，执行每条指令。

5. 发明授权

US08190669B1 Multipurpose arithmetic functional unit 有权
标题翻译：多功能算术功能单元
公开(公告)号：US08190669B1
公开(公告)日：2012-05-29
申请号：US10970253
申请日：2004-10-20
申请人： Stuart F. Oberman , Ming Y. Siu
发明人： Stuart F. Oberman , Ming Y. Siu
IPC分类号： G06F7/44
CPC分类号： G06F7/44 , G06F1/035 , G06F7/5443 , G06F9/3895 , G06F2101/04 , G06F2101/08 , G06F2101/10 , G06F2101/12
摘要： Multipurpose arithmetic functional units can perform planar attribute interpolation and unary function approximation operations. In one embodiment, planar interpolation operations for coordinates (x, y) are executed by computing A*x+B*y+C, and unary function approximation operations for operand x are executed by computing F2(xb)*xh2+F1(xb)*xh+F0(xb), where xh=x−xb. Shared multiplier and adder circuits are advantageously used to implement the product and sum operations for both classes of operations.
摘要翻译：多用途算术功能单元可以执行平面属性插值和一元函数近似运算。在一个实施例中，通过计算A * x + B * y + C来执行坐标（x，y）的平面内插操作，并且通过计算F2（xb）* xh2 + F1（xb）来执行操作数x的一元函数近似运算）* xh + F0（xb），其中xh = x-xb。共享乘法器和加法器电路有利地用于实现两类操作的乘积和求和运算。

6. 发明授权

US08037119B1 Multipurpose functional unit with single-precision and double-precision operations 有权
标题翻译：具有单精度和双精度运算功能的多用途功能单元
公开(公告)号：US08037119B1
公开(公告)日：2011-10-11
申请号：US11359353
申请日：2006-02-21
申请人： Stuart F. Oberman , Ming Y. Siu
发明人： Stuart F. Oberman , Ming Y. Siu
IPC分类号： G06F7/44
CPC分类号： G06F7/4876 , G06F7/5324 , G06F7/57 , G06F17/10
摘要： A multipurpose arithmetic functional unit selectably performs planar attribute interpolation, unary function approximation, and double-precision arithmetic. In one embodiment, planar interpolation operations for coordinates (x, y) are executed by computing A*x+B*y+C, and unary function approximation operations for operand x are executed by computing F2(xb)*xh2+F1(xb)*xh+F0(xb), where xh=x−xb. Shared multiplier and adder circuits are advantageously used to implement the product and sum operations for unary function approximation and planar interpolation; the same multipliers and adders are also leveraged to implement double-precision multiplication and addition.
摘要翻译：多用途算术功能单元可选地执行平面属性插值，一元函数近似和双精度算术。在一个实施例中，通过计算A * x + B * y + C来执行坐标（x，y）的平面内插操作，并且通过计算F2（xb）* xh2 + F1（xb）来执行操作数x的一元函数近似运算）* xh + F0（xb），其中xh = x-xb。共享乘法器和加法器电路有利地用于实现一元函数近似和平面内插的乘积和求和运算; 同样的乘法器和加法器也被用来实现双精度乘法和加法。

7. 发明申请

US20110078417A1 COOPERATIVE THREAD ARRAY REDUCTION AND SCAN OPERATIONS 有权
标题翻译：合作螺线减排和扫描作业
公开(公告)号：US20110078417A1
公开(公告)日：2011-03-31
申请号：US12890227
申请日：2010-09-24
申请人： Brian FAHS , Ming Y. Siu , Brett W. Coon , John R. Nickolls , Lars Nyland
发明人： Brian FAHS , Ming Y. Siu , Brett W. Coon , John R. Nickolls , Lars Nyland
IPC分类号： G06F9/38
CPC分类号： G06F9/522 , G06F8/458 , G06F9/3004 , G06F9/30087 , G06F9/30145 , G06F9/3851
摘要： One embodiment of the present invention sets forth a technique for performing aggregation operations across multiple threads that execute independently. Aggregation is specified as part of a barrier synchronization or barrier arrival instruction, where in addition to performing the barrier synchronization or arrival, the instruction aggregates (using reduction or scan operations) values supplied by each thread. When a thread executes the barrier aggregation instruction the thread contributes to a scan or reduction result, and waits to execute any more instructions until after all of the threads have executed the barrier aggregation instruction. A reduction result is communicated to each thread after all of the threads have executed the barrier aggregation instruction and a scan result is communicated to each thread as the barrier aggregation instruction is executed by the thread.
摘要翻译：本发明的一个实施例提出了一种用于跨独立执行的多个线程执行聚合操作的技术。聚合被指定为屏障同步或屏障到达指令的一部分，其中除了执行屏障同步或到达之外，指令聚合（使用缩减或扫描操作）由每个线程提供的值。当线程执行屏障聚合指令时，线程有助于扫描或缩小结果，并等待执行任何更多指令，直到所有线程都执行了阻挡聚合指令为止。在所有线程执行了屏障聚合指令之后，向每个线程传送减少结果，并且当线程执行屏障聚合指令时，将扫描结果传送给每个线程。

8. 发明申请

US20110072438A1 FAST MAPPING TABLE REGISTER FILE ALLOCATION ALGORITHM FOR SIMT PROCESSORS 有权
标题翻译：用于SIMT处理器的快速映射表寄存器文件分配算法
公开(公告)号：US20110072438A1
公开(公告)日：2011-03-24
申请号：US12875944
申请日：2010-09-03
申请人： Michael Fiyak , Ming Y. Siu
发明人： Michael Fiyak , Ming Y. Siu
IPC分类号： G06F9/46
CPC分类号： G06F9/3009 , G06F9/3012 , G06F9/30123 , G06F9/3851
摘要： One embodiment of the present invention sets forth a technique for allocating register file entries included in a register file to a thread group. A request to allocate a number of register file entries to the thread group is received. A required number of mapping table entries included in a register file mapping table (RFMT) is determined based on the request, where each mapping table entry included in the RFMT is associated with a different plurality of register file entries included in the register file. The RFMT is parsed to locate an available mapping table entry in the RFMT for each of the required mapping table entries. For each available mapping table entry, a register file pointer is associated with an address that corresponds to a first register file entry in the plurality of register file entries associated with the available mapping table entry.
摘要翻译：本发明的一个实施例提出了一种用于将包括在寄存器文件中的寄存器文件条目分配给线程组的技术。接收到向线程组分配一些寄存器文件条目的请求。基于请求确定包括在寄存器文件映射表（RFMT）中的所需数量的映射表条目，其中包括在RFMT中的每个映射表条目与包括在寄存器文件中的不同的多个寄存器文件条目相关联。解析RFMT以在RFMT中为每个所需的映射表条目定位可用的映射表条目。对于每个可用的映射表条目，寄存器文件指针与对应于与可用映射表条目相关联的多个寄存器文件条目中的第一寄存器文件条目的地址相关联。

9. 发明申请

US20110072243A1 Unified Collector Structure for Multi-Bank Register File 有权
标题翻译：多银行登记册统一采集器结构
公开(公告)号：US20110072243A1
公开(公告)日：2011-03-24
申请号：US12875843
申请日：2010-09-03
申请人： Xiaogang Qiu , Ming Y. Siu , Yan Yan Tang , John Erik Lindholm , Michael C. Shebanow , Stuart F. Oberman
发明人： Xiaogang Qiu , Ming Y. Siu , Yan Yan Tang , John Erik Lindholm , Michael C. Shebanow , Stuart F. Oberman
IPC分类号： G06F9/30
CPC分类号： G06F9/3012 , G06F9/30098 , G06F9/3824 , G06F9/3851 , G06F9/3885 , G06F9/3887 , G06F9/3889
摘要： One embodiment of the present invention sets forth a technique for collecting operands specified by an instruction. As a sequence of instructions is received the operands specified by the instructions are assigned to ports, so that each one of the operands specified by a single instruction is assigned to a different port. Reading of the operands from a multi-bank register file is scheduled by selecting an operand from each one of the different ports to produce an operand read request and ensuring that two or more of the selected operands are not stored in the same bank of the multi-bank register file. The operands specified by the operand read request are read from the multi-bank register file in a single clock cycle. Each instruction is then executed as the operands specified by the instruction are read from the multi-bank register file and collected over one or more clock cycles.
摘要翻译：本发明的一个实施例提出了一种用于收集由指令指定的操作数的技术。由于接收到指令序列，指令指定的操作数被分配给端口，以便将由单个指令指定的每个操作数分配给不同的端口。通过从不同端口中的每一个选择一个操作数来调度来自多存储器寄存器文件的操作数，以产生操作数读取请求，并确保所选择的操作数中的两个或更多个不存储在多个存储区的同一个存储区中银行寄存器文件。由操作数读取请求指定的操作数在单个时钟周期内从多存储体寄存器文件读取。然后由指令指定的操作数从多存储寄存器文件中读取并在一个或多个时钟周期内采集，执行每条指令。

10. 发明授权

US07680988B1 Single interconnect providing read and write access to a memory shared by concurrent threads 有权
标题翻译：单一互连提供对并发线程共享的内存的读写访问
公开(公告)号：US07680988B1
公开(公告)日：2010-03-16
申请号：US11554563
申请日：2006-10-30
申请人： John R. Nickolls , Brett W. Coon , Ming Y. Siu , Stuart F. Oberman , Samuel Liu
发明人： John R. Nickolls , Brett W. Coon , Ming Y. Siu , Stuart F. Oberman , Samuel Liu
IPC分类号： G06F13/16
CPC分类号： G06F12/084 , G06F9/544 , G06F15/167 , Y02D10/13
摘要： A shared memory is usable by concurrent threads in a multithreaded processor, with any addressable storage location in the shared memory being readable and writeable by any of the threads. Processing engines that execute the threads are coupled to the shared memory via an interconnect that transfers data in only one direction (e.g., from the shared memory to the processing engines); the same interconnect supports both read and write operations. The interconnect advantageously supports multiple parallel read or write operations.
摘要翻译：共享存储器可由多线程处理器中的并发线程使用，共享存储器中的任何可寻址存储位置可由任何线程读取和写入。执行线程的处理引擎通过仅在一个方向（例如，从共享存储器到处理引擎）传送数据的互连来耦合到共享存储器; 相同的互连支持读写操作。互连有利地支持多个并行读或写操作。

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