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1. 发明申请

US20190212984A1 ARITHMETIC LOGIC UNIT FOR SINGLE-CYCLE FUSION OPERATIONS 审中-公开
公开(公告)号：US20190212984A1
公开(公告)日：2019-07-11
申请号：US15864371
申请日：2018-01-08
申请人： International Business Machines Corporation
发明人： Maarten J. Boersma , Niels Fricke
IPC分类号： G06F7/57 , G06F7/506
CPC分类号： G06F7/57 , G06F7/506 , G06F2207/506
摘要： An arithmetic logic unit is disclosed that includes a first logical circuit that generates a first partial sum result from three operands in a first stage of a single clock cycle of a processor; a second circuit that generates a second partial result in the same first stage of the clock cycle of the processor; and an adder that receives the first partial result from the first logical circuit and the second partial result from the second circuit and generates a secondary result during a second stage of the single clock cycle of the processor. The arithmetic logic unit may optionally further include a backend circuit that performs additional arithmetic and logic functions in the same single clock cycle of the processor.

2. 发明申请

US20190197763A1 VISIBILITY FUNCTION OF A THREE-DIMENSIONAL SCENE 审中-公开
公开(公告)号：US20190197763A1
公开(公告)日：2019-06-27
申请号：US16232799
申请日：2018-12-26
申请人： Dassault Systemes
发明人： Gilles Laurent , Cyril Delalandre , Tamy Boubekeur
IPC分类号： G06T15/20 , G06F7/57 , G06F17/16 , G06T1/20 , G06T1/60
CPC分类号： G06T15/20 , G06F7/57 , G06F17/16 , G06T1/20 , G06T1/60 , G06T15/08 , G06T15/40 , G06T2210/21
摘要： The disclosure notably relates to a computer-implemented method of computing a visibility function of a 3D scene. The method includes obtaining a set of directions ({right arrow over (ω)}) in the 3D scene, computing a set of lines that are parallel to the direction, for each computed set of lines, sampling the lines of the set into spatial segments, associating each line of a set with a bit field, each spatial segment of the line corresponding to a bit of the bit field, superimposing the set of lines and the 3D scene, when a spatial segment of a line intersects a geometry in the 3D scene, marking the bit, corresponding to the spatial segment of the bit field, associated with the line, obtaining two points in the 3D scene, identifying spatial segments having a closest alignment with the query segment, computing the visibility of the query segment by performing a logical bit operation.

3. 发明申请

US20170288684A1 PROCESSING APPARATUS AND PROCESSING SYSTEM 有权
公开(公告)号：US20170288684A1
公开(公告)日：2017-10-05
申请号：US15624931
申请日：2017-06-16
申请人： OLYMPUS CORPORATION
发明人： Tomoharu OGIHARA
IPC分类号： H03L7/095 , G06F7/57 , H03K19/177
CPC分类号： H03L7/095 , G06F7/57 , H03K19/17716
摘要： A processing apparatus includes an FPGA unit connected to an oscillator configured to output a first clock, wherein the FPGA unit includes: a PLL circuit configured to output a second clock with a frequency of a predetermined ratio with respect to a frequency of the first clock and configured to output a lock signal (detection signal); an input and output monitoring unit configured to detect a ratio between the frequencies of the first clock and the second clock, compare the detected ratio with the predetermined ratio, and output an abnormal signal when the detected ratio does not coincide with the predetermined ratio; and an initialization unit configured to output a reset signal when the input and output monitoring unit outputs the abnormal signal and configured to output the reset signal when the PLL circuit outputs the lock signal.

4. 发明授权

US09600236B2 Systems and methods for computing mathematical functions 有权
公开(公告)号：US09600236B2
公开(公告)日：2017-03-21
申请号：US14486891
申请日：2014-09-15
申请人： Vivante Corporation
发明人： Mike M. Cai , Lefan Zhong
IPC分类号： G06F7/38 , G06F7/556 , G06F1/035 , G06F7/57 , G06F7/552 , G06F7/548
CPC分类号： G06F7/556 , G06F1/0356 , G06F7/548 , G06F7/5525 , G06F7/57 , G06F2101/08 , G06F2101/10 , G06F2101/12
摘要： Mathematical functions are computed in a single pipeline performing a polynomial approximation (e.g. a quadratic approximation, or the like); and one or more data tables corresponding to at least one of the RCP, SQRT, EXP or LOG functions operable to be coupled to the single pipeline according to one or more opcodes; wherein the single pipeline is operable for computing at least one of RCP, SQRT, EXP or LOG functions according to the one or more opcodes. SIN and COS are also computed using the pipeline according to the approximation ((−1)^IntX)*Sin(π*Min(FracX, 1.0−FracX)/Min(FracX, 1.0−FracX). A pipeline portion approximates Sin(π*FracX) using tables and interpolation and a subsequent stage multiplies this approximation by FracX. For input arguments of x close 1.0. LOG 2(x−1)/(x−1) is computed using a first pipeline portion using tables and interpolation and subsequently multiplied by (x−1). A DIV operation may also be performed with input arguments scaled up to avoid underflow as needed.

5. 发明授权

US09594694B2 Dynamic evaluation and adaption of hardware hash functions 有权
标题翻译：硬件哈希函数的动态评估和适应
公开(公告)号：US09594694B2
公开(公告)日：2017-03-14
申请号：US14993583
申请日：2016-01-12
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Sascha Junghans , Matthias Klein , Thomas Schlipf
IPC分类号： G06F3/00 , G06F12/10 , G06F9/38 , G06F1/16 , G06F1/03
CPC分类号： G06F7/544 , G06F1/0328 , G06F1/1615 , G06F7/57 , G06F9/3838 , G06F12/1018 , G06F17/30109 , G06F17/30949 , G06F2212/401
摘要： Creating hash values based on bit values of an input vector. An apparatus includes a first and a second hash table, a first and second hash function generator adapted to configure a respective hash function for a creation of a first and second hash value based on the bit values of the input vector. The hash values are stored in the respective hash tables. An evaluation unit includes a comparison unit to compare a respective effectiveness of the first hash function and the second hash function, and an exchanging unit responsive to the comparison unit adapted to replace the first hash function by the second hash function.
摘要翻译：基于输入向量的位值创建哈希值。一种装置包括第一和第二散列表，第一和第二散列函数发生器，其适于基于输入向量的位值来配置用于创建第一和第二散列值的相应散列函数。哈希值存储在相应的散列表中。评估单元包括比较单元，用于比较第一散列函数和第二散列函数的相应有效性，以及响应于比较单元的交换单元，适于通过第二散列函数来替换第一散列函数。

6. 发明申请

US20160124715A1 MULTI-ELEMENT COMPARISON AND MULTI-ELEMENT ADDITION 有权
标题翻译：多元素比较和多元素补充
公开(公告)号：US20160124715A1
公开(公告)日：2016-05-05
申请号：US14528326
申请日：2014-10-30
申请人： ARM LIMITED
发明人： Neil BURGESS , David Raymond LUTZ
IPC分类号： G06F7/50 , G06F17/16
CPC分类号： G06F7/50 , G06F7/02 , G06F7/509 , G06F7/544 , G06F7/57 , G06F9/3001 , G06F9/30021 , G06F9/30036 , G06F17/16
摘要： An apparatus 8 for performing a selectable one of multi-element comparison and multi-element addition is formed from a carry propagate adders stage 12 supplied with four non-final intermediate operands formed from the input vector, a non-final limit value selecting stage 14, which when performing a multi-element comparison serves to select, in dependence upon at least carry save values generated by the carry propagate adder, limit values that are of a larger or a smaller value of a pair of elements. A final intermediate operand forming stage 16 forms final intermediate operands from two non-final intermediate sum values from the carry propagate adders stage 12 and supplies these to a final output adder stage 18 which forms a sum of these two final intermediate operands to generate an output operand which can be either one or more candidates for limit values that will be a maximum or minimum value, or a sum value, or partial sum values in the case of a multi-element addition.
摘要翻译：从提供有由输入向量形成的四个非最终中间操作数的进位传播加法器级12形成用于执行多元素比较和多元素相加可选择的装置8，非最终极限值选择级14 其在执行多元素比较时用于根据进位传播加法器产生的至少携带保存值来选择具有一对元素的较大值或较小值的限制值。最终的中间操作数形成级16从来自进位传播加法器级12的两个非最终中间和值形成最终中间操作数，并将其提供给最终输出加法器级18，其形成这两个最终中间操作数的和以产生输出操作数，其可以是作为最大值或最小值的极限值的一个或多个候选者，或者是多个元素添加的情况下的和值或部分和值。

7. 发明授权

US09323500B2 Reducing power consumption in a fused multiply-add (FMA) unit responsive to input data values 有权
公开(公告)号：US09323500B2
公开(公告)日：2016-04-26
申请号：US13785528
申请日：2013-03-05
申请人： Brian Hickmann , Dennis Bradford , Thomas Fletcher
发明人： Brian Hickmann , Dennis Bradford , Thomas Fletcher
IPC分类号： G06F7/38 , G06F7/60 , G06F7/48 , G06F7/57 , G06F7/483 , G06F7/544 , G06F9/30 , G06F1/32
CPC分类号： G06F7/60 , G06F1/324 , G06F1/3243 , G06F7/48 , G06F7/483 , G06F7/5443 , G06F7/57 , G06F9/30 , G06F9/3001 , G06F2207/3884 , Y02D10/126 , Y02D10/152
摘要： In an embodiment, a fused multiply-add (FMA) circuit is configured to receive a plurality of input data values to perform an FMA instruction on the input data values. The circuit includes a multiplier unit and an adder unit coupled to an output of the multiplier unit, and a control logic to receive the input data values and to reduce switching activity and thus reduce power consumption of one or more components of the circuit based on a value of one or more of the input data values. Other embodiments are described and claimed.

8. 发明申请

US20160110161A1 APPARATUS AND METHOD FOR PERFORMING RECIPROCAL ESTIMATION OPERATION 有权
标题翻译：用于执行重复估计操作的装置和方法
公开(公告)号：US20160110161A1
公开(公告)日：2016-04-21
申请号：US14519787
申请日：2014-10-21
申请人： ARM LIMITED
发明人： David Raymond LUTZ , Neil BURGESS
IPC分类号： G06F7/485
CPC分类号： G06F7/485 , G06F7/483 , G06F7/535 , G06F7/5525 , G06F7/57 , G06F2207/48 , G06F2207/5356
摘要： A data processing apparatus has floating-point add circuitry for performing a floating-point add operation for adding or subtracting two floating-point operands. The apparatus also has reciprocal estimation circuitry for performing a reciprocal estimation operation on a first operand to generate a reciprocal estimate value which represents an estimate of a reciprocal of a first operand or an estimate or a reciprocal of the square root of the first operand. The reciprocal estimation circuitry is physically distinct from the floating-point adder circuitry, which allows both the reciprocal estimate and the add operations to be faster.
摘要翻译：数据处理装置具有用于执行用于相加或减去两个浮点操作数的浮点加法运算的浮点加法电路。该装置还具有相互估计电路，用于对第一操作数执行倒数估计操作，以产生表示第一操作数的倒数的估计或第一操作数的平方根的倒数的倒数的倒数估计值。相互估计电路在物理上不同于浮点加法器电路，这允许相互估计和相加操作都更快。

9. 发明授权

US09274800B2 Dynamic evaluation and adaption of hardware hash functions 有权
标题翻译：硬件哈希函数的动态评估和适应
公开(公告)号：US09274800B2
公开(公告)日：2016-03-01
申请号：US14060900
申请日：2013-10-23
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Sascha Junghans , Matthias Klein , Thomas Schlipf
IPC分类号： G06F3/00 , G06F9/38 , G06F1/16 , G06F1/03
CPC分类号： G06F7/544 , G06F1/0328 , G06F1/1615 , G06F7/57 , G06F9/3838 , G06F12/1018 , G06F17/30109 , G06F17/30949 , G06F2212/401
摘要： Creating hash values based on bit values of an input vector. An apparatus includes a first and a second hash table, a first and second hash function generator adapted to configure a respective hash function for a creation of a first and second hash value based on the bit values of the input vector. The hash values are stored in the respective hash tables. An evaluation unit includes a comparison unit to compare a respective effectiveness of the first hash function and the second hash function, and an exchanging unit responsive to the comparison unit adapted to replace the first hash function by the second hash function.
摘要翻译：基于输入向量的位值创建哈希值。一种装置包括第一和第二散列表，第一和第二散列函数发生器，其适于基于输入向量的位值来配置用于创建第一和第二散列值的相应散列函数。哈希值存储在相应的散列表中。评估单元包括比较单元，用于比较第一散列函数和第二散列函数的相应有效性，以及响应于比较单元的交换单元，适于通过第二散列函数来替换第一散列函数。

10. 发明授权

US09131083B2 Portable imaging device with multi-core processor 有权
标题翻译：便携式成像设备，具有多核处理器
公开(公告)号：US09131083B2
公开(公告)日：2015-09-08
申请号：US13620901
申请日：2012-09-15
申请人： Kia Silverbrook
发明人： Kia Silverbrook
IPC分类号： H04N5/232 , H04N1/00 , H04N5/378 , B41J2/14 , B41J2/175 , B41J3/44 , B41J11/00 , B41J11/70 , B41J15/04 , B82Y30/00 , G06F9/22 , G06F9/26 , G06F9/30 , G06F9/38 , G06F21/79 , G06F21/86 , G06K1/12 , G06K7/10 , G06K7/14 , G06K19/06 , G06K19/073 , G11C11/56 , H01L23/00 , H04N1/21 , H04N1/32 , H04N5/225 , H04N5/262 , B41J2/165 , B41J2/04 , G06F7/57 , H04N101/00
CPC分类号： H04N5/76 , B41J2/14314 , B41J2/14427 , B41J2/16585 , B41J2/17513 , B41J2/17596 , B41J3/445 , B41J11/0005 , B41J11/005 , B41J11/70 , B41J15/04 , B41J2002/041 , B41J2202/21 , B82Y30/00 , G06F7/57 , G06F9/226 , G06F9/265 , G06F9/30094 , G06F9/30101 , G06F9/3885 , G06F21/79 , G06F21/86 , G06F2221/2129 , G06K1/121 , G06K7/10762 , G06K7/14 , G06K7/1417 , G06K19/06037 , G06K19/073 , G11C11/56 , H01L23/576 , H01L2924/0002 , H04N1/00127 , H04N1/00278 , H04N1/00326 , H04N1/0044 , H04N1/00965 , H04N1/00968 , H04N1/2112 , H04N1/2154 , H04N1/32101 , H04N1/32133 , H04N1/32561 , H04N1/32587 , H04N1/32593 , H04N1/32603 , H04N1/46 , H04N5/225 , H04N5/228 , H04N5/23229 , H04N5/235 , H04N5/2628 , H04N5/378 , H04N2101/00 , H04N2201/0008 , H04N2201/0084 , H04N2201/3222 , H04N2201/3261 , H04N2201/3264 , H04N2201/3269 , H04N2201/3276 , H04N2201/328 , H01L2924/00
摘要： A portable imaging device that has a CMOS image sensor, a color display for displaying an image sensed by the CMOS image sensor and a central processor. The central processor has an image sensor interface for receiving data from the CMOS image sensor, multiple processing units for parallel operation to simultaneously process the data, and an image display interface for sending processed data to the color display. The central processor is integrated onto a single chip.
摘要翻译：一种具有CMOS图像传感器的便携式成像装置，用于显示由CMOS图像传感器感测到的图像的彩色显示器和中央处理器。中央处理器具有用于从CMOS图像传感器接收数据的图像传感器接口，用于并行处理数据的多个处理单元，以及用于将处理后的数据发送到彩色显示器的图像显示接口。中央处理器集成到单个芯片上。

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