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1. 发明授权

US08615627B2 Raid system based on calculated average of mechanical loads and solder joint damage and controlling method of the same 失效
标题翻译： Raid系统基于机械负载和焊点损伤的计算平均值及其控制方法
公开(公告)号：US08615627B2
公开(公告)日：2013-12-24
申请号：US13181651
申请日：2011-07-13
申请人： Takahiro Omori , Minoru Mukai , Kenji Hirohata
发明人： Takahiro Omori , Minoru Mukai , Kenji Hirohata
IPC分类号： G06F12/16
CPC分类号： G06F3/0658 , G06F3/0616 , G06F3/0688
摘要： A RAID system to transfer data to and from host equipment includes a semiconductor storage unit, a semiconductor-memory selector, and a memory controller. The semiconductor storage unit includes two or more semiconductor memories, a mounting board, and solder joints. The semiconductor memories are mounted on the mounting board. The solder joints are between the semiconductor memories and the mounting board. The semiconductor-memory selector selects a combination of the semiconductor memories to dispersively record the data in the semiconductor storage unit. The memory controller accesses the combination in response to a request of the host equipment. In addition, the selector selects the combination so that mechanical loads received by the semiconductor memories are averaged.
摘要翻译：用于向主机设备传送数据的RAID系统包括半导体存储单元，半导体存储器选择器和存储器控制器。半导体存储单元包括两个或更多个半导体存储器，安装板和焊接接头。半导体存储器安装在安装板上。焊点位于半导体存储器和安装板之间。半导体存储器选择器选择半导体存储器的组合以将数据分散地记录在半导体存储单元中。存储器控制器响应于主机设备的请求来访问组合。此外，选择器选择组合，使得由半导体存储器接收的机械负载被平均。

2. 发明授权

US08482998B2 Storage device and method for controlling storage device 有权
标题翻译：用于控制存储设备的存储设备和方法
公开(公告)号：US08482998B2
公开(公告)日：2013-07-09
申请号：US13446034
申请日：2012-04-13
申请人： Minoru Mukai , Kenji Hirohata , Tomoko Monda
发明人： Minoru Mukai , Kenji Hirohata , Tomoko Monda
IPC分类号： G11C7/00
CPC分类号： H05K3/341 , H05K3/3436 , H05K2201/10151 , H05K2201/10159 , H05K2203/163 , Y02P70/613
摘要： A storage device includes: a printed circuit board; a semiconductor memory package mounted on the printed circuit board via solder joints, the semiconductor memory package incorporating semiconductor memories; a sensor configured to measure a physical quantity relating to a state of the storage device; a database including a damage estimation model base to be used for estimating damage of the solder joints from the physical quantity measured by the sensor; a damage estimating module configured to calculate a damage estimation value of the solder joints from the physical quantity using the damage estimation model base; and a controller configured to control writing, reading, and erasure of electronic data to or from the semiconductor memories based on the damage estimation values calculated by the damage estimating module.
摘要翻译：存储装置包括：印刷电路板; 半导体存储器封装，其通过焊点安装在所述印刷电路板上，所述半导体存储器封装结合有半导体存储器; 被配置为测量与所述存储装置的状态有关的物理量的传感器; 数据库，包括用于从传感器测量的物理量估计焊点的损坏的损伤估计模型库; 损伤估计模块，被配置为使用所述损伤估计模型基础从所述物理量计算所述焊点的损伤估计值; 以及控制器，其被配置为基于由所述损伤估计模块计算出的损伤估计值来控制对所述半导体存储器的电子数据的写入，读取和擦除。

3. 发明申请

US20120248440A1 SEMICONDUCTOR MODULE 有权
标题翻译：半导体模块
公开(公告)号：US20120248440A1
公开(公告)日：2012-10-04
申请号：US13429762
申请日：2012-03-26
申请人： Kenji HIROHATA , Minoru Mukai , Tomoko Monda
发明人： Kenji HIROHATA , Minoru Mukai , Tomoko Monda
IPC分类号： H01L23/64
CPC分类号： G01R27/16 , H01L23/64 , H01L2924/0002 , H01L2924/00
摘要： According to one embodiment, a semiconductor module comprises a substrate, a first wiring, an electrode pad, a junction, an oscillator, and a detector. The first wiring is disposed on the substrate, and has a characteristic impedance Z0. The electrode pad is connected to the first wiring. The junction is disposed on the electrode pad, and has an impedance Z1. The oscillator is disposed in contact with the first wiring, and oscillates a pulse wave of a voltage toward the junction via the first wiring. The detector is disposed in contact with the first wiring, and detects an output wave of the pulse wave from the junction. The characteristic impedance Z0 and the impedance Z1 satisfy a following relationship (1),  Z   0 - Z   1 Z   0  ≤ 0.05 . ( 1 )
摘要翻译：根据一个实施例，半导体模块包括衬底，第一布线，电极焊盘，结，振荡器和检测器。第一布线设置在基板上，并具有特性阻抗Z0。电极焊盘连接到第一布线。接点设置在电极焊盘上，并具有阻抗Z1。振荡器设置成与第一布线接触，并且经由第一布线使得电压脉冲波朝向结。检测器设置成与第一布线接触，并检测来自结的脉冲波的输出波。特征阻抗Z0和阻抗Z1满足以下关系式（1），0。。（1）

4. 发明授权

US08189412B2 Storage device and method for controlling storage device 有权
标题翻译：用于控制存储设备的存储设备和方法
公开(公告)号：US08189412B2
公开(公告)日：2012-05-29
申请号：US12509555
申请日：2009-07-27
申请人： Minoru Mukai , Kenji Hirohata , Tomoko Monda
发明人： Minoru Mukai , Kenji Hirohata , Tomoko Monda
IPC分类号： G11C29/00
CPC分类号： H05K3/341 , H05K3/3436 , H05K2201/10151 , H05K2201/10159 , H05K2203/163 , Y02P70/613
摘要： A storage device includes: a printed circuit board; a semiconductor memory package mounted on the printed circuit board via solder joints, the semiconductor memory package incorporating semiconductor memories; a sensor configured to measure a physical quantity relating to a state of the storage device; a database including a damage estimation model base to be used for estimating damage of the solder joints from the physical quantity measured by the sensor; a damage estimating module configured to calculate a damage estimation value of the solder joints from the physical quantity using the damage estimation model base; and a controller configured to control writing, reading, and erasure of electronic data to or from the semiconductor memories based on the damage estimation values calculated by the damage estimating module.
摘要翻译：存储装置包括：印刷电路板; 半导体存储器封装，其通过焊点安装在所述印刷电路板上，所述半导体存储器封装结合有半导体存储器; 被配置为测量与所述存储装置的状态有关的物理量的传感器; 数据库，包括用于从传感器测量的物理量估计焊点的损坏的损伤估计模型库; 损伤估计模块，被配置为使用所述损伤估计模型基础从所述物理量计算所述焊点的损伤估计值; 以及控制器，其被配置为基于由所述损伤估计模块计算出的损伤估计值来控制对所述半导体存储器的电子数据的写入，读取和擦除。

5. 发明授权

US08050055B2 Electronic apparatus 有权
标题翻译：电子仪器
公开(公告)号：US08050055B2
公开(公告)日：2011-11-01
申请号：US12355125
申请日：2009-01-16
申请人： Tomoko Monda , Minoru Mukai
发明人： Tomoko Monda , Minoru Mukai
IPC分类号： H05K5/00
CPC分类号： H05K1/0268 , H05K1/116 , H05K3/3447 , H05K7/142 , H05K2201/09663 , H05K2201/10598
摘要： According to one aspect of the invention, there is provided an electronic apparatus having a circuit board supporting structure, the circuit board supporting structure including: a casing including a first body and a second body, the first body having a first boss portion, the second body having a second boss portion; a jig including a cylindrical portion having, and a flange portion formed on an outer periphery, the cylindrical portion configured to slidably receive the first boss portion and the second boss portion in an inner peripheral wall; and a circuit board disposed in the casing. The first and second boss portions are configured to be fastened by a bolt member; the circuit board has a hole and a joining region provided around the hole, the hole configured to allow the cylindrical portion to penetrate therethrough; and the joining region is configured to be soldered to the flange portion.
摘要翻译：根据本发明的一个方面，提供了一种具有电路板支撑结构的电子设备，该电路板支撑结构包括：壳体，包括第一主体和第二主体，第一主体具有第一凸台部分，第二主体部件主体具有第二凸台部分; 包括具有圆柱形部分的夹具和形成在外周上的凸缘部分，该圆筒部分构造成在内周壁中可滑动地容纳第一凸台部分和第二凸台部分; 以及设置在壳体中的电路板。第一和第二凸台部分被构造成由螺栓构件紧固; 所述电路板具有孔和设置在所述孔周围的接合区域，所述孔构造成允许所述圆筒部穿过其中; 并且所述接合区域被构造成被焊接到所述凸缘部。

6. 发明申请

US20100251039A1 MEMORY DEVICE 有权
标题翻译：内存设备
公开(公告)号：US20100251039A1
公开(公告)日：2010-09-30
申请号：US12748807
申请日：2010-03-29
申请人： Kenji HIROHATA , Minoru YONEZAWA , Chie MORITA , Takeichiro NISHIKAWA , Minoru NAKATSUGAWA , Minoru MUKAI
发明人： Kenji HIROHATA , Minoru YONEZAWA , Chie MORITA , Takeichiro NISHIKAWA , Minoru NAKATSUGAWA , Minoru MUKAI
IPC分类号： G06F11/00
CPC分类号： G06F11/008 , G06F3/0616 , G06F3/0625 , G06F3/0631 , G06F3/0685 , Y02D10/154
摘要： A first module calculates a failure occurrence risk index of each data storage area address. A second module calculates a power saving index of each data storage area address. A third module calculates an access speed index per unit data volume necessary to access each data storage area address. A fourth module generates a distribution table that represents the failure occurrence risk index, the power saving index, and the access speed index for each candidate address, with respect to data to be distributed. A fifth module selects a candidate address in the distribution table such that the power saving index and the access speed index meet restricting conditions and the failure occurrence risk index is minimized, and distributes the data to the candidate address.
摘要翻译：第一模块计算每个数据存储区域地址的故障发生风险指数。第二模块计算每个数据存储区域地址的功率节省指数。第三模块计算访问每个数据存储区域地址所需的每单位数据量的访问速度指数。第四模块相对于要分发的数据生成表示每个候选地址的故障发生风险指数，功率节省指数和访问速度指数的分布表。第五模块选择分配表中的候选地址，使得省电指标和访问速度指数满足限制条件，故障发生风险指数最小化，并将数据分配给候选地址。

7. 发明申请

US20100082913A1 STORAGE DEVICE AND METHOD FOR CONTROLLING STORAGE DEVICE 有权
标题翻译：存储装置和用于控制存储装置的方法
公开(公告)号：US20100082913A1
公开(公告)日：2010-04-01
申请号：US12509555
申请日：2009-07-27
申请人： Minoru Mukai , Kenji Hirohata , Tomoko Monda
发明人： Minoru Mukai , Kenji Hirohata , Tomoko Monda
IPC分类号： G06F12/00 , G06F19/00
CPC分类号： H05K3/341 , H05K3/3436 , H05K2201/10151 , H05K2201/10159 , H05K2203/163 , Y02P70/613
摘要： A storage device includes: a printed circuit board; a semiconductor memory package mounted on the printed circuit board via solder joints, the semiconductor memory package incorporating semiconductor memories; a sensor configured to measure a physical quantity relating to a state of the storage device; a database including a damage estimation model base to be used for estimating damage of the solder joints from the physical quantity measured by the sensor; a damage estimating module configured to calculate a damage estimation value of the solder joints from the physical quantity using the damage estimation model base; and a controller configured to control writing, reading, and erasure of electronic data to or from the semiconductor memories based on the damage estimation values calculated by the damage estimating module.
摘要翻译：存储装置包括：印刷电路板; 半导体存储器封装，其通过焊点安装在所述印刷电路板上，所述半导体存储器封装结合有半导体存储器; 被配置为测量与所述存储装置的状态有关的物理量的传感器; 数据库，包括用于从传感器测量的物理量估计焊点的损坏的损伤估计模型库; 损伤估计模块，被配置为使用所述损伤估计模型基础从所述物理量计算所述焊点的损伤估计值; 以及控制器，其被配置为基于由所述损伤估计模块计算出的损伤估计值来控制对所述半导体存储器的电子数据的写入，读取和擦除。

8. 发明申请

US20080068814A1 Electronic equipment 有权
标题翻译：电子设备
公开(公告)号：US20080068814A1
公开(公告)日：2008-03-20
申请号：US11899783
申请日：2007-09-07
申请人： Tomoko Monda , Minoru Mukai
发明人： Tomoko Monda , Minoru Mukai
IPC分类号： H05K5/02
CPC分类号： H05K7/142
摘要： An electronic equipment is provided with a housing which is assembled by combining first and second cases. The first and second cases are provided with first and second projections on inner surfaces of the first and second cases. A circuit board is located in the housing, which has a hole having a diameter larger than those of the first and second projections. The first and second projections are so engaged with each other as to be inserted in the hole. Stoppers are provided around the first and second projections so as to form gaps between first and second projections and the circuit board.
摘要翻译：电子设备设置有通过组合第一和第二壳体而组装的壳体。第一和第二壳体在第一和第二壳体的内表面上设置有第一和第二突起。电路板位于壳体中，其具有直径大于第一和第二突起的直径的孔。第一和第二突起彼此接合以插入孔中。围绕第一和第二突起设置止动件，以便在第一和第二突起与电路板之间形成间隙。

9. 发明授权

US08582310B2 Electronic apparatus having circuit board 失效
标题翻译：具有电路板的电子设备
公开(公告)号：US08582310B2
公开(公告)日：2013-11-12
申请号：US13137917
申请日：2011-09-21
申请人： Tomoko Monda , Minoru Mukai
发明人： Tomoko Monda , Minoru Mukai
IPC分类号： H05K5/00
CPC分类号： H05K7/142 , G01R31/046 , G01R31/2812 , H05K1/0268 , H05K3/341 , H05K2201/10409 , H05K2203/163
摘要： An electronic apparatus includes: a circuit board that is disposed inside a case that is formed by coupling first and second case halves, the circuit board being interposed between first and second boss portions; first and second conductive members that are disposed between a gap formed between the first boss portion and the circuit board; a third conductive member that is disposed between the first boss portion and the first conductive member and between the first boss portion and the second conductive member to electrically connect the first conductive member to the second conductive member; and a measurement circuit that is electrically connected to a first wiring and a second wiring, which are respectively connected to the first conductive member and the second conductive member, and measures an electrical characteristic value of at least one of the first conductive member and the second conductive member.
摘要翻译：电子设备包括：电路板，设置在通过联接第一和第二半壳形成的壳体内，电路板插入在第一和第二凸台部分之间; 第一和第二导电构件，其布置在形成在第一凸台部分和电路板之间的间隙之间; 第三导电构件，其设置在第一凸台部分和第一导电构件之间以及第一凸台部分和第二导电构件之间，以将第一导电构件电连接到第二导电构件; 以及测量电路，其电连接到分别连接到第一导电构件和第二导电构件的第一布线和第二布线，并且测量第一导电构件和第二导电构件中的至少一个的电特性值导电构件。

10. 发明授权

US08200813B2 Monitoring device and a server 有权
标题翻译：监控设备和服务器
公开(公告)号：US08200813B2
公开(公告)日：2012-06-12
申请号：US12766350
申请日：2010-04-23
申请人： Kenji Hirohata , Minoru Mukai
发明人： Kenji Hirohata , Minoru Mukai
IPC分类号： G06F15/173
CPC分类号： H04L29/00 , G05B23/0224 , H04L41/142 , H04L41/145 , H04L43/022
摘要： According to one embodiment, each monitoring device acquires monitoring variables from an observation target, generates an individual multidimensional distribution of the monitoring variables, and transmits the individual multidimensional distribution to a server. The server generates sampling data using the individual multidimensional distribution received from each monitoring device, generates an overall multidimensional distribution of the monitoring variables using the sampling data, determines a statistical model of each index using the overall multidimensional distribution, generates an overall index multidimensional distribution of indexes using the statistical model and the overall multidimensional distribution, and transmits the overall index multidimensional distribution and statistical models to each monitoring device. The monitoring device generates sampling data using the individual multidimensional distribution, and calculates a positioning of the observation target using the sampling data, the overall index multidimensional distribution and the statistical models.
摘要翻译：根据一个实施例，每个监视设备从观察目标获取监视变量，生成监控变量的单独的多维分布，并将该单个多维分布发送到服务器。服务器使用从每个监控设备接收到的单独的多维分布生成采样数据，使用采样数据生成监视变量的整体多维分布，使用整体多维分布确定每个索引的统计模型，生成整体索引多维分布指标使用统计模型和整体多维分布，并将整体索引多维分布和统计模型传输到每个监控设备。监测装置使用单独的多维分布生成采样数据，并使用采样数据，整体索引多维分布和统计模型来计算观测目标的定位。

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