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    • 4. 发明授权
    • Shift register and semiconductor display device
    • 移位寄存器和半导体显示器件
    • US08664976B2
    • 2014-03-04
    • US13248420
    • 2011-09-29
    • Mitsuaki OsameAya Anzai
    • Mitsuaki OsameAya Anzai
    • G09G3/36G11C19/00G06F7/38
    • G09G3/3677G09G3/3266G09G3/3275G09G3/3688G11C19/00G11C19/28
    • The invention provides a shift register which can operate normally while suppressing a delay of signal and a rounding of waveform. The shift register of the invention includes a plurality of stages of flip-flop circuits each of which includes a clocked inverter. The clocked inverter includes a first transistor and a second transistor which are connected in series, a first compensation circuit including a third transistor and a fourth transistor which are connected in series, and a second compensation circuit including a fifth transistor and a transmission gate. According to the first compensation circuit, a timing at which a signal outputted from the flip-flop circuit rises or falls can be controlled in synchronization with an output of two stages before. The second compensation circuit can control a clock signal input can be controlled.
    • 本发明提供了一种能够在抑制信号延迟和波形舍入的同时正常工作的移位寄存器。 本发明的移位寄存器包括多个级的触发器电路,每个触发器电路包括时钟反相器。 时钟反相器包括串联连接的第一晶体管和第二晶体管,包括串联连接的第三晶体管和第四晶体管的第一补偿电路和包括第五晶体管和透射栅的第二补偿电路。 根据第一补偿电路,可以与前两级的输出同步地控制从触发器电路输出的信号上升或下降的定时。 第二补偿电路可以控制时钟信号输入可以控制。