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1. 发明授权

US07984281B2 Shared interrupt controller for a multi-threaded processor 有权
标题翻译：用于多线程处理器的共享中断控制器
公开(公告)号：US07984281B2
公开(公告)日：2011-07-19
申请号：US11954615
申请日：2007-12-12
申请人： Erich James Plondke , Lucian Codrescu , Muhammad Ahmed , William Anderson , Suresh K. Venkumahanti
发明人： Erich James Plondke , Lucian Codrescu , Muhammad Ahmed , William Anderson , Suresh K. Venkumahanti
IPC分类号： G06F9/00
CPC分类号： G06F9/4812 , G06F9/30123 , G06F9/3013 , G06F9/3851
摘要： A multi-threaded processor is disclosed that includes a sequencer adapted to provide instructions associated with one or more threads of a multi-threaded processor. The sequencer includes an interrupt controller adapted to receive one or more interrupts and to selectively allow a first thread of the one or more threads to service at least one interrupt. The interrupt controller includes logic to preclude a second thread of the one or more threads from responding to the at least one interrupt.
摘要翻译：公开了一种多线程处理器，其包括适于提供与多线程处理器的一个或多个线程相关联的指令的定序器。定序器包括适于接收一个或多个中断并且选择性地允许一个或多个线程的第一线程服务于至少一个中断的中断控制器。所述中断控制器包括排除所述一个或多个线程的第二线程以响应所述至少一个中断的逻辑。

2. 发明申请

US20100281483A1 PROGRAMMABLE SCHEDULING CO-PROCESSOR 审中-公开
标题翻译：可编程调度协同处理器
公开(公告)号：US20100281483A1
公开(公告)日：2010-11-04
申请号：US12433824
申请日：2009-04-30
申请人： Shlomo Selim Rakib , Alexander Hubris , Muhammad Ahmed
发明人： Shlomo Selim Rakib , Alexander Hubris , Muhammad Ahmed
IPC分类号： G06F9/46 , G06F12/00
CPC分类号： G06F9/4881 , G06F9/30032 , G06F9/3009 , G06F9/30181 , G06F9/3828 , G06F9/3851 , G06F9/3853 , G06F9/3887 , G06F9/5066 , G06F15/8023 , G06F2209/483
摘要： A scheduling co-processor for scheduling the execution of threads on a processor is disclosed. In certain embodiments, the scheduling co-processor includes one or more engines (such as lookup tables) that are programmable with a Petri-net representation of a thread scheduling algorithm. The scheduling co-processor may further include a token list to store tokens associated with the Petri-net; an enabled-thread list to indicate which threads are enabled for execution in response to particular tokens being present in the token list; and a ready-thread list to indicate which threads from the enabled-thread list are ready for execution when data and/or space availability conditions associated with the threads are satisfied.
摘要翻译：公开了一种用于调度处理器上的线程执行的调度协处理器。在某些实施例中，调度协处理器包括可以用线程调度算法的Petri网表示来编程的一个或多个引擎（诸如查找表）。调度协处理器还可以包括用于存储与Petri网相关联的令牌的令牌列表; 启用线程列表，以指示响应于令牌列表中存在的特定令牌而启用执行的线程; 以及准备线程列表，以指示当与线程相关联的数据和/或空间可用性条件得到满足时，来自启用线程列表的哪些线程准备好执行。

3. 发明申请

US20100281236A1 APPARATUS AND METHOD FOR TRANSFERRING DATA WITHIN A VECTOR PROCESSOR 审中-公开
标题翻译：用于在矢量处理器中传输数据的装置和方法
公开(公告)号：US20100281236A1
公开(公告)日：2010-11-04
申请号：US12433821
申请日：2009-04-30
申请人： Shlomo Selim Rakib , Muhammad Ahmed , Marc Schaub
发明人： Shlomo Selim Rakib , Muhammad Ahmed , Marc Schaub
IPC分类号： G06F9/30 , G06F15/80 , G06F9/06
CPC分类号： G06F9/3828 , G06F9/3851 , G06F9/3887 , G06F9/3891
摘要： An apparatus for processing data may include an array of processing elements (such as an n×m or n×n array of processing elements) configured to simultaneously perform operations on a plurality of data elements using a single instruction. Each processing element in the array may be configured to transfer data directly to at least one neighboring processing element within the array. In selected embodiments, the apparatus may include exchange registers to temporarily store data transferred between neighboring processing elements.
摘要翻译：用于处理数据的装置可以包括被配置为使用单个指令同时对多个数据元素执行操作的处理元件（诸如n×m或n×n个处理元件阵列）的阵列。阵列中的每个处理元件可以被配置为将数据直接传送到阵列内的至少一个相邻的处理元件。在所选择的实施例中，该装置可以包括用于临时存储在相邻处理元件之间传送的数据的交换寄存器。

4. 发明申请

US20100281234A1 INTERLEAVED MULTI-THREADED VECTOR PROCESSOR 审中-公开
标题翻译：交互式多通道矢量处理器
公开(公告)号：US20100281234A1
公开(公告)日：2010-11-04
申请号：US12433826
申请日：2009-04-30
申请人： MUHAMMAD AHMED , Marc Schaub , Shlomo Selim Rakib
发明人： MUHAMMAD AHMED , Marc Schaub , Shlomo Selim Rakib
IPC分类号： G06F9/30 , G06F15/80 , G06F9/02
CPC分类号： G06F9/3851 , G06F9/30032 , G06F9/30036 , G06F9/30101 , G06F9/30123 , G06F9/30181 , G06F9/3828 , G06F9/3877 , G06F9/3885 , G06F9/3887 , G06F9/3889 , G06F9/3891
摘要： A method includes providing a processor configured to execute instructions. The method may further include providing a first set of registers in the processor to store first data and first instructions associated with a first thread, and providing a second set of registers in the processor to store second data and second instructions associated with a second thread. The method may further include transmitting the first data and first instructions associated with the first thread to the first set of registers, and executing the first instructions in order to process the first data. The method may further include transmitting the second data and second instructions to the second set of registers while executing the first instructions and processing the first data. A corresponding apparatus is also disclosed and claimed herein.
摘要翻译：一种方法包括提供配置成执行指令的处理器。该方法还可以包括在处理器中提供第一组寄存器以存储与第一线程相关联的第一数据和第一指令，以及在处理器中提供第二组寄存器以存储与第二线程相关联的第二数据和第二指令。该方法还可以包括将第一数据和与第一线程相关联的第一指令发送到第一组寄存器，以及执行第一指令以便处理第一数据。该方法还可以包括在执行第一指令并处理第一数据时将第二数据和第二指令发送到第二组寄存器。本文还公开并要求对应的装置。

5. 发明申请

US20080016316A1 Method and system to indicate an exception-triggering page within a microprocessor 有权
标题翻译：用于指示微处理器内的异常触发页面的方法和系统
公开(公告)号：US20080016316A1
公开(公告)日：2008-01-17
申请号：US11487284
申请日：2006-07-14
申请人： Lucian Codrescu , Erich Plondke , Muhammad Ahmed , Vijaya Kumar Janjanam
发明人： Lucian Codrescu , Erich Plondke , Muhammad Ahmed , Vijaya Kumar Janjanam
IPC分类号： G06F12/00
CPC分类号： G06F12/1009 , G06F12/1027 , G06F2212/684
摘要： A method and system to indicate which page within a software-managed page table triggers an exception within a microprocessor, such as, for example, a digital signal processor, wherein a software-managed translation lookaside buffer (TLB) module receives a virtual address produced by an instruction within a Very Long Instruction Word (VLIW) packet, such as, for example, a fetch instruction, and further compares the virtual address to each stored TLB entry. If a match exists, then the TLB module outputs a corresponding mapped physical address for the instruction. Otherwise, if the VLIW packet spans two pages, where a first page is present as a TLB entry within the TLB module and the second page is missing from the stored TLB entries, an indication bit within a data field of a control register is set to identify the TLB miss exception to a software management unit. The software management unit retrieves the indication bit information from the register and further performs a page table look-up within the software-managed page table using the indication bit information in order to retrieve the missing page information. Subsequently, the missing page information is written into a new TLB entry within the TLB module for subsequent virtual address translation and execution of the packet of instructions.
摘要翻译：一种方法和系统，用于指示软件管理的页表内的哪个页面在微处理器（例如数字信号处理器）内触发异常，其中软件管理的翻译后备缓冲器（TLB）模块接收产生的虚拟地址通过超长指令字（VLIW）分组（例如，取指令）中的指令，并且还将虚拟地址与每个存储的TLB条目进行比较。如果匹配存在，则TLB模块输出相应的映射物理地址。否则，如果VLIW分组跨越两页，其中第一页作为TLB模块中的TLB条目存在，并且第二页从存储的TLB条目丢失，则将控制寄存器的数据字段内的指示位设置为识别软件管理单元的TLB错误异常。软件管理单元从寄存器检索指示位信息，并使用指示位信息进一步在软件管理的页表中执行页表查找，以便检索丢失页信息。随后，丢失的页面信息被写入TLB模块中的新TLB条目，用于随后的虚拟地址转换和指令分组的执行。

6. 发明申请

US20070271417A1 METHOD AND SYSTEM FOR MAXIMUM RESIDENCY REPLACEMENT OF CACHE MEMORY 有权
标题翻译：用于缓存存储器最大容量替换的方法和系统
公开(公告)号：US20070271417A1
公开(公告)日：2007-11-22
申请号：US11531111
申请日：2006-09-12
申请人： Muhammad Ahmed
发明人： Muhammad Ahmed
IPC分类号： G06F12/00
CPC分类号： G06F12/123 , G06F12/0859 , G06F12/126 , G06F12/128 , Y02D10/13
摘要： Techniques for use in CDMA-based products and services, including replacing cache memory allocation so as to maximize residency of a plurality of set ways following a tag miss allocation. Herein, steps and instructions provide for forming a first-in, first-out (FIFO) cache way listing of victim ways for the cache memory, wherein the depth of the FIFO cache way listing approximately equals the number of ways in the cache memory. The method and system place a victim way on the FIFO cache way listing only in the event that a tag miss results in a tag miss allocation, the victim way is placed at the tail of the FIFO cache way listing after any previously selected victim way. Use of a victim way on the FIFO cache way listing is prevented in the event of an incomplete prior allocation of the victim way by, for example, stalling a reuse request until such initial allocation of the victim way completes or replaying a reuse request until such initial allocation of the victim way completes.
摘要翻译：用于基于CDMA的产品和服务的技术，包括替换高速缓冲存储器分配，以便在标签未命中分配之后最大化多个设置路径的驻留。这里，步骤和指令提供用于形成用于高速缓存存储器的受害方式的先入先出（FIFO）高速缓存方式列表，其中FIFO高速缓存方式列表的深度大约等于高速缓存存储器中的路数。该方法和系统将牺牲方式置于FIFO缓存方式列表中，只有在标记未命中导致标签未命中分配的情况下，受害者的方式将放置在先前选择的受害方式之后的FIFO缓存方式列表的尾部。通过例如停止重用请求直到对受害者方式的这种初始分配完成或重放重用请求直到此为止，才能防止在FIFO高速缓存方式列表中使用受害方式。受害方的初始分配完成。

7. 发明申请

US20060242384A1 Register files for a digital signal processor operating in an interleaved multi-threaded environment 有权
标题翻译：为交错多线程环境中的数字信号处理器注册文件
公开(公告)号：US20060242384A1
公开(公告)日：2006-10-26
申请号：US11115916
申请日：2005-04-26
申请人： Muhammad Ahmed , Erich Plondke , Lucian Codrescu , William Anderson
发明人： Muhammad Ahmed , Erich Plondke , Lucian Codrescu , William Anderson
IPC分类号： G06F15/00
CPC分类号： G06F9/30149 , G06F9/3012 , G06F9/3851 , G06F9/3885
摘要： A processor device is disclosed and includes a memory and a sequencer that is responsive to the memory. The sequencer supports very long instruction word (VLIW) type instructions and at least one VLIW instruction packet uses a number of operands during execution. The processor device further includes a plurality of instruction execution units responsive to the sequencer and a plurality of register files. Each of the plurality of register files includes a plurality of registers and the plurality of register files are coupled to the plurality of instruction execution units. Further, each of the plurality of register files includes a number of data read ports and the number of data read ports of each of the plurality of register files is less than the number of operands used by the at least one VLIW instruction packet.
摘要翻译：公开了处理器设备，并且包括响应于存储器的存储器和定序器。定序器支持非常长的指令字（VLIW）类型指令，并且至少一个VLIW指令分组在执行期间使用多个操作数。处理器设备还包括响应于定序器的多个指令执行单元和多个寄存器文件。多个寄存器文件中的每一个包括多个寄存器，并且多个寄存器文件耦合到多个指令执行单元。此外，多个寄存器文件中的每一个包括多个数据读取端口，并且多个寄存器堆栈中的每一个的数据读取端口的数量小于由至少一个VLIW指令包使用的操作数的数量。

8. 发明申请

US20060230253A1 Unified non-partitioned register files for a digital signal processor operating in an interleaved multi-threaded environment 审中-公开
标题翻译：用于在交错多线程环境中工作的数字信号处理器的统一非分区寄存器文件
公开(公告)号：US20060230253A1
公开(公告)日：2006-10-12
申请号：US11103744
申请日：2005-04-11
申请人： Lucian Codrescu , Erich Plondke , Muhammad Ahmed , William Anderson , Taylor Simpson
发明人： Lucian Codrescu , Erich Plondke , Muhammad Ahmed , William Anderson , Taylor Simpson
IPC分类号： G06F15/00
CPC分类号： H04M1/72522 , G06F9/3012 , G06F9/3885 , H04M1/2535 , H04M2250/02
摘要： A processor device is disclosed and includes a memory and a sequencer that is responsive to the memory. The sequencer can support very long instruction word (VLIW) instructions and superscalar instructions. The processor device further includes a first instruction execution unit responsive to the sequencer, a second instruction execution unit responsive to the sequencer, a third instruction execution unit responsive to the sequencer, and a fourth instruction execution unit responsive to the sequencer. Further, the processor device includes a plurality of register files and each of the plurality of register files includes a plurality of registers. The plurality of register files are coupled to the sequencer and coupled to the first instruction execution unit, the second instruction execution unit, the third instruction execution unit, and the fourth instruction execution unit.
摘要翻译：公开了处理器设备，并且包括响应于存储器的存储器和定序器。音序器可以支持非常长的指令字（VLIW）指令和超标量指令。处理器装置还包括响应于定序器的第一指令执行单元，响应于定序器的第二指令执行单元，响应于定序器的第三指令执行单元，以及响应于定序器的第四指令执行单元。此外，处理器装置包括多个寄存器文件，并且多个寄存器文件中的每一个包括多个寄存器。多个寄存器文件耦合到定序器并耦合到第一指令执行单元，第二指令执行单元，第三指令执行单元和第四指令执行单元。

9. 发明申请

US20060218559A1 Method and system for variable thread allocation and switching in a multithreaded processor 有权
标题翻译：多线程处理器中可变线程分配和切换的方法和系统
公开(公告)号：US20060218559A1
公开(公告)日：2006-09-28
申请号：US11089474
申请日：2005-03-23
申请人： Muhammad Ahmed , Sujat Jamil , Erich Plondke , Lucian Codrescu , William Anderson
发明人： Muhammad Ahmed , Sujat Jamil , Erich Plondke , Lucian Codrescu , William Anderson
IPC分类号： G06F9/46
CPC分类号： G06F9/3851
摘要： Techniques for processing transmissions in a communications (e.g., CDMA) system. An aspect of the disclosed subject matter includes a method for processing instructions on a multithreaded processor. The multithreaded processor processes a plurality of threads via a plurality of processor pipelines. The method includes the step determining the operating frequency, F, at which the multithreaded processor operates. Then, the method determines a variable thread switch timeout state for triggering the switching of the processing among the plurality of active threads. The variable thread switch timeout state varies so that each of the plurality of active threads operates at a frequency of an allocated portion of the frequency, F. The allocated portion at which the active threads operate is determined at least in part in order to optimize the operation of the multithreaded processor. The method further switches the processing from a first one of the active threads to a next one of the active threads upon the occurrence of the variable thread switch timeout state.
摘要翻译：用于在通信（例如，CDMA）系统中处理传输的技术。所公开的主题的一个方面包括用于在多线程处理器上处理指令的方法。多线程处理器经由多个处理器管线处理多个线程。该方法包括确定多线程处理器工作的工作频率F的步骤。然后，该方法确定用于触发多个活动线程之间的处理切换的可变线程切换超时状态。可变线程切换超时状态改变，使得多个活动线程中的每一个以所分配的频率部分F的频率运行。活动线程运行的分配部分至少部分地被确定，以便优化操作多线程处理器。在发生可变线程切换超时状态时，该方法还将处理从主动线程中的第一个切换到下一个活动线程。

10. 发明申请

US20060212681A1 Processor and method of grouping and executing dependent instructions in a packet 有权
公开(公告)号：US20060212681A1
公开(公告)日：2006-09-21
申请号：US11086475
申请日：2005-03-21
申请人： Lucian Codrescu , Erich Plondke , Muhammad Ahmed , Sujat Jamil , William Anderson
发明人： Lucian Codrescu , Erich Plondke , Muhammad Ahmed , Sujat Jamil , William Anderson
IPC分类号： G06F9/30
CPC分类号： G06F9/3885 , G06F9/3851 , G06F9/3853
摘要： An interleaved multithreading pipeline operating method comprises reading an instruction packet containing at least two instructions, steering a first instruction of the instruction packet to a first execution unit for execution and generating a first result, steering a second instruction of the instruction packet to a second execution unit for execution using the first result and generating a second result, and storing the second result.

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