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1. 发明授权

US10415987B2 Identifying, processing and displaying data point clusters 有权
公开(公告)号：US10415987B2
公开(公告)日：2019-09-17
申请号：US15108510
申请日：2016-06-24
申请人： GOOGLE LLC , Steve Chien , Mark Yinan Li , Marc Schaub , Benjamin Anderson , James Aspinall , Zhou Bailiang , Ruwen Hess
发明人： Steve Chien , Mark Yinan Li , Marc Schaub , Benjamin Anderson , James Aspinall , Zhou Bailiang , Ruwen Hess
IPC分类号： G01C21/34 , G01C21/36 , G06F16/29 , H04W4/21 , G06F16/901
摘要： Presented are techniques of identifying, processing and displaying data point clusters (850, 851) associated with map information (200) in an efficient manner. Methods and systems are disclosed which process map information (200) to identify clusters (850, 851) of requested data points for display (1020), based on iterative clustering and filtering of the data points. Methods and systems are also disclosed which generate polygons (1860, 1861, 1901-05) representing the clusters. The amount of data to be processed and/or displayed can be reduced, without loss of any associated information content in a displayed map.

2. 发明授权

US08713285B2 Address generation unit for accessing a multi-dimensional data structure in a desired pattern 有权
标题翻译：地址生成单元，用于以期望的模式访问多维数据结构
公开(公告)号：US08713285B2
公开(公告)日：2014-04-29
申请号：US12331333
申请日：2008-12-09
申请人： Shlomo Selim Rakib , Marc Schaub
发明人： Shlomo Selim Rakib , Marc Schaub
IPC分类号： G06F12/02 , G06F12/10 , G06F9/34
CPC分类号： G06F17/30949 , G06F9/345 , G06F9/3885 , G06F9/3891
摘要： An apparatus, system, and method for providing a multi-dimensional data structure and address generation unit configured to calculate real addresses in order to access the multi-dimensional data structure in a desired pattern. The address generation unit may be configured to calculate the real addresses by executing a series of nested loops pre-programmed into the address generation unit prior to accessing the multi-dimensional data structure. The address generation unit may receive as inputs a set of parameters defining characteristics of the nested loops such as a starting offset, number of iterations or step size for loops, data structure dimensions, or loop starting point inheritance. A vector processor may then access the multi-dimensional data structure at the real addresses calculated by the address generation unit. The multi-dimensional data structure may be stored in a buffer in a data memory.
摘要翻译：一种用于提供多维数据结构和地址生成单元的装置，系统和方法，其被配置为计算实际地址以便以期望的模式访问多维数据结构。地址生成单元可以被配置为通过在访问多维数据结构之前执行预编程到地址生成单元中的一系列嵌套循环来计算实际地址。地址生成单元可以作为输入接收定义嵌套循环的特征的一组参数，例如起始偏移，循环次数或循环的步长，数据结构维度或循环起点继承。然后，向量处理器可以以由地址生成单元计算的实际地址访问多维数据结构。多维数据结构可以存储在数据存储器中的缓冲器中。

3. 发明授权

US07031331B2 Method and system for managing packets in a shared memory buffer that serves multiple output links 有权
公开(公告)号：US07031331B2
公开(公告)日：2006-04-18
申请号：US09930597
申请日：2001-08-15
申请人： Marc Schaub
发明人： Marc Schaub
IPC分类号： H04L12/56
CPC分类号： H04L49/9021 , H04L47/6205 , H04L49/90 , H04L49/901
摘要： Managing packets in a shared memory buffer involves linking buffered packets into a linked list in the order that the packets are written into the shared memory buffer, examining the packets in the order of the linked list to determine which packets are intended for available output links, and then dispatching the oldest packet that is intended for an available output link even if the packet is preceded on the linked list by packets that are older but are intended for unavailable output links. Packets are stored with NEXT pointers that establish the linked list and output link identifiers that identify the intended output links of the packets. The head of the linked list is identified by a linked list HEAD pointer. When a packet is dispatched, the packet is removed from the linked list by adjusting the linked list HEAD pointer or the NEXT pointer of the previous packet.

4. 发明申请

US20100281192A1 APPARATUS AND METHOD FOR TRANSFERRING DATA WITHIN A DATA PROCESSING SYSTEM 审中-公开
标题翻译：用于在数据处理系统中传输数据的装置和方法
公开(公告)号：US20100281192A1
公开(公告)日：2010-11-04
申请号：US12433822
申请日：2009-04-30
申请人： Shlomo Selim Rakib , Marc Schaub
发明人： Shlomo Selim Rakib , Marc Schaub
IPC分类号： G06F5/14 , H04L9/32
CPC分类号： G06F5/08
摘要： An apparatus for transferring data between buffers within a data processing architecture includes first and second memory devices. The apparatus further includes a first connection manager associated with a first buffer in the first memory device, and a second connection manager associated with a second buffer in the second memory device. The first and second connection managers manage data transfers between the first and second buffers. The first connection manager is configured to receive a token from the second connection manager in order to trigger data transfer between the first buffer and the second buffer. The first connection manager is further configured to initiate a data transfer between the first and second buffers in response to receiving the token. This token-based method for initiating data transfers between the connection managers requires little or no CPU intervention.
摘要翻译：一种用于在数据处理架构内的缓冲器之间传送数据的装置包括第一和第二存储器件。该设备还包括与第一存储器设备中的第一缓冲器相关联的第一连接管理器和与第二存储器设备中的第二缓冲器相关联的第二连接管理器。第一和第二连接管理器管理第一和第二缓冲器之间的数据传输。第一连接管理器被配置为从第二连接管理器接收令牌，以便触发第一缓冲器和第二缓冲器之间的数据传输。第一连接管理器还被配置为响应于接收到令牌而在第一和第二缓冲器之间发起数据传输。这种基于令牌的方法用于在连接管理器之间启动数据传输需要很少或没有CPU干预。

5. 发明授权

US08359455B2 System and method for generating real addresses using a connection ID designating a buffer and an access pattern 有权
标题翻译：使用指定缓冲器和访问模式的连接ID生成实际地址的系统和方法
公开(公告)号：US08359455B2
公开(公告)日：2013-01-22
申请号：US12331324
申请日：2008-12-09
申请人： Shlomo Selim Rakib , Marc Schaub
发明人： Shlomo Selim Rakib , Marc Schaub
IPC分类号： G06F12/00 , G06F12/10
CPC分类号： G06F12/0284
摘要： A system and method for generating a real address in data memory in response to a read/write request may include generating an access request to at least one of read and write data to the data memory. A connection identifier (ID), received in association with the access request; may include a buffer ID designating a buffer in the data memory in which to access the data, and a port ID designating a pattern in which to access the data in the buffer. The method may further include translating the connection ID into the real address of the data memory, and accessing the data memory at a location corresponding to the real address. Different types of buffers, such as point-to-point, scatter, and gather buffers may be used, and different patterns, such as first-in-first out (FIFO), nested loop, matrix transforms may be used.
摘要翻译：响应于读/写请求在数据存储器中产生真实地址的系统和方法可以包括向数据存储器生成至少一个读取和写入数据的访问请求。与访问请求相关联地接收的连接标识符（ID）; 可以包括指定访问数据的数据存储器中的缓冲器的缓冲器ID，以及指定访问缓冲器中的数据的模式的端口ID。该方法还可以包括将连接ID转换成数据存储器的实际地址，以及在对应于真实地址的位置处访问数据存储器。可以使用不同类型的缓冲器，例如点对点，散布和采集缓冲器，并且可以使用不同的模式，诸如先进先出（FIFO），嵌套循环，矩阵变换。

6. 发明申请

US20100145993A1 Address Generation Unit Using End Point Patterns to Scan Multi-Dimensional Data Structures 有权
标题翻译：使用端点模式扫描多维数据结构的地址生成单元
公开(公告)号：US20100145993A1
公开(公告)日：2010-06-10
申请号：US12331337
申请日：2008-12-09
申请人： Shlomo Selim Rakib , Marc Schaub
发明人： Shlomo Selim Rakib , Marc Schaub
IPC分类号： G06F17/30
CPC分类号： G06F17/30949 , G06F9/345 , G06F9/3885 , G06F9/3891 , Y10S707/957
摘要： A system in accordance with the invention may include a data memory storing a multi-dimensional (e.g., a two-dimensional) data structure. An address generation unit is provided to calculate real addresses in order to access the multi-dimensional data structure in a desired pattern. The address generation unit may be configured to calculate real addresses by moving across the multi-dimensional data structure between pairs of end points. The pairs of end points (as well as parameters such as the step size between the end points) may be pre-programmed into the address generation unit prior to accessing the multi-dimensional data structure. A processor, such as a vector processor, may be configured to access (e.g., read or write data to) the data structure at the real addresses calculated by the address generation unit.
摘要翻译：根据本发明的系统可以包括存储多维（例如，二维）数据结构的数据存储器。提供地址生成单元以计算实际地址以便以期望的模式访问多维数据结构。地址生成单元可以被配置为通过跨越两个端点之间的多维数据结构移动来计算实际地址。可以在访问多维数据结构之前，将这些端点对（以及诸如端点之间的步长的参数）预编程到地址生成单元中。诸如向量处理器的处理器可以被配置为以由地址生成单元计算的实际地址访问（例如，读取或写入数据）数据结构。

7. 发明授权

US09003165B2 Address generation unit using end point patterns to scan multi-dimensional data structures 有权
标题翻译：地址生成单元使用端点模式扫描多维数据结构
公开(公告)号：US09003165B2
公开(公告)日：2015-04-07
申请号：US12331337
申请日：2008-12-09
申请人： Shlomo Selim Rakib , Marc Schaub
发明人： Shlomo Selim Rakib , Marc Schaub
IPC分类号： G06F17/30 , G06F9/345 , G06F9/38
CPC分类号： G06F17/30949 , G06F9/345 , G06F9/3885 , G06F9/3891 , Y10S707/957
摘要： A system in accordance with the invention may include a data memory storing a multi-dimensional (e.g., a two-dimensional) data structure. An address generation unit is provided to calculate real addresses in order to access the multi-dimensional data structure in a desired pattern. The address generation unit may be configured to calculate real addresses by moving across the multi-dimensional data structure between pairs of end points. The pairs of end points (as well as parameters such as the step size between the end points) may be pre-programmed into the address generation unit prior to accessing the multi-dimensional data structure. A processor, such as a vector processor, may be configured to access (e.g., read or write data to) the data structure at the real addresses calculated by the address generation unit.
摘要翻译：根据本发明的系统可以包括存储多维（例如，二维）数据结构的数据存储器。提供地址生成单元以计算实际地址以便以期望的模式访问多维数据结构。地址生成单元可以被配置为通过跨越两个端点之间的多维数据结构移动来计算实际地址。可以在访问多维数据结构之前，将这些端点对（以及诸如端点之间的步长的参数）预编程到地址生成单元中。诸如向量处理器的处理器可以被配置为以由地址生成单元计算的实际地址访问（例如，读取或写入数据）数据结构。

8. 发明申请

US20100281236A1 APPARATUS AND METHOD FOR TRANSFERRING DATA WITHIN A VECTOR PROCESSOR 审中-公开
标题翻译：用于在矢量处理器中传输数据的装置和方法
公开(公告)号：US20100281236A1
公开(公告)日：2010-11-04
申请号：US12433821
申请日：2009-04-30
申请人： Shlomo Selim Rakib , Muhammad Ahmed , Marc Schaub
发明人： Shlomo Selim Rakib , Muhammad Ahmed , Marc Schaub
IPC分类号： G06F9/30 , G06F15/80 , G06F9/06
CPC分类号： G06F9/3828 , G06F9/3851 , G06F9/3887 , G06F9/3891
摘要： An apparatus for processing data may include an array of processing elements (such as an n×m or n×n array of processing elements) configured to simultaneously perform operations on a plurality of data elements using a single instruction. Each processing element in the array may be configured to transfer data directly to at least one neighboring processing element within the array. In selected embodiments, the apparatus may include exchange registers to temporarily store data transferred between neighboring processing elements.
摘要翻译：用于处理数据的装置可以包括被配置为使用单个指令同时对多个数据元素执行操作的处理元件（诸如n×m或n×n个处理元件阵列）的阵列。阵列中的每个处理元件可以被配置为将数据直接传送到阵列内的至少一个相邻的处理元件。在所选择的实施例中，该装置可以包括用于临时存储在相邻处理元件之间传送的数据的交换寄存器。

9. 发明申请

US20100281234A1 INTERLEAVED MULTI-THREADED VECTOR PROCESSOR 审中-公开
标题翻译：交互式多通道矢量处理器
公开(公告)号：US20100281234A1
公开(公告)日：2010-11-04
申请号：US12433826
申请日：2009-04-30
申请人： MUHAMMAD AHMED , Marc Schaub , Shlomo Selim Rakib
发明人： MUHAMMAD AHMED , Marc Schaub , Shlomo Selim Rakib
IPC分类号： G06F9/30 , G06F15/80 , G06F9/02
CPC分类号： G06F9/3851 , G06F9/30032 , G06F9/30036 , G06F9/30101 , G06F9/30123 , G06F9/30181 , G06F9/3828 , G06F9/3877 , G06F9/3885 , G06F9/3887 , G06F9/3889 , G06F9/3891
摘要： A method includes providing a processor configured to execute instructions. The method may further include providing a first set of registers in the processor to store first data and first instructions associated with a first thread, and providing a second set of registers in the processor to store second data and second instructions associated with a second thread. The method may further include transmitting the first data and first instructions associated with the first thread to the first set of registers, and executing the first instructions in order to process the first data. The method may further include transmitting the second data and second instructions to the second set of registers while executing the first instructions and processing the first data. A corresponding apparatus is also disclosed and claimed herein.
摘要翻译：一种方法包括提供配置成执行指令的处理器。该方法还可以包括在处理器中提供第一组寄存器以存储与第一线程相关联的第一数据和第一指令，以及在处理器中提供第二组寄存器以存储与第二线程相关联的第二数据和第二指令。该方法还可以包括将第一数据和与第一线程相关联的第一指令发送到第一组寄存器，以及执行第一指令以便处理第一数据。该方法还可以包括在执行第一指令并处理第一数据时将第二数据和第二指令发送到第二组寄存器。本文还公开并要求对应的装置。

10. 发明申请

US20100146238A1 System and Method for Generating Real Addresses in Data Processing Architectures 有权
标题翻译：用于在数据处理架构中生成实际地址的系统和方法
公开(公告)号：US20100146238A1
公开(公告)日：2010-06-10
申请号：US12331324
申请日：2008-12-09
申请人： Shlomo Selim Rakib , Marc Schaub
发明人： Shlomo Selim Rakib , Marc Schaub
IPC分类号： G06F12/00
CPC分类号： G06F12/0284
摘要： A system and method for generating a real address in data memory in response to a read/write request may include generating an access request to at least one of read and write data to a data memory. A connection ID may be received in association with the access request. This connection ID may include a buffer ID designating a buffer in data memory to which to access the data, and a port ID designating a pattern in which to access the data in the buffer. The method may further include translating the connection ID into a real address of the data memory, and accessing the data in the data memory at a location corresponding to the real address.
摘要翻译：响应于读/写请求在数据存储器中产生实地址的系统和方法可以包括向数据存储器生成对读和写数据中的至少一个的访问请求。可以与访问请求相关联地接收连接ID。该连接ID可以包括指定访问数据的数据存储器中的缓冲器的缓冲器ID，以及指定访问缓冲器中的数据的模式的端口ID。该方法还可以包括将连接ID转换成数据存储器的实际地址，以及在对应于实际地址的位置处访问数据存储器中的数据。

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