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1. 发明申请

US20160299843A1 UNIFIED NON-VOLATILE MEMORY AND ELECTRONIC APPARATUS APPLYING THE NON-VOLATILE MEMORY 审中-公开
标题翻译：统一的非易失性存储器和电子设备应用非易失性存储器
公开(公告)号：US20160299843A1
公开(公告)日：2016-10-13
申请号：US14682078
申请日：2015-04-08
申请人： Nanya Technology Corp.
发明人： Da-Zen Chuang , Chi-Hsiang Kuo
IPC分类号： G06F12/06 , G11C7/10 , G11C14/00 , G06F12/02
CPC分类号： G11C11/16 , G06F12/0238 , G06F2212/1032 , G06F2212/1056 , G06F2212/202 , G06F2212/205 , G11C11/005 , G11C11/22 , G11C13/0002 , G11C13/0004 , G11C13/0011 , Y02D10/13
摘要： Discloses is a unified non-volatile memory comprising: a first memory section, served as a read only memory; and a second memory section, served as a random access memory. An electronic apparatus applying the unified non-volatile memory is also disclosed.
摘要翻译：公开了一种统一的非易失性存储器，包括：第一存储器部分，用作只读存储器; 以及作为随机存取存储器的第二存储器部分。还公开了应用统一的非易失性存储器的电子设备。

2. 发明授权

US09412433B2 Counter based design for temperature controlled refresh 有权
标题翻译：基于计数器的温度控制刷新设计
公开(公告)号：US09412433B2
公开(公告)日：2016-08-09
申请号：US14161655
申请日：2014-01-22
申请人： NANYA TECHNOLOGY CORP.
发明人： Donald Martin Morgan
IPC分类号： G11C11/406
CPC分类号： G11C11/40626 , G11C11/40611
摘要： A DRAM includes: a temperature sensor for monitoring a temperature operating condition of the DRAM; and a binary counter coupled to the temperature sensor, for receiving external commands to perform a refresh operation, and incrementing a count upon each received external command, wherein the refresh operation will be selectively skipped according to a value of the binary counter. The binary counter is activated to a first mode when the temperature sensor determines the temperature operating condition of the DRAM goes below a first threshold and activated to a second mode when the temperature sensor determines the temperature operating condition of the DRAM goes below a second threshold lower than the first threshold.
摘要翻译： DRAM包括：用于监视DRAM的温度操作状态的温度传感器; 以及耦合到所述温度传感器的二进制计数器，用于接收执行刷新操作的外部命令，以及在每个所接收的外部命令时递增计数，其中根据二进制计数器的值选择性地跳过刷新操作。当温度传感器确定DRAM的温度操作条件低于第一阈值时，二进制计数器被激活到第一模式，并且当温度传感器确定DRAM的温度操作条件低于第二阈值时激活到第二模式比第一个门槛。

3. 发明申请

US20160077143A1 POWER UP DETECTING SYSTEM 有权
公开(公告)号：US20160077143A1
公开(公告)日：2016-03-17
申请号：US14951508
申请日：2015-11-25
申请人： NANYA TECHNOLOGY CORP.
发明人： Wayne A. BATT
IPC分类号： G01R31/02 , G11C5/14 , G01R19/165
CPC分类号： G01R31/02 , G01R19/165 , G11C5/143 , G11C5/148 , G11C29/12005
摘要： A power up detecting system for generating one of a first power up detecting signal and a second power up detecting signal as the final power up detecting signal, according to power provided by a power supplier. The power up detecting system comprises: a power up detecting module, controlled by a control signal to generate the first power up detecting signal in a first mode and to generate the second power up detecting signal in a second mode, wherein a voltage level of the first power up detecting signal is transited when the power reaches a first predetermined voltage value, and the voltage level of the second power up detecting signal is transited when the power reaches a second predetermined voltage value; where the first predetermined voltage value is higher than the second predetermined voltage value.

4. 发明授权

US09091929B2 Method of forming tight-pitched pattern 有权
标题翻译：形成紧密花纹图案的方法
公开(公告)号：US09091929B2
公开(公告)日：2015-07-28
申请号：US14249371
申请日：2014-04-10
申请人： NANYA TECHNOLOGY CORP.
发明人： Chun-Wei Wu
IPC分类号： G03F7/20 , G03F1/50
CPC分类号： G03F7/2022 , G03F1/50 , G03F7/203 , G03F7/70458 , G03F7/70466
摘要： A method of forming a tight-pitched pattern. A target pattern including a plurality of first stripe patterns is provided. Each of the first stripe patterns has a first width and a first length. A photomask includes a plurality of second stripe patterns corresponding to the first stripe patterns is provided. Each of the second stripe patterns has a second width and a second length. A first exposure process with the photomask is provided in an exposure system. The first exposure process uses a first light source with a higher resolution that is capable of resolving the second width of each of the second stripe patterns. Finally, a second exposure process with the photo-mask is provided in the exposure system. The second exposure process uses a second light source with a lower resolution that is not adequate to resolve the second width of each of the second stripe patterns.
摘要翻译：形成紧斜图案的方法。提供包括多个第一条纹图案的目标图案。每个第一条纹图案具有第一宽度和第一长度。光掩模包括与第一条纹图案相对应的多个第二条纹。每个第二条纹图案具有第二宽度和第二长度。在曝光系统中提供了具有光掩模的第一曝光过程。第一曝光过程使用具有更高分辨率的第一光源，其能够分辨每个第二条纹图案的第二宽度。最后，在曝光系统中提供具有光掩模的第二曝光处理。第二曝光过程使用具有较低分辨率的第二光源，其不足以解决每个第二条纹图案的第二宽度。

5. 发明申请

US20150194390A1 METHOD FOR FORMING CRACK STOP STRUCTURE 有权
标题翻译：形成断裂结构的方法
公开(公告)号：US20150194390A1
公开(公告)日：2015-07-09
申请号：US14591010
申请日：2015-01-07
申请人： NANYA TECHNOLOGY CORP.
发明人： Tse-Yao Huang , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： H01L23/00 , H01L21/762 , H01L21/311
CPC分类号： H01L23/562 , H01L21/311 , H01L21/561 , H01L21/76224 , H01L21/78 , H01L23/3178 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure includes a matrix, an integrated circuit and a scribe line. The matrix includes a scribe line region and a circuit region. The integrated circuit is disposed within the circuit region. The scribe line is disposed within the scribe line region and includes a crack stop trench which is disposed in the matrix and adjacent to the circuit region. The crack stop trench is parallel with one side of the circuit region and filled with a composite material in a form of a grid to form a crack stop structure.
摘要翻译：半导体结构包括矩阵，集成电路和划线。矩阵包括划线区域和电路区域。集成电路设置在电路区域内。划痕线设置在划线区域内并且包括设置在矩阵中并且邻近电路区域的裂缝停止沟槽。裂缝停止沟槽与电路区域的一侧平行，并填充有格栅形式的复合材料以形成裂纹停止结构。

6. 发明授权

US09070584B2 Buried digitline (BDL) access device and memory array 有权
标题翻译：埋地数字线（BDL）接入设备和存储器阵列
公开(公告)号：US09070584B2
公开(公告)日：2015-06-30
申请号：US13901592
申请日：2013-05-24
申请人： NANYA TECHNOLOGY CORP.
发明人： Shyam Surthi , Lars Heineck
IPC分类号： H01L27/108 , H01L23/522
CPC分类号： H01L27/10894 , H01L23/5225 , H01L27/10885 , H01L27/10891 , H01L2924/0002 , H01L2924/00
摘要： A memory array includes a plurality of digitline (DL) trenches extending along a first direction; a buried digitline between the DL trenches; a trench fill material layer sealing an air gap in each of the DL trenches; a plurality of wordline (WL) trenches extending along a second direction; an active chop (AC) trench disposed at one end of the buried digitline; a shield layer in the air gap; and a sidewall conductor around the sidewall of the AC trench.
摘要翻译：存储器阵列包括沿着第一方向延伸的多个数字线（DL）沟槽; DL沟槽之间的埋置数字线; 密封每个DL沟槽中的气隙的沟槽填充材料层; 沿着第二方向延伸的多个字线（WL）沟槽; 设置在埋地数字线一端的有源斩波（AC）沟槽; 气隙中的屏蔽层; 以及围绕AC沟槽的侧壁的侧壁导体。

7. 发明申请

US20150179822A1 SEMICONDUCTOR DEVICE CAPABLE OF REDUCING INFLUENCES OF ADJACENT WORD LINES OR ADJACENT TRANSISTORS AND FABRICATING METHOD THEREOF 有权
标题翻译：能够减少相邻字线或相邻晶体管的影响的半导体器件及其制造方法
公开(公告)号：US20150179822A1
公开(公告)日：2015-06-25
申请号：US14641439
申请日：2015-03-09
申请人： NANYA TECHNOLOGY CORP.
发明人： Shian-Jyh Lin
IPC分类号： H01L29/792 , H01L27/108
CPC分类号： H01L29/792 , H01L27/108 , H01L27/10823 , H01L27/10876 , H01L27/10891
摘要： A semiconductor device capable of reducing influences of adjacent word lines is provided in the present invention. The semiconductor device includes: a substrate, and a word line disposed in the substrate. The word line includes: a gate electrode, a gate dielectric layer disposed between the gate electrode and the substrate and at least one first charge trapping dielectric layer disposed adjacent to the gate electrode, wherein the first charge trapping dielectric layer comprises HfO2, TiO2, ZrO2, a germanium nanocrystal layer, an organic charge trapping material, HfSiOxNy, or MoSiOqNz.
摘要翻译：本发明提供能够减少相邻字线的影响的半导体装置。半导体器件包括：衬底和设置在衬底中的字线。字线包括：栅电极，设置在栅极电极和衬底之间的栅介质层和邻近栅电极设置的至少一个第一电荷俘获电介质层，其中第一电荷俘获电介质层包括HfO 2，TiO 2，ZrO 2 锗纳米晶层，有机电荷俘获材料，HfSiOxNy或MoSiOqNz。

8. 发明授权

US09041154B2 Contact structure and semiconductor memory device using the same 有权
标题翻译：接触结构和使用其的半导体存储器件
公开(公告)号：US09041154B2
公开(公告)日：2015-05-26
申请号：US13786463
申请日：2013-03-06
申请人： NANYA TECHNOLOGY CORP.
发明人： Chien-An Yu , Chih-Huang Wu
IPC分类号： H01L29/00 , H01L27/04 , H01L23/522 , H01L27/06 , H01L27/108 , H01L49/02
CPC分类号： H01L27/04 , H01L23/5223 , H01L27/0629 , H01L27/10852 , H01L27/10876 , H01L27/10888 , H01L27/10894 , H01L28/40 , H01L28/60 , H01L28/91 , H01L2924/0002 , Y10S257/906 , H01L2924/00
摘要： A semiconductor memory device includes a substrate having thereon a memory array region and a periphery circuit region. A first dielectric layer covers the memory array region and the periphery circuit region on the substrate. A second dielectric layer covers the memory array region and the periphery circuit region on the first dielectric layer. At least a capacitor structure is provided in the memory array region. The capacitor structure includes an electrode material layer embedded in the second dielectric layer. The semiconductor memory device further includes a contact structure comprising the electrode material layer.
摘要翻译：半导体存储器件包括其上具有存储器阵列区域和外围电路区域的衬底。第一电介质层覆盖衬底上的存储器阵列区域和外围电路区域。第二电介质层覆盖第一电介质层上的存储器阵列区域和外围电路区域。在存储器阵列区域中至少提供一个电容器结构。电容器结构包括嵌入在第二电介质层中的电极材料层。半导体存储器件还包括包括电极材料层的接触结构。

9. 发明授权

US08981426B2 Electrostatic discharge protection device 有权
标题翻译：静电放电保护装置
公开(公告)号：US08981426B2
公开(公告)日：2015-03-17
申请号：US14070433
申请日：2013-11-01
申请人： Nanya Technology Corp.
发明人： Wei-Fan Chen
IPC分类号： H01L29/66 , H01L27/02
CPC分类号： H01L27/0262 , H01L2924/0002 , H01L2924/00
摘要： The invention discloses an ESD protection circuit, including a P-type substrate; an N-well formed on the P-type substrate; a P-doped region formed on the N-well, wherein the P-doped region is electrically connected to an input/output terminal of a circuit under protection; a first N-doped region formed on the P-type substrate, the first N-doped region is electrically connected to a first node, and the P-doped region, the N-well, the P-type substrate, and the first N-doped region constitute a silicon controlled rectifier; and a second N-doped region formed on the N-well and electrically connected to a second node, wherein a part of the P-doped region and the second N-doped region constitute a discharging path, and when an ESD event occurs at the input/output terminal, the silicon controlled rectifier and the discharging path bypass electrostatic charges to the first and second nodes respectively.
摘要翻译：本发明公开了一种ESD保护电路，包括P型衬底; 在P型衬底上形成的N阱; 形成在所述N阱上的P掺杂区域，其中所述P掺杂区域电连接到保护电路的输入/输出端子; 形成在P型基板上的第一N掺杂区域，第一N掺杂区域电连接到第一节点，P掺杂区域，N阱，P型衬底和第一N掺杂区域掺杂区域构成可控硅整流器; 以及形成在所述N阱上并电连接到第二节点的第二N掺杂区域，其中所述P掺杂区域和所述第二N掺杂区域的一部分构成放电路径，并且当在所述第二N掺杂区域处发生ESD事件时输入/输出端子，可控硅整流器和放电路径分别将静电电荷分别连接到第一和第二节点。

10. 发明申请

US20150067197A1 DATA PATTERN GENERATION FOR I/O TRAINING AND CHARACTERIZATION 有权
标题翻译：用于I / O培训和表征的数据模式生成
公开(公告)号：US20150067197A1
公开(公告)日：2015-03-05
申请号：US14017277
申请日：2013-09-03
申请人： NANYA TECHNOLOGY CORP.
发明人： Timothy M. Hollis , Jeffrey P. Wright , Kang-Yong Kim , Eric J. Stave
IPC分类号： G06F3/06
CPC分类号： G06F13/00 , G06F3/061 , G06F3/0653 , G06F3/0683 , G06F12/00 , G11C11/40 , G11C29/022 , G11C29/50012
摘要： A memory structure that can perform characterization of output data paths without accessing the main memory array includes: a plurality of output data paths; a plurality of registers coupled to the output data paths. The registers include: at least a first pattern register and a second pattern register, for respectively storing a first data pattern and a second data pattern; and at least a first mapping register, for storing a plurality of binary values, wherein each binary value indicates whether the first data pattern or the second data pattern should be mapped to a corresponding output data path.
摘要翻译：可以在不访问主存储器阵列的情况下执行输出数据路径的表征的存储器结构包括：多个输出数据路径; 耦合到输出数据路径的多个寄存器。寄存器包括：至少第一模式寄存器和第二模式寄存器，用于分别存储第一数据模式和第二数据模式; 以及至少第一映射寄存器，用于存储多个二进制值，其中每个二进制值指示第一数据模式或第二数据模式是否应映射到相应的输出数据路径。

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